xref: /linux/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h (revision ab93e0dd72c37d378dd936f031ffb83ff2bd87ce)
1 /* SPDX-License-Identifier: MIT
2  *
3  * Copyright © 2023 Intel Corporation
4  */
5 
6 #ifndef __INTEL_CX0_PHY_REGS_H__
7 #define __INTEL_CX0_PHY_REGS_H__
8 
9 #include "intel_display_limits.h"
10 #include "intel_display_reg_defs.h"
11 
12 /* DDI Buffer Control */
13 #define _DDI_CLK_VALFREQ_A		0x64030
14 #define _DDI_CLK_VALFREQ_B		0x64130
15 #define DDI_CLK_VALFREQ(port)		_MMIO_PORT(port, _DDI_CLK_VALFREQ_A, _DDI_CLK_VALFREQ_B)
16 
17 /*
18  * Wrapper macro to convert from port number to the index used in some of the
19  * registers. For Display version 20 and above it converts the port number to a
20  * single range, starting with the TC offsets. When used together with
21  * _PICK_EVEN_2RANGES(idx, PORT_TC1, ...), this single range will be the second
22  * range. Example:
23  *
24  * PORT_TC1 -> PORT_TC1
25  * PORT_TC2 -> PORT_TC2
26  * PORT_TC3 -> PORT_TC3
27  * PORT_TC4 -> PORT_TC4
28  * PORT_A   -> PORT_TC4 + 1
29  * PORT_B   -> PORT_TC4 + 2
30  * ...
31  */
32 #define __xe2lpd_port_idx(port)						\
33 	(port >= PORT_TC1 ? port : PORT_TC4 + 1 + port - PORT_A)
34 
35 #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A		0x64040
36 #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B		0x64140
37 #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1		0x16F240
38 #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2		0x16F440
39 #define _XELPDP_PORT_M2P_MSGBUS_CTL(idx, lane)		_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
40 										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
41 										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
42 										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
43 										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4)
44 #define XELPDP_PORT_M2P_MSGBUS_CTL(i915__, port, lane)				\
45 	(DISPLAY_VER(i915__) >= 20 ?						\
46 	 _XELPDP_PORT_M2P_MSGBUS_CTL(__xe2lpd_port_idx(port), lane) :		\
47 	 _XELPDP_PORT_M2P_MSGBUS_CTL(port, lane))
48 #define   XELPDP_PORT_M2P_TRANSACTION_PENDING		REG_BIT(31)
49 #define   XELPDP_PORT_M2P_COMMAND_TYPE_MASK		REG_GENMASK(30, 27)
50 #define   XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED	REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x1)
51 #define   XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED	REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x2)
52 #define   XELPDP_PORT_M2P_COMMAND_READ			REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x3)
53 #define   XELPDP_PORT_M2P_DATA_MASK			REG_GENMASK(23, 16)
54 #define   XELPDP_PORT_M2P_DATA(val)			REG_FIELD_PREP(XELPDP_PORT_M2P_DATA_MASK, val)
55 #define   XELPDP_PORT_M2P_TRANSACTION_RESET		REG_BIT(15)
56 #define   XELPDP_PORT_M2P_ADDRESS_MASK			REG_GENMASK(11, 0)
57 #define   XELPDP_PORT_M2P_ADDRESS(val)			REG_FIELD_PREP(XELPDP_PORT_M2P_ADDRESS_MASK, val)
58 
59 #define _XELPDP_PORT_P2M_MSGBUS_STATUS(idx, lane)	_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
60 										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
61 										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
62 										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
63 										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4 + 8)
64 #define XELPDP_PORT_P2M_MSGBUS_STATUS(i915__, port, lane)			\
65 	(DISPLAY_VER(i915__) >= 20 ?						\
66 	 _XELPDP_PORT_P2M_MSGBUS_STATUS(__xe2lpd_port_idx(port), lane) :	\
67 	 _XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane))
68 #define   XELPDP_PORT_P2M_RESPONSE_READY		REG_BIT(31)
69 #define   XELPDP_PORT_P2M_COMMAND_TYPE_MASK		REG_GENMASK(30, 27)
70 #define   XELPDP_PORT_P2M_COMMAND_READ_ACK		0x4
71 #define   XELPDP_PORT_P2M_COMMAND_WRITE_ACK		0x5
72 #define   XELPDP_PORT_P2M_DATA_MASK			REG_GENMASK(23, 16)
73 #define   XELPDP_PORT_P2M_DATA(val)			REG_FIELD_PREP(XELPDP_PORT_P2M_DATA_MASK, val)
74 #define   XELPDP_PORT_P2M_ERROR_SET			REG_BIT(15)
75 
76 #define XELPDP_MSGBUS_TIMEOUT_SLOW			1
77 #define XELPDP_MSGBUS_TIMEOUT_FAST_US			2
78 #define XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US		3200
79 #define XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US		20
80 #define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US		100
81 #define XELPDP_PORT_RESET_START_TIMEOUT_US		5
82 #define XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US		100
83 #define XELPDP_PORT_RESET_END_TIMEOUT			15
84 #define XELPDP_REFCLK_ENABLE_TIMEOUT_US			1
85 
86 #define _XELPDP_PORT_BUF_CTL1_LN0_A			0x64004
87 #define _XELPDP_PORT_BUF_CTL1_LN0_B			0x64104
88 #define _XELPDP_PORT_BUF_CTL1_LN0_USBC1			0x16F200
89 #define _XELPDP_PORT_BUF_CTL1_LN0_USBC2			0x16F400
90 #define _XELPDP_PORT_BUF_CTL1(idx)			_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
91 										 _XELPDP_PORT_BUF_CTL1_LN0_A, \
92 										 _XELPDP_PORT_BUF_CTL1_LN0_B, \
93 										 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
94 										 _XELPDP_PORT_BUF_CTL1_LN0_USBC2))
95 #define XELPDP_PORT_BUF_CTL1(i915__, port)					\
96 	(DISPLAY_VER(i915__) >= 20 ?						\
97 	 _XELPDP_PORT_BUF_CTL1(__xe2lpd_port_idx(port)) :			\
98 	 _XELPDP_PORT_BUF_CTL1(port))
99 #define   XELPDP_PORT_BUF_D2D_LINK_ENABLE		REG_BIT(29)
100 #define   XELPDP_PORT_BUF_D2D_LINK_STATE		REG_BIT(28)
101 #define   XELPDP_PORT_BUF_SOC_PHY_READY			REG_BIT(24)
102 #define   XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK		REG_GENMASK(19, 18)
103 #define   XELPDP_PORT_BUF_PORT_DATA_10BIT		REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 0)
104 #define   XELPDP_PORT_BUF_PORT_DATA_20BIT		REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 1)
105 #define   XELPDP_PORT_BUF_PORT_DATA_40BIT		REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 2)
106 #define   XELPDP_PORT_REVERSAL				REG_BIT(16)
107 #define   XELPDP_PORT_BUF_IO_SELECT_TBT			REG_BIT(11)
108 #define   XELPDP_PORT_BUF_PHY_IDLE			REG_BIT(7)
109 #define   XELPDP_TC_PHY_OWNERSHIP			REG_BIT(6)
110 #define   XELPDP_TCSS_POWER_REQUEST			REG_BIT(5)
111 #define   XELPDP_TCSS_POWER_STATE			REG_BIT(4)
112 #define   XELPDP_PORT_WIDTH_MASK			REG_GENMASK(3, 1)
113 #define   XELPDP_PORT_WIDTH(width)			REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK, \
114 								       ((width) == 3 ? 4 : (width) - 1))
115 
116 #define _XELPDP_PORT_BUF_CTL2(idx)			_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
117 										 _XELPDP_PORT_BUF_CTL1_LN0_A, \
118 										 _XELPDP_PORT_BUF_CTL1_LN0_B, \
119 										 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
120 										 _XELPDP_PORT_BUF_CTL1_LN0_USBC2) + 4)
121 #define XELPDP_PORT_BUF_CTL2(i915__, port)					\
122 	(DISPLAY_VER(i915__) >= 20 ?						\
123 	 _XELPDP_PORT_BUF_CTL2(__xe2lpd_port_idx(port)) :			\
124 	 _XELPDP_PORT_BUF_CTL2(port))
125 #define   XELPDP_LANE_PIPE_RESET(lane)			_PICK(lane, REG_BIT(31), REG_BIT(30))
126 #define   XELPDP_LANE_PHY_CURRENT_STATUS(lane)		_PICK(lane, REG_BIT(29), REG_BIT(28))
127 #define   XELPDP_LANE_POWERDOWN_UPDATE(lane)		_PICK(lane, REG_BIT(25), REG_BIT(24))
128 #define   _XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK	REG_GENMASK(23, 20)
129 #define   _XELPDP_LANE0_POWERDOWN_NEW_STATE(val)	REG_FIELD_PREP(_XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK, val)
130 #define   _XELPDP_LANE1_POWERDOWN_NEW_STATE_MASK	REG_GENMASK(19, 16)
131 #define   _XELPDP_LANE1_POWERDOWN_NEW_STATE(val)	REG_FIELD_PREP(_XELPDP_LANE1_POWERDOWN_NEW_STATE_MASK, val)
132 #define   XELPDP_LANE_POWERDOWN_NEW_STATE(lane, val)	_PICK(lane, \
133 							      _XELPDP_LANE0_POWERDOWN_NEW_STATE(val), \
134 							      _XELPDP_LANE1_POWERDOWN_NEW_STATE(val))
135 #define   XELPDP_LANE_POWERDOWN_NEW_STATE_MASK		REG_GENMASK(3, 0)
136 #define   XELPDP_POWER_STATE_READY_MASK			REG_GENMASK(7, 4)
137 #define   XELPDP_POWER_STATE_READY(val)			REG_FIELD_PREP(XELPDP_POWER_STATE_READY_MASK, val)
138 
139 #define _XELPDP_PORT_BUF_CTL3(idx)			_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
140 										 _XELPDP_PORT_BUF_CTL1_LN0_A, \
141 										 _XELPDP_PORT_BUF_CTL1_LN0_B, \
142 										 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
143 										 _XELPDP_PORT_BUF_CTL1_LN0_USBC2) + 8)
144 #define XELPDP_PORT_BUF_CTL3(i915__, port)					\
145 	(DISPLAY_VER(i915__) >= 20 ?						\
146 	 _XELPDP_PORT_BUF_CTL3(__xe2lpd_port_idx(port)) :			\
147 	 _XELPDP_PORT_BUF_CTL3(port))
148 #define   XELPDP_PLL_LANE_STAGGERING_DELAY_MASK		REG_GENMASK(15, 8)
149 #define   XELPDP_PLL_LANE_STAGGERING_DELAY(val)		REG_FIELD_PREP(XELPDP_PLL_LANE_STAGGERING_DELAY_MASK, val)
150 #define   XELPDP_POWER_STATE_ACTIVE_MASK		REG_GENMASK(3, 0)
151 #define   XELPDP_POWER_STATE_ACTIVE(val)		REG_FIELD_PREP(XELPDP_POWER_STATE_ACTIVE_MASK, val)
152 #define   CX0_P0_STATE_ACTIVE				0x0
153 #define   CX0_P2_STATE_READY				0x2
154 #define   CX0_P2PG_STATE_DISABLE			0x9
155 #define   CX0_P4PG_STATE_DISABLE			0xC
156 #define   CX0_P2_STATE_RESET				0x2
157 
158 #define _XELPDP_PORT_MSGBUS_TIMER_LN0_A			0x640d8
159 #define _XELPDP_PORT_MSGBUS_TIMER_LN0_B			0x641d8
160 #define _XELPDP_PORT_MSGBUS_TIMER_LN0_USBC1		0x16f258
161 #define _XELPDP_PORT_MSGBUS_TIMER_LN0_USBC2		0x16f458
162 #define _XELPDP_PORT_MSGBUS_TIMER(port, lane)		_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
163 										 _XELPDP_PORT_MSGBUS_TIMER_LN0_A, \
164 										 _XELPDP_PORT_MSGBUS_TIMER_LN0_B, \
165 										 _XELPDP_PORT_MSGBUS_TIMER_LN0_USBC1, \
166 										 _XELPDP_PORT_MSGBUS_TIMER_LN0_USBC2) + (lane) * 4)
167 #define XELPDP_PORT_MSGBUS_TIMER(i915__, port, lane)				\
168 	(DISPLAY_VER(i915__) >= 20 ?						\
169 	 _XELPDP_PORT_MSGBUS_TIMER(__xe2lpd_port_idx(port), lane) :		\
170 	 _XELPDP_PORT_MSGBUS_TIMER(port, lane))
171 #define   XELPDP_PORT_MSGBUS_TIMER_TIMED_OUT		REG_BIT(31)
172 #define   XELPDP_PORT_MSGBUS_TIMER_VAL_MASK		REG_GENMASK(23, 0)
173 #define   XELPDP_PORT_MSGBUS_TIMER_VAL			REG_FIELD_PREP(XELPDP_PORT_MSGBUS_TIMER_VAL_MASK, 0xa000)
174 
175 #define _XELPDP_PORT_CLOCK_CTL_A			0x640E0
176 #define _XELPDP_PORT_CLOCK_CTL_B			0x641E0
177 #define _XELPDP_PORT_CLOCK_CTL_USBC1			0x16F260
178 #define _XELPDP_PORT_CLOCK_CTL_USBC2			0x16F460
179 #define _XELPDP_PORT_CLOCK_CTL(idx)			_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
180 										 _XELPDP_PORT_CLOCK_CTL_A, \
181 										 _XELPDP_PORT_CLOCK_CTL_B, \
182 										 _XELPDP_PORT_CLOCK_CTL_USBC1, \
183 										 _XELPDP_PORT_CLOCK_CTL_USBC2))
184 #define XELPDP_PORT_CLOCK_CTL(i915__, port)					\
185 	(DISPLAY_VER(i915__) >= 20 ?						\
186 	 _XELPDP_PORT_CLOCK_CTL(__xe2lpd_port_idx(port)) :			\
187 	 _XELPDP_PORT_CLOCK_CTL(port))
188 #define   XELPDP_LANE_PCLK_PLL_REQUEST(lane)		REG_BIT(31 - ((lane) * 4))
189 #define   XELPDP_LANE_PCLK_PLL_ACK(lane)		REG_BIT(30 - ((lane) * 4))
190 #define   XELPDP_LANE_PCLK_REFCLK_REQUEST(lane)		REG_BIT(29 - ((lane) * 4))
191 #define   XELPDP_LANE_PCLK_REFCLK_ACK(lane)		REG_BIT(28 - ((lane) * 4))
192 
193 #define   XELPDP_TBT_CLOCK_REQUEST			REG_BIT(19)
194 #define   XELPDP_TBT_CLOCK_ACK				REG_BIT(18)
195 #define   _XELPDP_DDI_CLOCK_SELECT_MASK			REG_GENMASK(15, 12)
196 #define   _XE3_DDI_CLOCK_SELECT_MASK			REG_GENMASK(16, 12)
197 #define   XELPDP_DDI_CLOCK_SELECT_MASK(display)		(DISPLAY_VER(display) >= 30 ? \
198 							 _XE3_DDI_CLOCK_SELECT_MASK : _XELPDP_DDI_CLOCK_SELECT_MASK)
199 #define   XELPDP_DDI_CLOCK_SELECT_PREP(display, val)	(DISPLAY_VER(display) >= 30 ? \
200 							 REG_FIELD_PREP(_XE3_DDI_CLOCK_SELECT_MASK, (val)) : \
201 							 REG_FIELD_PREP(_XELPDP_DDI_CLOCK_SELECT_MASK, (val)))
202 #define   XELPDP_DDI_CLOCK_SELECT_GET(display, val)	(DISPLAY_VER(display) >= 30 ? \
203 							 REG_FIELD_GET(_XE3_DDI_CLOCK_SELECT_MASK, (val)) : \
204 							 REG_FIELD_GET(_XELPDP_DDI_CLOCK_SELECT_MASK, (val)))
205 
206 #define   XELPDP_DDI_CLOCK_SELECT_NONE			0x0
207 #define   XELPDP_DDI_CLOCK_SELECT_MAXPCLK		0x8
208 #define   XELPDP_DDI_CLOCK_SELECT_DIV18CLK		0x9
209 #define   XELPDP_DDI_CLOCK_SELECT_TBT_162		0xc
210 #define   XELPDP_DDI_CLOCK_SELECT_TBT_270		0xd
211 #define   XELPDP_DDI_CLOCK_SELECT_TBT_540		0xe
212 #define   XELPDP_DDI_CLOCK_SELECT_TBT_810		0xf
213 #define   XELPDP_DDI_CLOCK_SELECT_TBT_312_5		0x18
214 #define   XELPDP_DDI_CLOCK_SELECT_TBT_625		0x19
215 #define   XELPDP_FORWARD_CLOCK_UNGATE			REG_BIT(10)
216 #define   XELPDP_LANE1_PHY_CLOCK_SELECT			REG_BIT(8)
217 #define   XELPDP_SSC_ENABLE_PLLA			REG_BIT(1)
218 #define   XELPDP_SSC_ENABLE_PLLB			REG_BIT(0)
219 
220 #define TCSS_DISP_MAILBOX_IN_CMD		_MMIO(0x161300)
221 #define   TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY	REG_BIT(31)
222 #define   TCSS_DISP_MAILBOX_IN_CMD_CMD_MASK	REG_GENMASK(7, 0)
223 #define   TCSS_DISP_MAILBOX_IN_CMD_DATA(val)	REG_FIELD_PREP(TCSS_DISP_MAILBOX_IN_CMD_CMD_MASK, val)
224 
225 #define TCSS_DISP_MAILBOX_IN_DATA		_MMIO(0x161304)
226 
227 /* C10 Vendor Registers */
228 #define PHY_C10_VDR_PLL(idx)		(0xC00 + (idx))
229 #define   C10_PLL0_SSC_EN		REG_BIT8(0)
230 #define   C10_PLL0_DIVCLK_EN		REG_BIT8(1)
231 #define   C10_PLL0_DIV5CLK_EN		REG_BIT8(2)
232 #define   C10_PLL0_WORDDIV2_EN		REG_BIT8(3)
233 #define   C10_PLL0_FRACEN		REG_BIT8(4)
234 #define   C10_PLL0_PMIX_EN		REG_BIT8(5)
235 #define   C10_PLL0_ANA_FREQ_VCO_MASK	REG_GENMASK8(7, 6)
236 #define   C10_PLL1_DIV_MULTIPLIER_MASK	REG_GENMASK8(7, 0)
237 #define   C10_PLL2_MULTIPLIERL_MASK	REG_GENMASK8(7, 0)
238 #define   C10_PLL3_MULTIPLIERH_MASK	REG_GENMASK8(3, 0)
239 #define   C10_PLL8_SSC_UP_SPREAD	REG_BIT8(5)
240 #define   C10_PLL9_FRACN_DENL_MASK	REG_GENMASK8(7, 0)
241 #define   C10_PLL10_FRACN_DENH_MASK	REG_GENMASK8(7, 0)
242 #define   C10_PLL11_FRACN_QUOT_L_MASK	REG_GENMASK8(7, 0)
243 #define   C10_PLL12_FRACN_QUOT_H_MASK	REG_GENMASK8(7, 0)
244 #define   C10_PLL13_FRACN_REM_L_MASK	REG_GENMASK8(7, 0)
245 #define   C10_PLL14_FRACN_REM_H_MASK	REG_GENMASK8(7, 0)
246 #define   C10_PLL15_TXCLKDIV_MASK	REG_GENMASK8(2, 0)
247 #define   C10_PLL15_HDMIDIV_MASK	REG_GENMASK8(5, 3)
248 #define   C10_PLL15_PIXELCLKDIV_MASK	REG_GENMASK8(7, 6)
249 #define   C10_PLL16_ANA_CPINT		REG_GENMASK8(6, 0)
250 #define   C10_PLL16_ANA_CPINTGS_L	REG_BIT8(7)
251 #define   C10_PLL17_ANA_CPINTGS_H_MASK	REG_GENMASK8(5, 0)
252 #define   C10_PLL17_ANA_CPPROP_L_MASK	REG_GENMASK8(7, 6)
253 #define   C10_PLL18_ANA_CPPROP_H_MASK	REG_GENMASK8(4, 0)
254 #define   C10_PLL18_ANA_CPPROPGS_L_MASK	REG_GENMASK8(7, 5)
255 #define   C10_PLL19_ANA_CPPROPGS_H_MASK	REG_GENMASK8(3, 0)
256 #define   C10_PLL19_ANA_V2I_MASK	REG_GENMASK8(5, 4)
257 
258 #define PHY_C10_VDR_CMN(idx)		(0xC20 + (idx))
259 #define   C10_CMN0_REF_RANGE		REG_FIELD_PREP(REG_GENMASK(4, 0), 1)
260 #define   C10_CMN0_REF_CLK_MPLLB_DIV	REG_FIELD_PREP(REG_GENMASK(7, 5), 1)
261 #define   C10_CMN3_TXVBOOST_MASK	REG_GENMASK8(7, 5)
262 #define   C10_CMN3_TXVBOOST(val)	REG_FIELD_PREP8(C10_CMN3_TXVBOOST_MASK, val)
263 #define PHY_C10_VDR_TX(idx)		(0xC30 + (idx))
264 #define   C10_TX0_TX_MPLLB_SEL		REG_BIT(4)
265 #define   C10_TX1_TERMCTL_MASK		REG_GENMASK8(7, 5)
266 #define   C10_TX1_TERMCTL(val)		REG_FIELD_PREP8(C10_TX1_TERMCTL_MASK, val)
267 #define PHY_C10_VDR_CONTROL(idx)	(0xC70 + (idx) - 1)
268 #define   C10_VDR_CTRL_MSGBUS_ACCESS	REG_BIT8(2)
269 #define   C10_VDR_CTRL_MASTER_LANE	REG_BIT8(1)
270 #define   C10_VDR_CTRL_UPDATE_CFG	REG_BIT8(0)
271 #define PHY_C10_VDR_CUSTOM_WIDTH	0xD02
272 #define   C10_VDR_CUSTOM_WIDTH_MASK    REG_GENMASK(1, 0)
273 #define   C10_VDR_CUSTOM_WIDTH_8_10    REG_FIELD_PREP(C10_VDR_CUSTOM_WIDTH_MASK, 0)
274 #define PHY_C10_VDR_OVRD		0xD71
275 #define   PHY_C10_VDR_OVRD_TX1		REG_BIT8(0)
276 #define   PHY_C10_VDR_OVRD_TX2		REG_BIT8(2)
277 #define PHY_C10_VDR_PRE_OVRD_TX1	0xD80
278 #define C10_PHY_OVRD_LEVEL_MASK		REG_GENMASK8(5, 0)
279 #define C10_PHY_OVRD_LEVEL(val)		REG_FIELD_PREP8(C10_PHY_OVRD_LEVEL_MASK, val)
280 #define PHY_CX0_VDROVRD_CTL(lane, tx, control)				\
281 					(PHY_C10_VDR_PRE_OVRD_TX1 +	\
282 					 ((lane) ^ (tx)) * 0x10 + (control))
283 
284 /* PIPE SPEC Defined Registers */
285 #define PHY_CX0_TX_CONTROL(tx, control)	(0x400 + ((tx) - 1) * 0x200 + (control))
286 #define   CONTROL2_DISABLE_SINGLE_TX	REG_BIT(6)
287 
288 #define PHY_CMN1_CONTROL(tx, control)	(0x800 + ((tx) - 1) * 0x200 + (control))
289 #define   CONTROL0_MAC_TRANSMIT_LFPS	REG_BIT(1)
290 
291 /* C20 Registers */
292 #define PHY_C20_WR_ADDRESS_L		0xC02
293 #define PHY_C20_WR_ADDRESS_H		0xC03
294 #define PHY_C20_WR_DATA_L		0xC04
295 #define PHY_C20_WR_DATA_H		0xC05
296 #define PHY_C20_RD_ADDRESS_L		0xC06
297 #define PHY_C20_RD_ADDRESS_H		0xC07
298 #define PHY_C20_RD_DATA_L		0xC08
299 #define PHY_C20_RD_DATA_H		0xC09
300 #define PHY_C20_VDR_CUSTOM_SERDES_RATE	0xD00
301 #define PHY_C20_VDR_HDMI_RATE		0xD01
302 #define   PHY_C20_CONTEXT_TOGGLE	REG_BIT8(0)
303 #define   PHY_C20_CUSTOM_SERDES_MASK	REG_GENMASK8(4, 1)
304 #define   PHY_C20_CUSTOM_SERDES(val)	REG_FIELD_PREP8(PHY_C20_CUSTOM_SERDES_MASK, val)
305 #define PHY_C20_VDR_CUSTOM_WIDTH	0xD02
306 #define   PHY_C20_CUSTOM_WIDTH_MASK	REG_GENMASK(1, 0)
307 #define   PHY_C20_CUSTOM_WIDTH(val)	REG_FIELD_PREP8(PHY_C20_CUSTOM_WIDTH_MASK, val)
308 
309 #define _MTL_C20_A_TX_CNTX_CFG	0xCF2E
310 #define _MTL_C20_B_TX_CNTX_CFG	0xCF2A
311 #define _MTL_C20_A_CMN_CNTX_CFG	0xCDAA
312 #define _MTL_C20_B_CMN_CNTX_CFG	0xCDA5
313 #define _MTL_C20_A_MPLLA_CFG	0xCCF0
314 #define _MTL_C20_B_MPLLA_CFG	0xCCE5
315 #define _MTL_C20_A_MPLLB_CFG	0xCB5A
316 #define _MTL_C20_B_MPLLB_CFG	0xCB4E
317 
318 #define _XE2HPD_C20_A_TX_CNTX_CFG	0xCF5E
319 #define _XE2HPD_C20_B_TX_CNTX_CFG	0xCF5A
320 #define _XE2HPD_C20_A_CMN_CNTX_CFG	0xCE8E
321 #define _XE2HPD_C20_B_CMN_CNTX_CFG	0xCE89
322 #define _XE2HPD_C20_A_MPLLA_CFG		0xCE58
323 #define _XE2HPD_C20_B_MPLLA_CFG		0xCE4D
324 #define _XE2HPD_C20_A_MPLLB_CFG		0xCCC2
325 #define _XE2HPD_C20_B_MPLLB_CFG		0xCCB6
326 
327 #define _IS_XE2HPD_C20(i915)	(DISPLAY_VERx100(i915) == 1401)
328 
329 #define PHY_C20_A_TX_CNTX_CFG(i915, idx) \
330 		((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_TX_CNTX_CFG : _MTL_C20_A_TX_CNTX_CFG) - (idx))
331 #define PHY_C20_B_TX_CNTX_CFG(i915, idx) \
332 		((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_B_TX_CNTX_CFG : _MTL_C20_B_TX_CNTX_CFG) - (idx))
333 #define   C20_PHY_TX_RATE		REG_GENMASK(2, 0)
334 #define   C20_PHY_TX_MISC_MASK		REG_GENMASK16(7, 0)
335 #define   C20_PHY_TX_MISC(val)		REG_FIELD_PREP16(C20_PHY_TX_MISC_MASK, (val))
336 #define   C20_PHY_TX_DCC_CAL_RANGE_MASK	REG_GENMASK16(11, 8)
337 #define   C20_PHY_TX_DCC_CAL_RANGE(val) \
338 		REG_FIELD_PREP16(C20_PHY_TX_DCC_CAL_RANGE_MASK, (val))
339 #define   C20_PHY_TX_DCC_BYPASS	REG_BIT(12)
340 #define   C20_PHY_TX_TERM_CTL_MASK	REG_GENMASK16(15, 13)
341 #define   C20_PHY_TX_TERM_CTL(val)	REG_FIELD_PREP16(C20_PHY_TX_TERM_CTL_MASK, (val))
342 
343 #define PHY_C20_A_CMN_CNTX_CFG(i915, idx) \
344 		((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_CMN_CNTX_CFG : _MTL_C20_A_CMN_CNTX_CFG) - (idx))
345 #define PHY_C20_B_CMN_CNTX_CFG(i915, idx) \
346 		((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_B_CMN_CNTX_CFG : _MTL_C20_B_CMN_CNTX_CFG) - (idx))
347 #define PHY_C20_A_MPLLA_CNTX_CFG(i915, idx) \
348 		((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_MPLLA_CFG : _MTL_C20_A_MPLLA_CFG) - (idx))
349 #define PHY_C20_B_MPLLA_CNTX_CFG(i915, idx) \
350 		((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_B_MPLLA_CFG : _MTL_C20_B_MPLLA_CFG) - (idx))
351 #define   C20_MPLLA_FRACEN		REG_BIT(14)
352 #define   C20_FB_CLK_DIV4_EN		REG_BIT(13)
353 #define   C20_MPLLA_TX_CLK_DIV_MASK	REG_GENMASK(10, 8)
354 
355 #define PHY_C20_A_MPLLB_CNTX_CFG(i915, idx) \
356 		((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_MPLLB_CFG : _MTL_C20_A_MPLLB_CFG) - (idx))
357 #define PHY_C20_B_MPLLB_CNTX_CFG(i915, idx) \
358 		((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_B_MPLLB_CFG : _MTL_C20_B_MPLLB_CFG) - (idx))
359 
360 #define   C20_MPLLB_TX_CLK_DIV_MASK	REG_GENMASK(15, 13)
361 #define   C20_MPLLB_FRACEN		REG_BIT(13)
362 #define   C20_REF_CLK_MPLLB_DIV_MASK	REG_GENMASK(12, 10)
363 #define   C20_MULTIPLIER_MASK		REG_GENMASK(11, 0)
364 #define   C20_PHY_USE_MPLLB		REG_BIT(7)
365 
366 /* C20 Phy VSwing Masks */
367 #define C20_PHY_VSWING_PREEMPH_MASK	REG_GENMASK8(5, 0)
368 #define C20_PHY_VSWING_PREEMPH(val)	REG_FIELD_PREP8(C20_PHY_VSWING_PREEMPH_MASK, val)
369 
370 #define RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(idx) (0x303D + (idx))
371 
372 /* C20 HDMI computed pll definitions */
373 #define REFCLK_38_4_MHZ		38400000
374 #define CLOCK_4999MHZ		4999999999
375 #define CLOCK_9999MHZ		9999999999
376 #define DATARATE_3000000000	3000000000
377 #define DATARATE_3500000000	3500000000
378 #define DATARATE_4000000000	4000000000
379 #define MPLL_FRACN_DEN		0xFFFF
380 
381 #define SSC_UP_SPREAD		REG_BIT16(9)
382 #define WORD_CLK_DIV		REG_BIT16(8)
383 
384 #define MPLL_TX_CLK_DIV(val)	REG_FIELD_PREP16(C20_MPLLB_TX_CLK_DIV_MASK, val)
385 #define MPLL_MULTIPLIER(val)	REG_FIELD_PREP16(C20_MULTIPLIER_MASK, val)
386 
387 #define MPLLB_ANA_FREQ_VCO_0	0
388 #define MPLLB_ANA_FREQ_VCO_1	1
389 #define MPLLB_ANA_FREQ_VCO_2	2
390 #define MPLLB_ANA_FREQ_VCO_3	3
391 #define MPLLB_ANA_FREQ_VCO_MASK	REG_GENMASK16(15, 14)
392 #define MPLLB_ANA_FREQ_VCO(val)	REG_FIELD_PREP16(MPLLB_ANA_FREQ_VCO_MASK, val)
393 
394 #define MPLL_DIV_MULTIPLIER_MASK	REG_GENMASK16(7, 0)
395 #define MPLL_DIV_MULTIPLIER(val)	REG_FIELD_PREP16(MPLL_DIV_MULTIPLIER_MASK, val)
396 
397 #define CAL_DAC_CODE_31		31
398 #define CAL_DAC_CODE_MASK	REG_GENMASK16(14, 10)
399 #define CAL_DAC_CODE(val)	REG_FIELD_PREP16(CAL_DAC_CODE_MASK, val)
400 
401 #define CP_INT_GS_28		28
402 #define CP_INT_GS_MASK		REG_GENMASK16(6, 0)
403 #define CP_INT_GS(val)		REG_FIELD_PREP16(CP_INT_GS_MASK, val)
404 
405 #define CP_PROP_GS_30		30
406 #define CP_PROP_GS_MASK		REG_GENMASK16(13, 7)
407 #define CP_PROP_GS(val)		REG_FIELD_PREP16(CP_PROP_GS_MASK, val)
408 
409 #define CP_INT_6		6
410 #define CP_INT_MASK		REG_GENMASK16(6, 0)
411 #define CP_INT(val)		REG_FIELD_PREP16(CP_INT_MASK, val)
412 
413 #define CP_PROP_20		20
414 #define CP_PROP_MASK		REG_GENMASK16(13, 7)
415 #define CP_PROP(val)		REG_FIELD_PREP16(CP_PROP_MASK, val)
416 
417 #define V2I_2			2
418 #define V2I_MASK		REG_GENMASK16(15, 14)
419 #define V2I(val)		REG_FIELD_PREP16(V2I_MASK, val)
420 
421 #define HDMI_DIV_1		1
422 #define HDMI_DIV_MASK		REG_GENMASK16(2, 0)
423 #define HDMI_DIV(val)		REG_FIELD_PREP16(HDMI_DIV_MASK, val)
424 
425 #define PICA_PHY_CONFIG_CONTROL		_MMIO(0x16FE68)
426 #define   EDP_ON_TYPEC			REG_BIT(31)
427 
428 #endif /* __INTEL_CX0_REG_DEFS_H__ */
429