xref: /linux/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/internal.h (revision 983d01b2ce0ac688bb42489f33a29a02274366d5) !
1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /* Copyright (c) 2024 NVIDIA Corporation & Affiliates */
3 
4 #ifndef HWS_INTERNAL_H_
5 #define HWS_INTERNAL_H_
6 
7 #include <linux/mlx5/transobj.h>
8 #include <linux/mlx5/vport.h>
9 #include "fs_core.h"
10 #include "wq.h"
11 #include "lib/mlx5.h"
12 
13 #include "prm.h"
14 #include "mlx5hws.h"
15 #include "pool.h"
16 #include "vport.h"
17 #include "context.h"
18 #include "table.h"
19 #include "send.h"
20 #include "action_ste_pool.h"
21 #include "rule.h"
22 #include "cmd.h"
23 #include "action.h"
24 #include "definer.h"
25 #include "matcher.h"
26 #include "debug.h"
27 #include "pat_arg.h"
28 #include "bwc.h"
29 #include "bwc_complex.h"
30 
31 #define W_SIZE		2
32 #define DW_SIZE		4
33 #define BITS_IN_BYTE	8
34 #define BITS_IN_DW	(BITS_IN_BYTE * DW_SIZE)
35 
36 #define IS_BIT_SET(_value, _bit) ((_value) & (1ULL << (_bit)))
37 
38 #define mlx5hws_err(ctx, arg...) mlx5_core_err((ctx)->mdev, ##arg)
39 #define mlx5hws_info(ctx, arg...) mlx5_core_info((ctx)->mdev, ##arg)
40 #define mlx5hws_dbg(ctx, arg...) mlx5_core_dbg((ctx)->mdev, ##arg)
41 
42 #define MLX5HWS_TABLE_TYPE_BASE 2
43 
is_mem_zero(const u8 * mem,size_t size)44 static inline bool is_mem_zero(const u8 *mem, size_t size)
45 {
46 	if (unlikely(!size)) {
47 		pr_warn("HWS: invalid buffer of size 0 in %s\n", __func__);
48 		return true;
49 	}
50 
51 	return (*mem == 0) && memcmp(mem, mem + 1, size - 1) == 0;
52 }
53 
align(unsigned long val,unsigned long align)54 static inline unsigned long align(unsigned long val, unsigned long align)
55 {
56 	return (val + align - 1) & ~(align - 1);
57 }
58 
59 #endif /* HWS_INTERNAL_H_ */
60