1 /*
2  *  linux/include/asm-arm/arch-pxa/balloon3.h
3  *
4  *  Authors:	Nick Bane and Wookey
5  *  Created:	Oct, 2005
6  *  Copyright:	Toby Churchill Ltd
7  *  Cribbed from mainstone.c, by Nicholas Pitre
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2 as
11  * published by the Free Software Foundation.
12  */
13 
14 #ifndef ASM_ARCH_BALLOON3_H
15 #define ASM_ARCH_BALLOON3_H
16 
17 enum balloon3_features {
18 	BALLOON3_FEATURE_OHCI,
19 	BALLOON3_FEATURE_MMC,
20 	BALLOON3_FEATURE_CF,
21 	BALLOON3_FEATURE_AUDIO,
22 	BALLOON3_FEATURE_TOPPOLY,
23 };
24 
25 #define BALLOON3_FPGA_PHYS	PXA_CS4_PHYS
26 #define BALLOON3_FPGA_VIRT	IOMEM(0xf1000000)	/* as per balloon2 */
27 #define BALLOON3_FPGA_LENGTH	0x01000000
28 
29 #define	BALLOON3_FPGA_SETnCLR		(0x1000)
30 
31 /* FPGA / CPLD registers for CF socket */
32 #define	BALLOON3_CF_STATUS_REG		(BALLOON3_FPGA_VIRT + 0x00e00008)
33 #define	BALLOON3_CF_CONTROL_REG		(BALLOON3_FPGA_VIRT + 0x00e00008)
34 /* FPGA / CPLD version register */
35 #define	BALLOON3_FPGA_VER		(BALLOON3_FPGA_VIRT + 0x00e0001c)
36 /* FPGA / CPLD registers for NAND flash */
37 #define	BALLOON3_NAND_BASE		(PXA_CS4_PHYS + 0x00e00000)
38 #define	BALLOON3_NAND_IO_REG		(BALLOON3_FPGA_VIRT + 0x00e00000)
39 #define	BALLOON3_NAND_CONTROL2_REG	(BALLOON3_FPGA_VIRT + 0x00e00010)
40 #define	BALLOON3_NAND_STAT_REG		(BALLOON3_FPGA_VIRT + 0x00e00014)
41 #define	BALLOON3_NAND_CONTROL_REG	(BALLOON3_FPGA_VIRT + 0x00e00014)
42 
43 /* fpga/cpld interrupt control register */
44 #define BALLOON3_INT_CONTROL_REG	(BALLOON3_FPGA_VIRT + 0x00e0000C)
45 #define BALLOON3_VERSION_REG		(BALLOON3_FPGA_VIRT + 0x00e0001c)
46 
47 #define BALLOON3_SAMOSA_ADDR_REG	(BALLOON3_FPGA_VIRT + 0x00c00000)
48 #define BALLOON3_SAMOSA_DATA_REG	(BALLOON3_FPGA_VIRT + 0x00c00004)
49 #define BALLOON3_SAMOSA_STATUS_REG	(BALLOON3_FPGA_VIRT + 0x00c0001c)
50 
51 /* CF Status Register bits (read-only) bits */
52 #define BALLOON3_CF_nIRQ		(1 << 0)
53 #define BALLOON3_CF_nSTSCHG_BVD1	(1 << 1)
54 
55 /* CF Control Set Register bits / CF Control Clear Register bits (write-only) */
56 #define BALLOON3_CF_RESET		(1 << 0)
57 #define BALLOON3_CF_ENABLE		(1 << 1)
58 #define BALLOON3_CF_ADD_ENABLE		(1 << 2)
59 
60 /* CF Interrupt sources */
61 #define BALLOON3_BP_CF_NRDY_IRQ		BALLOON3_IRQ(0)
62 #define BALLOON3_BP_NSTSCHG_IRQ		BALLOON3_IRQ(1)
63 
64 /* NAND Control register */
65 #define	BALLOON3_NAND_CONTROL_FLWP	(1 << 7)
66 #define	BALLOON3_NAND_CONTROL_FLSE	(1 << 6)
67 #define	BALLOON3_NAND_CONTROL_FLCE3	(1 << 5)
68 #define	BALLOON3_NAND_CONTROL_FLCE2	(1 << 4)
69 #define	BALLOON3_NAND_CONTROL_FLCE1	(1 << 3)
70 #define	BALLOON3_NAND_CONTROL_FLCE0	(1 << 2)
71 #define	BALLOON3_NAND_CONTROL_FLALE	(1 << 1)
72 #define	BALLOON3_NAND_CONTROL_FLCLE	(1 << 0)
73 
74 /* NAND Status register */
75 #define	BALLOON3_NAND_STAT_RNB		(1 << 0)
76 
77 /* NAND Control2 register */
78 #define	BALLOON3_NAND_CONTROL2_16BIT	(1 << 0)
79 
80 /* GPIOs for irqs */
81 #define BALLOON3_GPIO_AUX_NIRQ		(94)
82 #define BALLOON3_GPIO_CODEC_IRQ		(95)
83 
84 /* Timer and Idle LED locations */
85 #define BALLOON3_GPIO_LED_NAND		(9)
86 #define BALLOON3_GPIO_LED_IDLE		(10)
87 
88 /* backlight control */
89 #define BALLOON3_GPIO_RUN_BACKLIGHT	(99)
90 
91 #define BALLOON3_GPIO_S0_CD		(105)
92 
93 /* NAND */
94 #define BALLOON3_GPIO_RUN_NAND		(102)
95 
96 /* PCF8574A Leds */
97 #define	BALLOON3_PCF_GPIO_BASE		160
98 #define	BALLOON3_PCF_GPIO_LED0		(BALLOON3_PCF_GPIO_BASE + 0)
99 #define	BALLOON3_PCF_GPIO_LED1		(BALLOON3_PCF_GPIO_BASE + 1)
100 #define	BALLOON3_PCF_GPIO_LED2		(BALLOON3_PCF_GPIO_BASE + 2)
101 #define	BALLOON3_PCF_GPIO_LED3		(BALLOON3_PCF_GPIO_BASE + 3)
102 #define	BALLOON3_PCF_GPIO_LED4		(BALLOON3_PCF_GPIO_BASE + 4)
103 #define	BALLOON3_PCF_GPIO_LED5		(BALLOON3_PCF_GPIO_BASE + 5)
104 #define	BALLOON3_PCF_GPIO_LED6		(BALLOON3_PCF_GPIO_BASE + 6)
105 #define	BALLOON3_PCF_GPIO_LED7		(BALLOON3_PCF_GPIO_BASE + 7)
106 
107 /* FPGA Interrupt Mask/Acknowledge Register */
108 #define BALLOON3_INT_S0_IRQ		(1 << 0)  /* PCMCIA 0 IRQ */
109 #define BALLOON3_INT_S0_STSCHG		(1 << 1)  /* PCMCIA 0 status changed */
110 
111 /* CPLD (and FPGA) interface definitions */
112 #define CPLD_LCD0_DATA_SET             0x00
113 #define CPLD_LCD0_DATA_CLR             0x10
114 #define CPLD_LCD0_COMMAND_SET          0x01
115 #define CPLD_LCD0_COMMAND_CLR          0x11
116 #define CPLD_LCD1_DATA_SET             0x02
117 #define CPLD_LCD1_DATA_CLR             0x12
118 #define CPLD_LCD1_COMMAND_SET          0x03
119 #define CPLD_LCD1_COMMAND_CLR          0x13
120 
121 #define CPLD_MISC_SET                  0x07
122 #define CPLD_MISC_CLR                  0x17
123 #define CPLD_MISC_LOON_NRESET_BIT      0
124 #define CPLD_MISC_LOON_UNSUSP_BIT      1
125 #define CPLD_MISC_RUN_5V_BIT           2
126 #define CPLD_MISC_CHG_D0_BIT           3
127 #define CPLD_MISC_CHG_D1_BIT           4
128 #define CPLD_MISC_DAC_NCS_BIT          5
129 
130 #define CPLD_LCD_SET                   0x08
131 #define CPLD_LCD_CLR                   0x18
132 #define CPLD_LCD_BACKLIGHT_EN_0_BIT    0
133 #define CPLD_LCD_BACKLIGHT_EN_1_BIT    1
134 #define CPLD_LCD_LED_RED_BIT           4
135 #define CPLD_LCD_LED_GREEN_BIT         5
136 #define CPLD_LCD_NRESET_BIT            7
137 
138 #define CPLD_LCD_RO_SET                0x09
139 #define CPLD_LCD_RO_CLR                0x19
140 #define CPLD_LCD_RO_LCD0_nWAIT_BIT     0
141 #define CPLD_LCD_RO_LCD1_nWAIT_BIT     1
142 
143 #define CPLD_SERIAL_SET                0x0a
144 #define CPLD_SERIAL_CLR                0x1a
145 #define CPLD_SERIAL_GSM_RI_BIT         0
146 #define CPLD_SERIAL_GSM_CTS_BIT        1
147 #define CPLD_SERIAL_GSM_DTR_BIT        2
148 #define CPLD_SERIAL_LPR_CTS_BIT        3
149 #define CPLD_SERIAL_TC232_CTS_BIT      4
150 #define CPLD_SERIAL_TC232_DSR_BIT      5
151 
152 #define CPLD_SROUTING_SET              0x0b
153 #define CPLD_SROUTING_CLR              0x1b
154 #define CPLD_SROUTING_MSP430_LPR       0
155 #define CPLD_SROUTING_MSP430_TC232     1
156 #define CPLD_SROUTING_MSP430_GSM       2
157 #define CPLD_SROUTING_LOON_LPR         (0 << 4)
158 #define CPLD_SROUTING_LOON_TC232       (1 << 4)
159 #define CPLD_SROUTING_LOON_GSM         (2 << 4)
160 
161 #define CPLD_AROUTING_SET              0x0c
162 #define CPLD_AROUTING_CLR              0x1c
163 #define CPLD_AROUTING_MIC2PHONE_BIT    0
164 #define CPLD_AROUTING_PHONE2INT_BIT    1
165 #define CPLD_AROUTING_PHONE2EXT_BIT    2
166 #define CPLD_AROUTING_LOONL2INT_BIT    3
167 #define CPLD_AROUTING_LOONL2EXT_BIT    4
168 #define CPLD_AROUTING_LOONR2PHONE_BIT  5
169 #define CPLD_AROUTING_LOONR2INT_BIT    6
170 #define CPLD_AROUTING_LOONR2EXT_BIT    7
171 
172 /* Balloon3 Interrupts */
173 #define BALLOON3_IRQ(x)		(IRQ_BOARD_START + (x))
174 
175 #define BALLOON3_AUX_NIRQ	PXA_GPIO_TO_IRQ(BALLOON3_GPIO_AUX_NIRQ)
176 #define BALLOON3_CODEC_IRQ	PXA_GPIO_TO_IRQ(BALLOON3_GPIO_CODEC_IRQ)
177 #define BALLOON3_S0_CD_IRQ	PXA_GPIO_TO_IRQ(BALLOON3_GPIO_S0_CD)
178 
179 #define BALLOON3_NR_IRQS	(IRQ_BOARD_START + 16)
180 
181 extern int balloon3_has(enum balloon3_features feature);
182 
183 #endif
184