1 /****************************************************************************** 2 * 3 * Module Name: dmtbinfo2 - Table info for non-AML tables 4 * 5 *****************************************************************************/ 6 7 /****************************************************************************** 8 * 9 * 1. Copyright Notice 10 * 11 * Some or all of this work - Copyright (c) 1999 - 2025, Intel Corp. 12 * All rights reserved. 13 * 14 * 2. License 15 * 16 * 2.1. This is your license from Intel Corp. under its intellectual property 17 * rights. You may have additional license terms from the party that provided 18 * you this software, covering your right to use that party's intellectual 19 * property rights. 20 * 21 * 2.2. Intel grants, free of charge, to any person ("Licensee") obtaining a 22 * copy of the source code appearing in this file ("Covered Code") an 23 * irrevocable, perpetual, worldwide license under Intel's copyrights in the 24 * base code distributed originally by Intel ("Original Intel Code") to copy, 25 * make derivatives, distribute, use and display any portion of the Covered 26 * Code in any form, with the right to sublicense such rights; and 27 * 28 * 2.3. Intel grants Licensee a non-exclusive and non-transferable patent 29 * license (with the right to sublicense), under only those claims of Intel 30 * patents that are infringed by the Original Intel Code, to make, use, sell, 31 * offer to sell, and import the Covered Code and derivative works thereof 32 * solely to the minimum extent necessary to exercise the above copyright 33 * license, and in no event shall the patent license extend to any additions 34 * to or modifications of the Original Intel Code. No other license or right 35 * is granted directly or by implication, estoppel or otherwise; 36 * 37 * The above copyright and patent license is granted only if the following 38 * conditions are met: 39 * 40 * 3. Conditions 41 * 42 * 3.1. Redistribution of Source with Rights to Further Distribute Source. 43 * Redistribution of source code of any substantial portion of the Covered 44 * Code or modification with rights to further distribute source must include 45 * the above Copyright Notice, the above License, this list of Conditions, 46 * and the following Disclaimer and Export Compliance provision. In addition, 47 * Licensee must cause all Covered Code to which Licensee contributes to 48 * contain a file documenting the changes Licensee made to create that Covered 49 * Code and the date of any change. Licensee must include in that file the 50 * documentation of any changes made by any predecessor Licensee. Licensee 51 * must include a prominent statement that the modification is derived, 52 * directly or indirectly, from Original Intel Code. 53 * 54 * 3.2. Redistribution of Source with no Rights to Further Distribute Source. 55 * Redistribution of source code of any substantial portion of the Covered 56 * Code or modification without rights to further distribute source must 57 * include the following Disclaimer and Export Compliance provision in the 58 * documentation and/or other materials provided with distribution. In 59 * addition, Licensee may not authorize further sublicense of source of any 60 * portion of the Covered Code, and must include terms to the effect that the 61 * license from Licensee to its licensee is limited to the intellectual 62 * property embodied in the software Licensee provides to its licensee, and 63 * not to intellectual property embodied in modifications its licensee may 64 * make. 65 * 66 * 3.3. Redistribution of Executable. Redistribution in executable form of any 67 * substantial portion of the Covered Code or modification must reproduce the 68 * above Copyright Notice, and the following Disclaimer and Export Compliance 69 * provision in the documentation and/or other materials provided with the 70 * distribution. 71 * 72 * 3.4. Intel retains all right, title, and interest in and to the Original 73 * Intel Code. 74 * 75 * 3.5. Neither the name Intel nor any other trademark owned or controlled by 76 * Intel shall be used in advertising or otherwise to promote the sale, use or 77 * other dealings in products derived from or relating to the Covered Code 78 * without prior written authorization from Intel. 79 * 80 * 4. Disclaimer and Export Compliance 81 * 82 * 4.1. INTEL MAKES NO WARRANTY OF ANY KIND REGARDING ANY SOFTWARE PROVIDED 83 * HERE. ANY SOFTWARE ORIGINATING FROM INTEL OR DERIVED FROM INTEL SOFTWARE 84 * IS PROVIDED "AS IS," AND INTEL WILL NOT PROVIDE ANY SUPPORT, ASSISTANCE, 85 * INSTALLATION, TRAINING OR OTHER SERVICES. INTEL WILL NOT PROVIDE ANY 86 * UPDATES, ENHANCEMENTS OR EXTENSIONS. INTEL SPECIFICALLY DISCLAIMS ANY 87 * IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT AND FITNESS FOR A 88 * PARTICULAR PURPOSE. 89 * 90 * 4.2. IN NO EVENT SHALL INTEL HAVE ANY LIABILITY TO LICENSEE, ITS LICENSEES 91 * OR ANY OTHER THIRD PARTY, FOR ANY LOST PROFITS, LOST DATA, LOSS OF USE OR 92 * COSTS OF PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, OR FOR ANY INDIRECT, 93 * SPECIAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THIS AGREEMENT, UNDER ANY 94 * CAUSE OF ACTION OR THEORY OF LIABILITY, AND IRRESPECTIVE OF WHETHER INTEL 95 * HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. THESE LIMITATIONS 96 * SHALL APPLY NOTWITHSTANDING THE FAILURE OF THE ESSENTIAL PURPOSE OF ANY 97 * LIMITED REMEDY. 98 * 99 * 4.3. Licensee shall not export, either directly or indirectly, any of this 100 * software or system incorporating such software without first obtaining any 101 * required license or other approval from the U. S. Department of Commerce or 102 * any other agency or department of the United States Government. In the 103 * event Licensee exports any such software from the United States or 104 * re-exports any such software from a foreign destination, Licensee shall 105 * ensure that the distribution and export/re-export of the software is in 106 * compliance with all laws, regulations, orders, or other restrictions of the 107 * U.S. Export Administration Regulations. Licensee agrees that neither it nor 108 * any of its subsidiaries will export/re-export any technical data, process, 109 * software, or service, directly or indirectly, to any country for which the 110 * United States government or any agency thereof requires an export license, 111 * other governmental approval, or letter of assurance, without first obtaining 112 * such license, approval or letter. 113 * 114 ***************************************************************************** 115 * 116 * Alternatively, you may choose to be licensed under the terms of the 117 * following license: 118 * 119 * Redistribution and use in source and binary forms, with or without 120 * modification, are permitted provided that the following conditions 121 * are met: 122 * 1. Redistributions of source code must retain the above copyright 123 * notice, this list of conditions, and the following disclaimer, 124 * without modification. 125 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 126 * substantially similar to the "NO WARRANTY" disclaimer below 127 * ("Disclaimer") and any redistribution must be conditioned upon 128 * including a substantially similar Disclaimer requirement for further 129 * binary redistribution. 130 * 3. Neither the names of the above-listed copyright holders nor the names 131 * of any contributors may be used to endorse or promote products derived 132 * from this software without specific prior written permission. 133 * 134 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 135 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 136 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 137 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 138 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 139 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 140 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 141 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 142 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 143 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 144 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 145 * 146 * Alternatively, you may choose to be licensed under the terms of the 147 * GNU General Public License ("GPL") version 2 as published by the Free 148 * Software Foundation. 149 * 150 *****************************************************************************/ 151 152 #include <contrib/dev/acpica/include/acpi.h> 153 #include <contrib/dev/acpica/include/accommon.h> 154 #include <contrib/dev/acpica/include/acdisasm.h> 155 #include <contrib/dev/acpica/include/actbinfo.h> 156 157 /* This module used for application-level code only */ 158 159 #define _COMPONENT ACPI_CA_DISASSEMBLER 160 ACPI_MODULE_NAME ("dmtbinfo2") 161 162 /* 163 * How to add a new table: 164 * 165 * - Add the C table definition to the actbl1.h or actbl2.h header. 166 * - Add ACPI_xxxx_OFFSET macro(s) for the table (and subtables) to list below. 167 * - Define the table in this file (for the disassembler). If any 168 * new data types are required (ACPI_DMT_*), see below. 169 * - Add an external declaration for the new table definition (AcpiDmTableInfo*) 170 * in acdisam.h 171 * - Add new table definition to the dispatch table in dmtable.c (AcpiDmTableData) 172 * If a simple table (with no subtables), no disassembly code is needed. 173 * Otherwise, create the AcpiDmDump* function for to disassemble the table 174 * and add it to the dmtbdump.c file. 175 * - Add an external declaration for the new AcpiDmDump* function in acdisasm.h 176 * - Add the new AcpiDmDump* function to the dispatch table in dmtable.c 177 * - Create a template for the new table 178 * - Add data table compiler support 179 * 180 * How to add a new data type (ACPI_DMT_*): 181 * 182 * - Add new type at the end of the ACPI_DMT list in acdisasm.h 183 * - Add length and implementation cases in dmtable.c (disassembler) 184 * - Add type and length cases in dtutils.c (DT compiler) 185 */ 186 187 /* 188 * Remaining tables are not consumed directly by the ACPICA subsystem 189 */ 190 191 /******************************************************************************* 192 * 193 * AGDI - Arm Generic Diagnostic Dump and Reset Device Interface 194 * 195 * Conforms to "ACPI for Arm Components 1.1, Platform Design Document" 196 * ARM DEN0093 v1.1 197 * 198 ******************************************************************************/ 199 200 ACPI_DMTABLE_INFO AcpiDmTableInfoAgdi[] = 201 { 202 {ACPI_DMT_UINT8, ACPI_AGDI_OFFSET (Flags), "Flags (decoded below)", 0}, 203 {ACPI_DMT_FLAG0, ACPI_AGDI_FLAG_OFFSET (Flags, 0), "Signalling mode", 0}, 204 {ACPI_DMT_UINT24, ACPI_AGDI_OFFSET (Reserved[0]), "Reserved", 0}, 205 {ACPI_DMT_UINT32, ACPI_AGDI_OFFSET (SdeiEvent), "SdeiEvent", 0}, 206 {ACPI_DMT_UINT32, ACPI_AGDI_OFFSET (Gsiv), "Gsiv", 0}, 207 ACPI_DMT_TERMINATOR 208 }; 209 210 211 /******************************************************************************* 212 * 213 * APMT - ARM Performance Monitoring Unit Table 214 * 215 * Conforms to: 216 * ARM Performance Monitoring Unit Architecture 1.0 Platform Design Document 217 * ARM DEN0117 v1.0 November 25, 2021 218 * 219 ******************************************************************************/ 220 221 ACPI_DMTABLE_INFO AcpiDmTableInfoApmtNode[] = 222 { 223 {ACPI_DMT_UINT16, ACPI_APMTN_OFFSET (Length), "Length of APMT Node", 0}, 224 {ACPI_DMT_UINT8, ACPI_APMTN_OFFSET (Flags), "Node Flags", 0}, 225 {ACPI_DMT_FLAG0, ACPI_APMTN_FLAG_OFFSET (Flags, 0), "Dual Page Extension", 0}, 226 {ACPI_DMT_FLAG1, ACPI_APMTN_FLAG_OFFSET (Flags, 0), "Processor Affinity Type", 0}, 227 {ACPI_DMT_FLAG2, ACPI_APMTN_FLAG_OFFSET (Flags, 0), "64-bit Atomic Support", 0}, 228 {ACPI_DMT_UINT8, ACPI_APMTN_OFFSET (Type), "Node Type", 0}, 229 {ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (Id), "Unique Node Identifier", 0}, 230 {ACPI_DMT_UINT64, ACPI_APMTN_OFFSET (InstPrimary), "Primary Node Instance", 0}, 231 {ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (InstSecondary), "Secondary Node Instance", 0}, 232 {ACPI_DMT_UINT64, ACPI_APMTN_OFFSET (BaseAddress0), "Page 0 Base Address", 0}, 233 {ACPI_DMT_UINT64, ACPI_APMTN_OFFSET (BaseAddress1), "Page 1 Base Address", 0}, 234 {ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (OvflwIrq), "Overflow Interrupt ID", 0}, 235 {ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (Reserved), "Reserved", 0}, 236 {ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (OvflwIrqFlags), "Overflow Interrupt Flags", 0}, 237 {ACPI_DMT_FLAG0, ACPI_APMTN_FLAG_OFFSET (OvflwIrqFlags, 0), "Interrupt Mode", 0}, 238 {ACPI_DMT_FLAG1, ACPI_APMTN_FLAG_OFFSET (OvflwIrqFlags, 0), "Interrupt Type", 0}, 239 {ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (ProcAffinity), "Processor Affinity", 0}, 240 {ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (ImplId), "Implementation ID", 0}, 241 ACPI_DMT_TERMINATOR 242 }; 243 244 245 /******************************************************************************* 246 * 247 * IORT - IO Remapping Table 248 * 249 ******************************************************************************/ 250 251 ACPI_DMTABLE_INFO AcpiDmTableInfoIort[] = 252 { 253 {ACPI_DMT_UINT32, ACPI_IORT_OFFSET (NodeCount), "Node Count", 0}, 254 {ACPI_DMT_UINT32, ACPI_IORT_OFFSET (NodeOffset), "Node Offset", 0}, 255 {ACPI_DMT_UINT32, ACPI_IORT_OFFSET (Reserved), "Reserved", 0}, 256 ACPI_DMT_TERMINATOR 257 }; 258 259 /* Optional padding field */ 260 261 ACPI_DMTABLE_INFO AcpiDmTableInfoIortPad[] = 262 { 263 {ACPI_DMT_RAW_BUFFER, 0, "Optional Padding", DT_OPTIONAL}, 264 ACPI_DMT_TERMINATOR 265 }; 266 267 /* Common Subtable header (one per Subtable) */ 268 269 ACPI_DMTABLE_INFO AcpiDmTableInfoIortHdr[] = 270 { 271 {ACPI_DMT_UINT8, ACPI_IORTH_OFFSET (Type), "Type", 0}, 272 {ACPI_DMT_UINT16, ACPI_IORTH_OFFSET (Length), "Length", DT_LENGTH}, 273 {ACPI_DMT_UINT8, ACPI_IORTH_OFFSET (Revision), "Revision", 0}, 274 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (Identifier), "Reserved", 0}, 275 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (MappingCount), "Mapping Count", 0}, 276 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (MappingOffset), "Mapping Offset", 0}, 277 ACPI_DMT_TERMINATOR 278 }; 279 280 /* Common Subtable header (one per Subtable)- Revision 3 */ 281 282 ACPI_DMTABLE_INFO AcpiDmTableInfoIortHdr3[] = 283 { 284 {ACPI_DMT_UINT8, ACPI_IORTH_OFFSET (Type), "Type", 0}, 285 {ACPI_DMT_UINT16, ACPI_IORTH_OFFSET (Length), "Length", DT_LENGTH}, 286 {ACPI_DMT_UINT8, ACPI_IORTH_OFFSET (Revision), "Revision", 0}, 287 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (Identifier), "Identifier", 0}, 288 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (MappingCount), "Mapping Count", 0}, 289 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (MappingOffset), "Mapping Offset", 0}, 290 ACPI_DMT_TERMINATOR 291 }; 292 293 ACPI_DMTABLE_INFO AcpiDmTableInfoIortMap[] = 294 { 295 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (InputBase), "Input base", DT_OPTIONAL}, 296 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (IdCount), "ID Count", 0}, 297 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (OutputBase), "Output Base", 0}, 298 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (OutputReference), "Output Reference", 0}, 299 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (Flags), "Flags (decoded below)", 0}, 300 {ACPI_DMT_FLAG0, ACPI_IORTM_FLAG_OFFSET (Flags, 0), "Single Mapping", 0}, 301 ACPI_DMT_TERMINATOR 302 }; 303 304 ACPI_DMTABLE_INFO AcpiDmTableInfoIortAcc[] = 305 { 306 {ACPI_DMT_UINT32, ACPI_IORTA_OFFSET (CacheCoherency), "Cache Coherency", 0}, 307 {ACPI_DMT_UINT8, ACPI_IORTA_OFFSET (Hints), "Hints (decoded below)", 0}, 308 {ACPI_DMT_FLAG0, ACPI_IORTA_FLAG_OFFSET (Hints, 0), "Transient", 0}, 309 {ACPI_DMT_FLAG1, ACPI_IORTA_FLAG_OFFSET (Hints, 0), "Write Allocate", 0}, 310 {ACPI_DMT_FLAG2, ACPI_IORTA_FLAG_OFFSET (Hints, 0), "Read Allocate", 0}, 311 {ACPI_DMT_FLAG3, ACPI_IORTA_FLAG_OFFSET (Hints, 0), "Override", 0}, 312 {ACPI_DMT_UINT16, ACPI_IORTA_OFFSET (Reserved), "Reserved", 0}, 313 {ACPI_DMT_UINT8, ACPI_IORTA_OFFSET (MemoryFlags), "Memory Flags (decoded below)", 0}, 314 {ACPI_DMT_FLAG0, ACPI_IORTA_FLAG_OFFSET (MemoryFlags, 0), "Coherency", 0}, 315 {ACPI_DMT_FLAG1, ACPI_IORTA_FLAG_OFFSET (MemoryFlags, 0), "Device Attribute", 0}, 316 {ACPI_DMT_FLAG2, ACPI_IORTA_FLAG_OFFSET (MemoryFlags, 0), "Ensured Coherency of Accesses", 0}, 317 ACPI_DMT_TERMINATOR 318 }; 319 320 /* IORT subtables */ 321 322 /* 0x00: ITS Group */ 323 324 ACPI_DMTABLE_INFO AcpiDmTableInfoIort0[] = 325 { 326 {ACPI_DMT_UINT32, ACPI_IORT0_OFFSET (ItsCount), "ItsCount", 0}, 327 ACPI_DMT_TERMINATOR 328 }; 329 330 ACPI_DMTABLE_INFO AcpiDmTableInfoIort0a[] = 331 { 332 {ACPI_DMT_UINT32, 0, "Identifiers", DT_OPTIONAL}, 333 ACPI_DMT_TERMINATOR 334 }; 335 336 /* 0x01: Named Component */ 337 338 ACPI_DMTABLE_INFO AcpiDmTableInfoIort1[] = 339 { 340 {ACPI_DMT_UINT32, ACPI_IORT1_OFFSET (NodeFlags), "Node Flags", 0}, 341 {ACPI_DMT_IORTMEM, ACPI_IORT1_OFFSET (MemoryProperties), "Memory Properties", 0}, 342 {ACPI_DMT_UINT8, ACPI_IORT1_OFFSET (MemoryAddressLimit), "Memory Size Limit", 0}, 343 {ACPI_DMT_STRING, ACPI_IORT1_OFFSET (DeviceName[0]), "Device Name", 0}, 344 ACPI_DMT_TERMINATOR 345 }; 346 347 ACPI_DMTABLE_INFO AcpiDmTableInfoIort1a[] = 348 { 349 {ACPI_DMT_RAW_BUFFER, 0, "Padding", DT_OPTIONAL}, 350 ACPI_DMT_TERMINATOR 351 }; 352 353 /* 0x02: PCI Root Complex */ 354 355 ACPI_DMTABLE_INFO AcpiDmTableInfoIort2[] = 356 { 357 {ACPI_DMT_IORTMEM, ACPI_IORT2_OFFSET (MemoryProperties), "Memory Properties", 0}, 358 {ACPI_DMT_UINT32, ACPI_IORT2_OFFSET (AtsAttribute), "ATS Attribute", 0}, 359 {ACPI_DMT_UINT32, ACPI_IORT2_OFFSET (PciSegmentNumber), "PCI Segment Number", 0}, 360 {ACPI_DMT_UINT8, ACPI_IORT2_OFFSET (MemoryAddressLimit), "Memory Size Limit", 0}, 361 {ACPI_DMT_UINT16, ACPI_IORT2_OFFSET (PasidCapabilities), "PASID Capabilities", 0}, 362 {ACPI_DMT_UINT8, ACPI_IORT2_OFFSET (Reserved[0]), "Reserved", 0}, 363 ACPI_DMT_TERMINATOR 364 }; 365 366 /* 0x03: SMMUv1/2 */ 367 368 ACPI_DMTABLE_INFO AcpiDmTableInfoIort3[] = 369 { 370 {ACPI_DMT_UINT64, ACPI_IORT3_OFFSET (BaseAddress), "Base Address", 0}, 371 {ACPI_DMT_UINT64, ACPI_IORT3_OFFSET (Span), "Span", 0}, 372 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (Model), "Model", 0}, 373 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (Flags), "Flags (decoded below)", 0}, 374 {ACPI_DMT_FLAG0, ACPI_IORT3_FLAG_OFFSET (Flags, 0), "DVM Supported", 0}, 375 {ACPI_DMT_FLAG1, ACPI_IORT3_FLAG_OFFSET (Flags, 0), "Coherent Walk", 0}, 376 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (GlobalInterruptOffset), "Global Interrupt Offset", 0}, 377 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (ContextInterruptCount), "Context Interrupt Count", 0}, 378 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (ContextInterruptOffset), "Context Interrupt Offset", 0}, 379 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (PmuInterruptCount), "PMU Interrupt Count", 0}, 380 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (PmuInterruptOffset), "PMU Interrupt Offset", 0}, 381 ACPI_DMT_TERMINATOR 382 }; 383 384 ACPI_DMTABLE_INFO AcpiDmTableInfoIort3a[] = 385 { 386 {ACPI_DMT_UINT32, ACPI_IORT3A_OFFSET (NSgIrpt), "NSgIrpt", 0}, 387 {ACPI_DMT_UINT32, ACPI_IORT3A_OFFSET (NSgIrptFlags), "NSgIrpt Flags (decoded below)", 0}, 388 {ACPI_DMT_FLAG0, ACPI_IORT3a_FLAG_OFFSET (NSgIrptFlags, 0), "Edge Triggered", 0}, 389 {ACPI_DMT_UINT32, ACPI_IORT3A_OFFSET (NSgCfgIrpt), "NSgCfgIrpt", 0}, 390 {ACPI_DMT_UINT32, ACPI_IORT3A_OFFSET (NSgCfgIrptFlags), "NSgCfgIrpt Flags (decoded below)", 0}, 391 {ACPI_DMT_FLAG0, ACPI_IORT3a_FLAG_OFFSET (NSgCfgIrptFlags, 0), "Edge Triggered", 0}, 392 ACPI_DMT_TERMINATOR 393 }; 394 395 ACPI_DMTABLE_INFO AcpiDmTableInfoIort3b[] = 396 { 397 {ACPI_DMT_UINT64, 0, "Context Interrupt", DT_OPTIONAL}, 398 ACPI_DMT_TERMINATOR 399 }; 400 401 ACPI_DMTABLE_INFO AcpiDmTableInfoIort3c[] = 402 { 403 {ACPI_DMT_UINT64, 0, "PMU Interrupt", DT_OPTIONAL}, 404 ACPI_DMT_TERMINATOR 405 }; 406 407 /* 0x04: SMMUv3 */ 408 409 ACPI_DMTABLE_INFO AcpiDmTableInfoIort4[] = 410 { 411 {ACPI_DMT_UINT64, ACPI_IORT4_OFFSET (BaseAddress), "Base Address", 0}, 412 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (Flags), "Flags (decoded below)", 0}, 413 {ACPI_DMT_FLAG0, ACPI_IORT4_FLAG_OFFSET (Flags, 0), "COHACC Override", 0}, 414 {ACPI_DMT_FLAG1, ACPI_IORT4_FLAG_OFFSET (Flags, 0), "HTTU Override", 0}, 415 {ACPI_DMT_FLAG3, ACPI_IORT4_FLAG_OFFSET (Flags, 0), "Proximity Domain Valid", 0}, 416 {ACPI_DMT_FLAG4, ACPI_IORT4_FLAG_OFFSET (Flags, 0), "DeviceID Valid", 0}, 417 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (Reserved), "Reserved", 0}, 418 {ACPI_DMT_UINT64, ACPI_IORT4_OFFSET (VatosAddress), "VATOS Address", 0}, 419 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (Model), "Model", 0}, 420 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (EventGsiv), "Event GSIV", 0}, 421 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (PriGsiv), "PRI GSIV", 0}, 422 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (GerrGsiv), "GERR GSIV", 0}, 423 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (SyncGsiv), "Sync GSIV", 0}, 424 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (Pxm), "Proximity Domain", 0}, 425 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (IdMappingIndex), "Device ID Mapping Index", 0}, 426 ACPI_DMT_TERMINATOR 427 }; 428 429 /* 0x05: PMCG */ 430 431 ACPI_DMTABLE_INFO AcpiDmTableInfoIort5[] = 432 { 433 {ACPI_DMT_UINT64, ACPI_IORT5_OFFSET (Page0BaseAddress), "Page 0 Base Address", 0}, 434 {ACPI_DMT_UINT32, ACPI_IORT5_OFFSET (OverflowGsiv), "Overflow Interrupt GSIV", 0}, 435 {ACPI_DMT_UINT32, ACPI_IORT5_OFFSET (NodeReference), "Node Reference", 0}, 436 {ACPI_DMT_UINT64, ACPI_IORT5_OFFSET (Page1BaseAddress), "Page 1 Base Address", 0}, 437 ACPI_DMT_TERMINATOR 438 }; 439 440 441 /* 0x06: RMR */ 442 443 ACPI_DMTABLE_INFO AcpiDmTableInfoIort6[] = 444 { 445 {ACPI_DMT_UINT32, ACPI_IORT6_OFFSET (Flags), "Flags (decoded below)", 0}, 446 {ACPI_DMT_FLAG0, ACPI_IORT6_FLAG_OFFSET (Flags, 0), "Remapping Permitted", 0}, 447 {ACPI_DMT_FLAG1, ACPI_IORT6_FLAG_OFFSET (Flags, 0), "Access Privileged", 0}, 448 {ACPI_DMT_FLAGS8_2, ACPI_IORT6_FLAG_OFFSET (Flags, 0), "Access Attributes", 0}, 449 {ACPI_DMT_UINT32, ACPI_IORT6_OFFSET (RmrCount), "Number of RMR Descriptors", 0}, 450 {ACPI_DMT_UINT32, ACPI_IORT6_OFFSET (RmrOffset), "RMR Descriptor Offset", 0}, 451 ACPI_DMT_TERMINATOR 452 }; 453 454 ACPI_DMTABLE_INFO AcpiDmTableInfoIort6a[] = 455 { 456 {ACPI_DMT_UINT64, ACPI_IORT6A_OFFSET (BaseAddress), "Base Address of RMR", DT_OPTIONAL}, 457 {ACPI_DMT_UINT64, ACPI_IORT6A_OFFSET (Length), "Length of RMR", 0}, 458 {ACPI_DMT_UINT32, ACPI_IORT6A_OFFSET (Reserved), "Reserved", 0}, 459 ACPI_DMT_TERMINATOR 460 }; 461 462 /* 0x07: IWB */ 463 464 ACPI_DMTABLE_INFO AcpiDmTableInfoIort7[] = 465 { 466 {ACPI_DMT_UINT64, ACPI_IORT7_OFFSET (BaseAddress), "Config Frame base", 0}, 467 {ACPI_DMT_UINT16, ACPI_IORT7_OFFSET (IwbIndex), "IWB Index", 0}, 468 {ACPI_DMT_STRING, ACPI_IORT7_OFFSET (DeviceName[0]), "IWB Device Name", 0}, 469 ACPI_DMT_TERMINATOR 470 }; 471 472 473 /******************************************************************************* 474 * 475 * IOVT - I/O Virtualization Table 476 * 477 ******************************************************************************/ 478 479 ACPI_DMTABLE_INFO AcpiDmTableInfoIovt[] = 480 { 481 {ACPI_DMT_UINT16, ACPI_IOVT_OFFSET (IommuCount), "IOMMU Count", 0}, 482 {ACPI_DMT_UINT16, ACPI_IOVT_OFFSET (IommuOffset), "IOMMU Offset", 0}, 483 {ACPI_DMT_UINT64, ACPI_IOVT_OFFSET (Reserved), "Reserved", 0}, 484 ACPI_DMT_TERMINATOR 485 }; 486 487 /* IOVT Subtables */ 488 489 ACPI_DMTABLE_INFO AcpiDmTableInfoIovt0[] = 490 { 491 {ACPI_DMT_IOVT, ACPI_IOVTH_OFFSET (Type), "Subtable Type", 0}, 492 {ACPI_DMT_UINT16, ACPI_IOVTH_OFFSET (Length), "Length", DT_LENGTH}, 493 {ACPI_DMT_UINT32, ACPI_IOVT0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 494 {ACPI_DMT_FLAG0, ACPI_IOVT0_FLAG_OFFSET (Flags,0), "PCI Device", 0}, 495 {ACPI_DMT_FLAG1, ACPI_IOVT0_FLAG_OFFSET (Flags,0), "Proximity Domain Valid", 0}, 496 {ACPI_DMT_FLAG2, ACPI_IOVT0_FLAG_OFFSET (Flags,0), "Manageable Devices Range", 0}, 497 {ACPI_DMT_FLAG3, ACPI_IOVT0_FLAG_OFFSET (Flags,0), "HW Capability Supported", 0}, 498 {ACPI_DMT_FLAG4, ACPI_IOVT0_FLAG_OFFSET (Flags,0), "MSI Interrupt Address", 0}, 499 {ACPI_DMT_UINT16, ACPI_IOVT0_OFFSET (Segment), "PCI Segment Number", 0}, 500 {ACPI_DMT_UINT16, ACPI_IOVT0_OFFSET (PhyWidth), "Physical Address Width", 0}, 501 {ACPI_DMT_UINT16, ACPI_IOVT0_OFFSET (VirtWidth), "Virtual Address Width", 0}, 502 {ACPI_DMT_UINT16, ACPI_IOVT0_OFFSET (MaxPageLevel), "Max Page Level", 0}, 503 {ACPI_DMT_UINT64, ACPI_IOVT0_OFFSET (PageSize), "Page Size Supported", 0}, 504 {ACPI_DMT_UINT32, ACPI_IOVT0_OFFSET (DeviceId), "IOMMU DeviceID", 0}, 505 {ACPI_DMT_UINT64, ACPI_IOVT0_OFFSET (BaseAddress), "IOMMU Base Address", 0}, 506 {ACPI_DMT_UINT32, ACPI_IOVT0_OFFSET (AddressSpaceSize), "IOMMU Register Size", 0}, 507 {ACPI_DMT_UINT8, ACPI_IOVT0_OFFSET (InterruptType), "Interrupt Type", 0}, 508 {ACPI_DMT_UINT24, ACPI_IOVT0_OFFSET (Reserved), "Reserved", 0}, 509 {ACPI_DMT_UINT32, ACPI_IOVT0_OFFSET (GsiNumber), "Global System Interrupt", 0}, 510 {ACPI_DMT_UINT32, ACPI_IOVT0_OFFSET (ProximityDomain), "Proximity Domain", 0}, 511 {ACPI_DMT_UINT32, ACPI_IOVT0_OFFSET (MaxDeviceNum), "Max Device Num", 0}, 512 {ACPI_DMT_UINT32, ACPI_IOVT0_OFFSET (DeviceEntryNum), "Number of Device Entries", 0}, 513 {ACPI_DMT_UINT32, ACPI_IOVT0_OFFSET (DeviceEntryOffset), "Offset of Device Entries", 0}, 514 ACPI_DMT_TERMINATOR 515 }; 516 517 /* device entry */ 518 519 ACPI_DMTABLE_INFO AcpiDmTableInfoIovtdev[] = 520 { 521 {ACPI_DMT_IOVTDEV, ACPI_IOVTDEV_OFFSET (Type), "Subtable Type", 0}, 522 {ACPI_DMT_UINT8, ACPI_IOVTDEV_OFFSET (Length), "Length", 0}, 523 {ACPI_DMT_UINT8, ACPI_IOVTDEV_OFFSET (Flags), "Flags", 0}, 524 {ACPI_DMT_UINT24, ACPI_IOVTDEV_OFFSET (Reserved), "Reserved", 0}, 525 {ACPI_DMT_UINT16, ACPI_IOVTDEV_OFFSET (DeviceId), "DeviceID", 0}, 526 ACPI_DMT_TERMINATOR 527 }; 528 529 530 /******************************************************************************* 531 * 532 * IVRS - I/O Virtualization Reporting Structure 533 * 534 ******************************************************************************/ 535 536 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs[] = 537 { 538 {ACPI_DMT_UINT32, ACPI_IVRS_OFFSET (Info), "Virtualization Info", 0}, 539 {ACPI_DMT_UINT64, ACPI_IVRS_OFFSET (Reserved), "Reserved", 0}, 540 ACPI_DMT_TERMINATOR 541 }; 542 543 /* IVRS subtables */ 544 545 /* 0x10: I/O Virtualization Hardware Definition (IVHD) Block */ 546 547 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsHware1[] = 548 { 549 {ACPI_DMT_IVRS, ACPI_IVRSH_OFFSET (Type), "Subtable Type", 0}, 550 {ACPI_DMT_UINT8, ACPI_IVRSH_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 551 {ACPI_DMT_FLAG0, ACPI_IVRS_FLAG_OFFSET (Flags,0), "HtTunEn", 0}, 552 {ACPI_DMT_FLAG1, ACPI_IVRS_FLAG_OFFSET (Flags,0), "PassPW", 0}, 553 {ACPI_DMT_FLAG2, ACPI_IVRS_FLAG_OFFSET (Flags,0), "ResPassPW", 0}, 554 {ACPI_DMT_FLAG3, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Isoc Control", 0}, 555 {ACPI_DMT_FLAG4, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Iotlb Support", 0}, 556 {ACPI_DMT_FLAG5, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Coherent", 0}, 557 {ACPI_DMT_FLAG6, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Prefetch Support", 0}, 558 {ACPI_DMT_FLAG7, ACPI_IVRS_FLAG_OFFSET (Flags,0), "PPR Support", 0}, 559 {ACPI_DMT_UINT16, ACPI_IVRSH_OFFSET (Length), "Length", DT_LENGTH}, 560 {ACPI_DMT_UINT16, ACPI_IVRSH_OFFSET (DeviceId), "DeviceId", 0}, 561 {ACPI_DMT_UINT16, ACPI_IVRS0_OFFSET (CapabilityOffset), "Capability Offset", 0}, 562 {ACPI_DMT_UINT64, ACPI_IVRS0_OFFSET (BaseAddress), "Base Address", 0}, 563 {ACPI_DMT_UINT16, ACPI_IVRS0_OFFSET (PciSegmentGroup), "PCI Segment Group", 0}, 564 {ACPI_DMT_UINT16, ACPI_IVRS0_OFFSET (Info), "Virtualization Info", 0}, 565 {ACPI_DMT_UINT32, ACPI_IVRS0_OFFSET (FeatureReporting), "Feature Reporting", 0}, 566 ACPI_DMT_TERMINATOR 567 }; 568 569 /* 0x11, 0x40: I/O Virtualization Hardware Definition (IVHD) Block */ 570 571 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsHware23[] = 572 { 573 {ACPI_DMT_IVRS, ACPI_IVRSH_OFFSET (Type), "Subtable Type", 0}, 574 {ACPI_DMT_UINT8, ACPI_IVRSH_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 575 {ACPI_DMT_FLAG0, ACPI_IVRS_FLAG_OFFSET (Flags,0), "HtTunEn", 0}, 576 {ACPI_DMT_FLAG1, ACPI_IVRS_FLAG_OFFSET (Flags,0), "PassPW", 0}, 577 {ACPI_DMT_FLAG2, ACPI_IVRS_FLAG_OFFSET (Flags,0), "ResPassPW", 0}, 578 {ACPI_DMT_FLAG3, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Isoc Control", 0}, 579 {ACPI_DMT_FLAG4, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Iotlb Support", 0}, 580 {ACPI_DMT_FLAG5, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Coherent", 0}, 581 {ACPI_DMT_FLAG6, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Prefetch Support", 0}, 582 {ACPI_DMT_FLAG7, ACPI_IVRS_FLAG_OFFSET (Flags,0), "PPR Support", 0}, 583 {ACPI_DMT_UINT16, ACPI_IVRS01_OFFSET (Header.Length), "Length", DT_LENGTH}, 584 {ACPI_DMT_UINT16, ACPI_IVRS01_OFFSET (Header.DeviceId), "DeviceId", 0}, 585 {ACPI_DMT_UINT16, ACPI_IVRS01_OFFSET (CapabilityOffset), "Capability Offset", 0}, 586 {ACPI_DMT_UINT64, ACPI_IVRS01_OFFSET (BaseAddress), "Base Address", 0}, 587 {ACPI_DMT_UINT16, ACPI_IVRS01_OFFSET (PciSegmentGroup), "PCI Segment Group", 0}, 588 {ACPI_DMT_UINT16, ACPI_IVRS01_OFFSET (Info), "Virtualization Info", 0}, 589 {ACPI_DMT_UINT32, ACPI_IVRS01_OFFSET (Attributes), "Attributes", 0}, 590 {ACPI_DMT_UINT64, ACPI_IVRS01_OFFSET (EfrRegisterImage), "EFR Image", 0}, 591 {ACPI_DMT_UINT64, ACPI_IVRS01_OFFSET (Reserved), "Reserved", 0}, 592 ACPI_DMT_TERMINATOR 593 }; 594 595 /* 0x20, 0x21, 0x22: I/O Virtualization Memory Definition (IVMD) Device Entry Block */ 596 597 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsMemory[] = 598 { 599 {ACPI_DMT_IVRS, ACPI_IVRSH_OFFSET (Type), "Subtable Type", 0}, 600 {ACPI_DMT_UINT8, ACPI_IVRSH_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 601 {ACPI_DMT_FLAG0, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Unity", 0}, 602 {ACPI_DMT_FLAG1, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Readable", 0}, 603 {ACPI_DMT_FLAG2, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Writeable", 0}, 604 {ACPI_DMT_FLAG3, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Exclusion Range", 0}, 605 {ACPI_DMT_UINT16, ACPI_IVRSH_OFFSET (Length), "Length", DT_LENGTH}, 606 {ACPI_DMT_UINT16, ACPI_IVRSH_OFFSET (DeviceId), "DeviceId", 0}, 607 {ACPI_DMT_UINT16, ACPI_IVRS1_OFFSET (AuxData), "Auxiliary Data", 0}, 608 {ACPI_DMT_UINT64, ACPI_IVRS1_OFFSET (Reserved), "Reserved", 0}, 609 {ACPI_DMT_UINT64, ACPI_IVRS1_OFFSET (StartAddress), "Start Address", 0}, 610 {ACPI_DMT_UINT64, ACPI_IVRS1_OFFSET (MemoryLength), "Memory Length", 0}, 611 ACPI_DMT_TERMINATOR 612 }; 613 614 /* Device entry header for IVHD block */ 615 616 #define ACPI_DMT_IVRS_DE_HEADER \ 617 {ACPI_DMT_IVRS_DE, ACPI_IVRSD_OFFSET (Type), "Subtable Type", 0}, \ 618 {ACPI_DMT_UINT16, ACPI_IVRSD_OFFSET (Id), "Device ID", 0}, \ 619 {ACPI_DMT_UINT8, ACPI_IVRSD_OFFSET (DataSetting), "Data Setting (decoded below)", 0}, \ 620 {ACPI_DMT_FLAG0, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "INITPass", 0}, \ 621 {ACPI_DMT_FLAG1, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "EIntPass", 0}, \ 622 {ACPI_DMT_FLAG2, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "NMIPass", 0}, \ 623 {ACPI_DMT_FLAG3, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "Reserved", 0}, \ 624 {ACPI_DMT_FLAGS4, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "System MGMT", 0}, \ 625 {ACPI_DMT_FLAG6, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "LINT0 Pass", 0}, \ 626 {ACPI_DMT_FLAG7, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "LINT1 Pass", 0} 627 628 /* 4-byte device entry (Types 1,2,3,4) */ 629 630 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs4[] = 631 { 632 ACPI_DMT_IVRS_DE_HEADER, 633 ACPI_DMT_TERMINATOR 634 }; 635 636 /* 8-byte device entry (Type Alias Select, Alias Start of Range) */ 637 638 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs8a[] = 639 { 640 ACPI_DMT_IVRS_DE_HEADER, 641 {ACPI_DMT_UINT8, ACPI_IVRS8A_OFFSET (Reserved1), "Reserved", 0}, 642 {ACPI_DMT_UINT16, ACPI_IVRS8A_OFFSET (UsedId), "Source Used Device ID", 0}, 643 {ACPI_DMT_UINT8, ACPI_IVRS8A_OFFSET (Reserved2), "Reserved", 0}, 644 ACPI_DMT_TERMINATOR 645 }; 646 647 /* 8-byte device entry (Type Extended Select, Extended Start of Range) */ 648 649 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs8b[] = 650 { 651 ACPI_DMT_IVRS_DE_HEADER, 652 {ACPI_DMT_UINT32, ACPI_IVRS8B_OFFSET (ExtendedData), "Extended Data", 0}, 653 ACPI_DMT_TERMINATOR 654 }; 655 656 /* 8-byte device entry (Type Special Device) */ 657 658 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs8c[] = 659 { 660 ACPI_DMT_IVRS_DE_HEADER, 661 {ACPI_DMT_UINT8, ACPI_IVRS8C_OFFSET (Handle), "Handle", 0}, 662 {ACPI_DMT_UINT16, ACPI_IVRS8C_OFFSET (UsedId), "Source Used Device ID", 0}, 663 {ACPI_DMT_UINT8, ACPI_IVRS8C_OFFSET (Variety), "Variety", 0}, 664 ACPI_DMT_TERMINATOR 665 }; 666 667 /* Variable-length Device Entry Type 0xF0 */ 668 669 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsHid[] = 670 { 671 ACPI_DMT_IVRS_DE_HEADER, 672 ACPI_DMT_TERMINATOR 673 }; 674 675 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsUidString[] = 676 { 677 {ACPI_DMT_UINT8, 0, "UID Format", DT_DESCRIBES_OPTIONAL}, 678 {ACPI_DMT_UINT8, 1, "UID Length", DT_DESCRIBES_OPTIONAL}, 679 {ACPI_DMT_IVRS_UNTERMINATED_STRING, 2, "UID", DT_OPTIONAL}, 680 ACPI_DMT_TERMINATOR 681 }; 682 683 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsUidInteger[] = 684 { 685 {ACPI_DMT_UINT8, 0, "UID Format", DT_DESCRIBES_OPTIONAL}, 686 {ACPI_DMT_UINT8, 1, "UID Length", DT_DESCRIBES_OPTIONAL}, 687 {ACPI_DMT_UINT64, 2, "UID", DT_OPTIONAL}, 688 ACPI_DMT_TERMINATOR 689 }; 690 691 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsHidString[] = 692 { 693 {ACPI_DMT_NAME8, 0, "ACPI HID", 0}, 694 ACPI_DMT_TERMINATOR 695 }; 696 697 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsHidInteger[] = 698 { 699 {ACPI_DMT_UINT64, 0, "ACPI HID", 0}, 700 ACPI_DMT_TERMINATOR 701 }; 702 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsCidString[] = 703 { 704 {ACPI_DMT_NAME8, 0, "ACPI CID", 0}, 705 ACPI_DMT_TERMINATOR 706 }; 707 708 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsCidInteger[] = 709 { 710 {ACPI_DMT_UINT64, 0, "ACPI CID", 0}, 711 ACPI_DMT_TERMINATOR 712 }; 713 714 715 /******************************************************************************* 716 * 717 * LPIT - Low Power Idle Table 718 * 719 ******************************************************************************/ 720 721 /* Main table consists only of the standard ACPI table header */ 722 723 /* Common Subtable header (one per Subtable) */ 724 725 ACPI_DMTABLE_INFO AcpiDmTableInfoLpitHdr[] = 726 { 727 {ACPI_DMT_LPIT, ACPI_LPITH_OFFSET (Type), "Subtable Type", 0}, 728 {ACPI_DMT_UINT32, ACPI_LPITH_OFFSET (Length), "Length", DT_LENGTH}, 729 {ACPI_DMT_UINT16, ACPI_LPITH_OFFSET (UniqueId), "Unique ID", 0}, 730 {ACPI_DMT_UINT16, ACPI_LPITH_OFFSET (Reserved), "Reserved", 0}, 731 {ACPI_DMT_UINT32, ACPI_LPITH_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 732 {ACPI_DMT_FLAG0, ACPI_LPITH_FLAG_OFFSET (Flags, 0), "State Disabled", 0}, 733 {ACPI_DMT_FLAG1, ACPI_LPITH_FLAG_OFFSET (Flags, 0), "No Counter", 0}, 734 ACPI_DMT_TERMINATOR 735 }; 736 737 /* LPIT Subtables */ 738 739 /* 0: Native C-state */ 740 741 ACPI_DMTABLE_INFO AcpiDmTableInfoLpit0[] = 742 { 743 {ACPI_DMT_GAS, ACPI_LPIT0_OFFSET (EntryTrigger), "Entry Trigger", 0}, 744 {ACPI_DMT_UINT32, ACPI_LPIT0_OFFSET (Residency), "Residency", 0}, 745 {ACPI_DMT_UINT32, ACPI_LPIT0_OFFSET (Latency), "Latency", 0}, 746 {ACPI_DMT_GAS, ACPI_LPIT0_OFFSET (ResidencyCounter), "Residency Counter", 0}, 747 {ACPI_DMT_UINT64, ACPI_LPIT0_OFFSET (CounterFrequency), "Counter Frequency", 0}, 748 ACPI_DMT_TERMINATOR 749 }; 750 /******************************************************************************* 751 * 752 * MADT - Multiple APIC Description Table and subtables 753 * 754 ******************************************************************************/ 755 756 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt[] = 757 { 758 {ACPI_DMT_UINT32, ACPI_MADT_OFFSET (Address), "Local Apic Address", 0}, 759 {ACPI_DMT_UINT32, ACPI_MADT_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 760 {ACPI_DMT_FLAG0, ACPI_MADT_FLAG_OFFSET (Flags,0), "PC-AT Compatibility", 0}, 761 ACPI_DMT_TERMINATOR 762 }; 763 764 /* Common Subtable header (one per Subtable) */ 765 766 ACPI_DMTABLE_INFO AcpiDmTableInfoMadtHdr[] = 767 { 768 {ACPI_DMT_MADT, ACPI_MADTH_OFFSET (Type), "Subtable Type", 0}, 769 {ACPI_DMT_UINT8, ACPI_MADTH_OFFSET (Length), "Length", DT_LENGTH}, 770 ACPI_DMT_TERMINATOR 771 }; 772 773 /* MADT Subtables */ 774 775 /* 0: processor APIC */ 776 777 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt0[] = 778 { 779 {ACPI_DMT_UINT8, ACPI_MADT0_OFFSET (ProcessorId), "Processor ID", 0}, 780 {ACPI_DMT_UINT8, ACPI_MADT0_OFFSET (Id), "Local Apic ID", 0}, 781 {ACPI_DMT_UINT32, ACPI_MADT0_OFFSET (LapicFlags), "Flags (decoded below)", DT_FLAG}, 782 {ACPI_DMT_FLAG0, ACPI_MADT0_FLAG_OFFSET (LapicFlags,0), "Processor Enabled", 0}, 783 {ACPI_DMT_FLAG1, ACPI_MADT0_FLAG_OFFSET (LapicFlags,0), "Runtime Online Capable", 0}, 784 ACPI_DMT_TERMINATOR 785 }; 786 787 /* 1: IO APIC */ 788 789 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt1[] = 790 { 791 {ACPI_DMT_UINT8, ACPI_MADT1_OFFSET (Id), "I/O Apic ID", 0}, 792 {ACPI_DMT_UINT8, ACPI_MADT1_OFFSET (Reserved), "Reserved", 0}, 793 {ACPI_DMT_UINT32, ACPI_MADT1_OFFSET (Address), "Address", 0}, 794 {ACPI_DMT_UINT32, ACPI_MADT1_OFFSET (GlobalIrqBase), "Interrupt", 0}, 795 ACPI_DMT_TERMINATOR 796 }; 797 798 /* 2: Interrupt Override */ 799 800 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt2[] = 801 { 802 {ACPI_DMT_UINT8, ACPI_MADT2_OFFSET (Bus), "Bus", 0}, 803 {ACPI_DMT_UINT8, ACPI_MADT2_OFFSET (SourceIrq), "Source", 0}, 804 {ACPI_DMT_UINT32, ACPI_MADT2_OFFSET (GlobalIrq), "Interrupt", 0}, 805 {ACPI_DMT_UINT16, ACPI_MADT2_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG}, 806 {ACPI_DMT_FLAGS0, ACPI_MADT2_FLAG_OFFSET (IntiFlags,0), "Polarity", 0}, 807 {ACPI_DMT_FLAGS2, ACPI_MADT2_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0}, 808 ACPI_DMT_TERMINATOR 809 }; 810 811 /* 3: NMI Sources */ 812 813 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt3[] = 814 { 815 {ACPI_DMT_UINT16, ACPI_MADT3_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG}, 816 {ACPI_DMT_FLAGS0, ACPI_MADT3_FLAG_OFFSET (IntiFlags,0), "Polarity", 0}, 817 {ACPI_DMT_FLAGS2, ACPI_MADT3_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0}, 818 {ACPI_DMT_UINT32, ACPI_MADT3_OFFSET (GlobalIrq), "Interrupt", 0}, 819 ACPI_DMT_TERMINATOR 820 }; 821 822 /* 4: Local APIC NMI */ 823 824 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt4[] = 825 { 826 {ACPI_DMT_UINT8, ACPI_MADT4_OFFSET (ProcessorId), "Processor ID", 0}, 827 {ACPI_DMT_UINT16, ACPI_MADT4_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG}, 828 {ACPI_DMT_FLAGS0, ACPI_MADT4_FLAG_OFFSET (IntiFlags,0), "Polarity", 0}, 829 {ACPI_DMT_FLAGS2, ACPI_MADT4_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0}, 830 {ACPI_DMT_UINT8, ACPI_MADT4_OFFSET (Lint), "Interrupt Input LINT", 0}, 831 ACPI_DMT_TERMINATOR 832 }; 833 834 /* 5: Address Override */ 835 836 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt5[] = 837 { 838 {ACPI_DMT_UINT16, ACPI_MADT5_OFFSET (Reserved), "Reserved", 0}, 839 {ACPI_DMT_UINT64, ACPI_MADT5_OFFSET (Address), "APIC Address", 0}, 840 ACPI_DMT_TERMINATOR 841 }; 842 843 /* 6: I/O Sapic */ 844 845 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt6[] = 846 { 847 {ACPI_DMT_UINT8, ACPI_MADT6_OFFSET (Id), "I/O Sapic ID", 0}, 848 {ACPI_DMT_UINT8, ACPI_MADT6_OFFSET (Reserved), "Reserved", 0}, 849 {ACPI_DMT_UINT32, ACPI_MADT6_OFFSET (GlobalIrqBase), "Interrupt Base", 0}, 850 {ACPI_DMT_UINT64, ACPI_MADT6_OFFSET (Address), "Address", 0}, 851 ACPI_DMT_TERMINATOR 852 }; 853 854 /* 7: Local Sapic */ 855 856 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt7[] = 857 { 858 {ACPI_DMT_UINT8, ACPI_MADT7_OFFSET (ProcessorId), "Processor ID", 0}, 859 {ACPI_DMT_UINT8, ACPI_MADT7_OFFSET (Id), "Local Sapic ID", 0}, 860 {ACPI_DMT_UINT8, ACPI_MADT7_OFFSET (Eid), "Local Sapic EID", 0}, 861 {ACPI_DMT_UINT24, ACPI_MADT7_OFFSET (Reserved[0]), "Reserved", 0}, 862 {ACPI_DMT_UINT32, ACPI_MADT7_OFFSET (LapicFlags), "Flags (decoded below)", DT_FLAG}, 863 {ACPI_DMT_FLAG0, ACPI_MADT7_FLAG_OFFSET (LapicFlags,0), "Processor Enabled", 0}, 864 {ACPI_DMT_UINT32, ACPI_MADT7_OFFSET (Uid), "Processor UID", 0}, 865 {ACPI_DMT_STRING, ACPI_MADT7_OFFSET (UidString[0]), "Processor UID String", 0}, 866 ACPI_DMT_TERMINATOR 867 }; 868 869 /* 8: Platform Interrupt Source */ 870 871 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt8[] = 872 { 873 {ACPI_DMT_UINT16, ACPI_MADT8_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG}, 874 {ACPI_DMT_FLAGS0, ACPI_MADT8_FLAG_OFFSET (IntiFlags,0), "Polarity", 0}, 875 {ACPI_DMT_FLAGS2, ACPI_MADT8_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0}, 876 {ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (Type), "InterruptType", 0}, 877 {ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (Id), "Processor ID", 0}, 878 {ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (Eid), "Processor EID", 0}, 879 {ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (IoSapicVector), "I/O Sapic Vector", 0}, 880 {ACPI_DMT_UINT32, ACPI_MADT8_OFFSET (GlobalIrq), "Interrupt", 0}, 881 {ACPI_DMT_UINT32, ACPI_MADT8_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 882 {ACPI_DMT_FLAG0, ACPI_MADT8_OFFSET (Flags), "CPEI Override", 0}, 883 ACPI_DMT_TERMINATOR 884 }; 885 886 /* 9: Processor Local X2_APIC (ACPI 4.0) */ 887 888 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt9[] = 889 { 890 {ACPI_DMT_UINT16, ACPI_MADT9_OFFSET (Reserved), "Reserved", 0}, 891 {ACPI_DMT_UINT32, ACPI_MADT9_OFFSET (LocalApicId), "Processor x2Apic ID", 0}, 892 {ACPI_DMT_UINT32, ACPI_MADT9_OFFSET (LapicFlags), "Flags (decoded below)", DT_FLAG}, 893 {ACPI_DMT_FLAG0, ACPI_MADT9_FLAG_OFFSET (LapicFlags,0), "Processor Enabled", 0}, 894 {ACPI_DMT_UINT32, ACPI_MADT9_OFFSET (Uid), "Processor UID", 0}, 895 ACPI_DMT_TERMINATOR 896 }; 897 898 /* 10: Local X2_APIC NMI (ACPI 4.0) */ 899 900 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt10[] = 901 { 902 {ACPI_DMT_UINT16, ACPI_MADT10_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG}, 903 {ACPI_DMT_FLAGS0, ACPI_MADT10_FLAG_OFFSET (IntiFlags,0), "Polarity", 0}, 904 {ACPI_DMT_FLAGS2, ACPI_MADT10_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0}, 905 {ACPI_DMT_UINT32, ACPI_MADT10_OFFSET (Uid), "Processor UID", 0}, 906 {ACPI_DMT_UINT8, ACPI_MADT10_OFFSET (Lint), "Interrupt Input LINT", 0}, 907 {ACPI_DMT_UINT24, ACPI_MADT10_OFFSET (Reserved[0]), "Reserved", 0}, 908 ACPI_DMT_TERMINATOR 909 }; 910 911 /* 11: Generic Interrupt Controller (ACPI 5.0) */ 912 913 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt11[] = 914 { 915 {ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (Reserved), "Reserved", 0}, 916 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (CpuInterfaceNumber), "CPU Interface Number", 0}, 917 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (Uid), "Processor UID", 0}, 918 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 919 {ACPI_DMT_FLAG0, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Processor Enabled", 0}, 920 {ACPI_DMT_FLAG1, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Performance Interrupt Trigger Mode", 0}, 921 {ACPI_DMT_FLAG2, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Virtual GIC Interrupt Trigger Mode", 0}, 922 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (ParkingVersion), "Parking Protocol Version", 0}, 923 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (PerformanceInterrupt), "Performance Interrupt", 0}, 924 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (ParkedAddress), "Parked Address", 0}, 925 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (BaseAddress), "Base Address", 0}, 926 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GicvBaseAddress), "Virtual GIC Base Address", 0}, 927 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GichBaseAddress), "Hypervisor GIC Base Address", 0}, 928 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (VgicInterrupt), "Virtual GIC Interrupt", 0}, 929 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GicrBaseAddress), "Redistributor Base Address", 0}, 930 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (ArmMpidr), "ARM MPIDR", 0}, 931 {ACPI_DMT_UINT8, ACPI_MADT11_OFFSET (EfficiencyClass), "Efficiency Class", 0}, 932 {ACPI_DMT_UINT8, ACPI_MADT11_OFFSET (Reserved2[0]), "Reserved", 0}, 933 {ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (SpeInterrupt), "SPE Overflow Interrupt", 0}, 934 {ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (TrbeInterrupt), "TRBE Interrupt", 0}, 935 ACPI_DMT_TERMINATOR 936 }; 937 938 /* 11: Generic Interrupt Controller (ACPI 5.0) - MADT revision 6 */ 939 940 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt11a[] = 941 { 942 {ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (Reserved), "Reserved", 0}, 943 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (CpuInterfaceNumber), "CPU Interface Number", 0}, 944 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (Uid), "Processor UID", 0}, 945 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 946 {ACPI_DMT_FLAG0, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Processor Enabled", 0}, 947 {ACPI_DMT_FLAG1, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Performance Interrupt Trigger Mode", 0}, 948 {ACPI_DMT_FLAG2, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Virtual GIC Interrupt Trigger Mode", 0}, 949 {ACPI_DMT_FLAG3, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Online Capable", 0}, 950 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (ParkingVersion), "Parking Protocol Version", 0}, 951 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (PerformanceInterrupt), "Performance Interrupt", 0}, 952 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (ParkedAddress), "Parked Address", 0}, 953 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (BaseAddress), "Base Address", 0}, 954 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GicvBaseAddress), "Virtual GIC Base Address", 0}, 955 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GichBaseAddress), "Hypervisor GIC Base Address", 0}, 956 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (VgicInterrupt), "Virtual GIC Interrupt", 0}, 957 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GicrBaseAddress), "Redistributor Base Address", 0}, 958 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (ArmMpidr), "ARM MPIDR", 0}, 959 {ACPI_DMT_UINT8, ACPI_MADT11_OFFSET (EfficiencyClass), "Efficiency Class", 0}, 960 {ACPI_DMT_UINT8, ACPI_MADT11_OFFSET (Reserved2[0]), "Reserved", 0}, 961 {ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (SpeInterrupt), "SPE Overflow Interrupt", 0}, 962 {ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (TrbeInterrupt), "TRBE Interrupt", 0}, 963 ACPI_DMT_TERMINATOR 964 }; 965 966 /* 11: Generic Interrupt Controller (ACPI 5.0) - MADT revision 7 */ 967 968 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt11b[] = 969 { 970 {ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (Reserved), "Reserved", 0}, 971 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (CpuInterfaceNumber), "CPU Interface Number", 0}, 972 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (Uid), "Processor UID", 0}, 973 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 974 {ACPI_DMT_FLAG0, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Processor Enabled", 0}, 975 {ACPI_DMT_FLAG1, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Performance Interrupt Trigger Mode", 0}, 976 {ACPI_DMT_FLAG2, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Virtual GIC Interrupt Trigger Mode", 0}, 977 {ACPI_DMT_FLAG3, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Online Capable", 0}, 978 {ACPI_DMT_FLAG4, ACPI_MADT11_FLAG_OFFSET (Flags,0), "GICR non-coherent", 0}, 979 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (ParkingVersion), "Parking Protocol Version", 0}, 980 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (PerformanceInterrupt), "Performance Interrupt", 0}, 981 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (ParkedAddress), "Parked Address", 0}, 982 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (BaseAddress), "Base Address", 0}, 983 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GicvBaseAddress), "Virtual GIC Base Address", 0}, 984 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GichBaseAddress), "Hypervisor GIC Base Address", 0}, 985 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (VgicInterrupt), "Virtual GIC Interrupt", 0}, 986 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GicrBaseAddress), "Redistributor Base Address", 0}, 987 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (ArmMpidr), "ARM MPIDR", 0}, 988 {ACPI_DMT_UINT8, ACPI_MADT11_OFFSET (EfficiencyClass), "Efficiency Class", 0}, 989 {ACPI_DMT_UINT8, ACPI_MADT11_OFFSET (Reserved2[0]), "Reserved", 0}, 990 {ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (SpeInterrupt), "SPE Overflow Interrupt", 0}, 991 {ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (TrbeInterrupt), "TRBE Interrupt", 0}, 992 ACPI_DMT_TERMINATOR 993 }; 994 995 /* 12: Generic Interrupt Distributor (ACPI 5.0) */ 996 997 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt12[] = 998 { 999 {ACPI_DMT_UINT16, ACPI_MADT12_OFFSET (Reserved), "Reserved", 0}, 1000 {ACPI_DMT_UINT32, ACPI_MADT12_OFFSET (GicId), "Local GIC Hardware ID", 0}, 1001 {ACPI_DMT_UINT64, ACPI_MADT12_OFFSET (BaseAddress), "Base Address", 0}, 1002 {ACPI_DMT_UINT32, ACPI_MADT12_OFFSET (GlobalIrqBase), "Interrupt Base", 0}, 1003 {ACPI_DMT_UINT8, ACPI_MADT12_OFFSET (Version), "Version", 0}, 1004 {ACPI_DMT_UINT24, ACPI_MADT12_OFFSET (Reserved2[0]), "Reserved", 0}, 1005 ACPI_DMT_TERMINATOR 1006 }; 1007 1008 /* 13: Generic MSI Frame (ACPI 5.1) */ 1009 1010 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt13[] = 1011 { 1012 {ACPI_DMT_UINT16, ACPI_MADT13_OFFSET (Reserved), "Reserved", 0}, 1013 {ACPI_DMT_UINT32, ACPI_MADT13_OFFSET (MsiFrameId), "MSI Frame ID", 0}, 1014 {ACPI_DMT_UINT64, ACPI_MADT13_OFFSET (BaseAddress), "Base Address", 0}, 1015 {ACPI_DMT_UINT32, ACPI_MADT13_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1016 {ACPI_DMT_FLAG0, ACPI_MADT13_FLAG_OFFSET (Flags,0), "Select SPI", 0}, 1017 {ACPI_DMT_UINT16, ACPI_MADT13_OFFSET (SpiCount), "SPI Count", 0}, 1018 {ACPI_DMT_UINT16, ACPI_MADT13_OFFSET (SpiBase), "SPI Base", 0}, 1019 ACPI_DMT_TERMINATOR 1020 }; 1021 1022 /* 14: Generic Redistributor (ACPI 5.1) */ 1023 1024 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt14[] = 1025 { 1026 {ACPI_DMT_UINT16, ACPI_MADT14_OFFSET (Reserved), "Reserved", 0}, 1027 {ACPI_DMT_UINT64, ACPI_MADT14_OFFSET (BaseAddress), "Base Address", 0}, 1028 {ACPI_DMT_UINT32, ACPI_MADT14_OFFSET (Length), "Length", 0}, 1029 ACPI_DMT_TERMINATOR 1030 }; 1031 1032 /* 14: Generic Redistributor (ACPI 5.1) */ 1033 1034 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt14a[] = 1035 { 1036 {ACPI_DMT_UINT8, ACPI_MADT14_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1037 {ACPI_DMT_FLAG0, ACPI_MADT14_FLAG_OFFSET (Flags,0), "GICR non-coherent", 0}, 1038 {ACPI_DMT_UINT8, ACPI_MADT14_OFFSET (Reserved), "Reserved", 0}, 1039 {ACPI_DMT_UINT64, ACPI_MADT14_OFFSET (BaseAddress), "Base Address", 0}, 1040 {ACPI_DMT_UINT32, ACPI_MADT14_OFFSET (Length), "Length", 0}, 1041 ACPI_DMT_TERMINATOR 1042 }; 1043 1044 /* 15: Generic Translator (ACPI 6.0) */ 1045 1046 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt15[] = 1047 { 1048 {ACPI_DMT_UINT16, ACPI_MADT15_OFFSET (Reserved), "Reserved", 0}, 1049 {ACPI_DMT_UINT32, ACPI_MADT15_OFFSET (TranslationId), "Translation ID", 0}, 1050 {ACPI_DMT_UINT64, ACPI_MADT15_OFFSET (BaseAddress), "Base Address", 0}, 1051 {ACPI_DMT_UINT32, ACPI_MADT15_OFFSET (Reserved2), "Reserved", 0}, 1052 ACPI_DMT_TERMINATOR 1053 }; 1054 1055 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt15a[] = 1056 { 1057 {ACPI_DMT_UINT8, ACPI_MADT15_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1058 {ACPI_DMT_FLAG0, ACPI_MADT15_FLAG_OFFSET (Flags,0), "GIC ITS non-coherent", 0}, 1059 {ACPI_DMT_UINT8, ACPI_MADT15_OFFSET (Reserved), "Reserved", 0}, 1060 {ACPI_DMT_UINT32, ACPI_MADT15_OFFSET (TranslationId), "Translation ID", 0}, 1061 {ACPI_DMT_UINT64, ACPI_MADT15_OFFSET (BaseAddress), "Base Address", 0}, 1062 {ACPI_DMT_UINT32, ACPI_MADT15_OFFSET (Reserved2), "Reserved", 0}, 1063 ACPI_DMT_TERMINATOR 1064 }; 1065 1066 /* 16: Multiprocessor wakeup structure (ACPI 6.6) */ 1067 1068 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt16[] = 1069 { 1070 {ACPI_DMT_UINT16, ACPI_MADT16_OFFSET (MailboxVersion), "Mailbox Version", 0}, 1071 {ACPI_DMT_UINT32, ACPI_MADT16_OFFSET (Reserved), "Reserved", 0}, 1072 {ACPI_DMT_UINT64, ACPI_MADT16_OFFSET (BaseAddress), "Mailbox Address", 0}, 1073 {ACPI_DMT_UINT64, ACPI_MADT16_OFFSET (ResetVector), "ResetVector", 0}, 1074 ACPI_DMT_TERMINATOR 1075 }; 1076 1077 /* 17: core interrupt controller */ 1078 1079 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt17[] = 1080 { 1081 {ACPI_DMT_UINT8, ACPI_MADT17_OFFSET (Version), "Version", 0}, 1082 {ACPI_DMT_UINT32, ACPI_MADT17_OFFSET (ProcessorId), "ProcessorId", 0}, 1083 {ACPI_DMT_UINT32, ACPI_MADT17_OFFSET (CoreId), "CoreId", 0}, 1084 {ACPI_DMT_UINT32, ACPI_MADT17_OFFSET (Flags), "Flags", 0}, 1085 ACPI_DMT_TERMINATOR 1086 }; 1087 1088 /* 18: Legacy I/O interrupt controller */ 1089 1090 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt18[] = 1091 { 1092 {ACPI_DMT_UINT8, ACPI_MADT18_OFFSET (Version), "Version", 0}, 1093 {ACPI_DMT_UINT64, ACPI_MADT18_OFFSET (Address), "Address", 0}, 1094 {ACPI_DMT_UINT16, ACPI_MADT18_OFFSET (Size), "Size", 0}, 1095 {ACPI_DMT_UINT16, ACPI_MADT18_OFFSET (Cascade), "Cascade", 0}, 1096 {ACPI_DMT_UINT64, ACPI_MADT18_OFFSET (CascadeMap), "CascadeMap", 0}, 1097 ACPI_DMT_TERMINATOR 1098 }; 1099 1100 /* 19: HT interrupt controller */ 1101 1102 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt19[] = 1103 { 1104 {ACPI_DMT_UINT8, ACPI_MADT19_OFFSET (Version), "Version", 0}, 1105 {ACPI_DMT_UINT64, ACPI_MADT19_OFFSET (Address), "Address", 0}, 1106 {ACPI_DMT_UINT16, ACPI_MADT19_OFFSET (Size), "Size", 0}, 1107 {ACPI_DMT_UINT64, ACPI_MADT19_OFFSET (Cascade), "Cascade", 0}, 1108 ACPI_DMT_TERMINATOR 1109 }; 1110 1111 /* 20: Extend I/O interrupt controller */ 1112 1113 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt20[] = 1114 { 1115 {ACPI_DMT_UINT8, ACPI_MADT20_OFFSET (Version), "Version", 0}, 1116 {ACPI_DMT_UINT8, ACPI_MADT20_OFFSET (Cascade), "Cascade", 0}, 1117 {ACPI_DMT_UINT8, ACPI_MADT20_OFFSET (Node), "Node", 0}, 1118 {ACPI_DMT_UINT64, ACPI_MADT20_OFFSET (NodeMap), "NodeMap", 0}, 1119 ACPI_DMT_TERMINATOR 1120 }; 1121 1122 /* 21: MSI controller */ 1123 1124 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt21[] = 1125 { 1126 {ACPI_DMT_UINT8, ACPI_MADT21_OFFSET (Version), "Version", 0}, 1127 {ACPI_DMT_UINT64, ACPI_MADT21_OFFSET (MsgAddress), "MsgAddress", 0}, 1128 {ACPI_DMT_UINT32, ACPI_MADT21_OFFSET (Start), "Start", 0}, 1129 {ACPI_DMT_UINT32, ACPI_MADT21_OFFSET (Count), "Count", 0}, 1130 ACPI_DMT_TERMINATOR 1131 }; 1132 1133 /* 22: BIO interrupt controller */ 1134 1135 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt22[] = 1136 { 1137 {ACPI_DMT_UINT8, ACPI_MADT22_OFFSET (Version), "Version", 0}, 1138 {ACPI_DMT_UINT64, ACPI_MADT22_OFFSET (Address), "Address", 0}, 1139 {ACPI_DMT_UINT16, ACPI_MADT22_OFFSET (Size), "Size", 0}, 1140 {ACPI_DMT_UINT16, ACPI_MADT22_OFFSET (Id), "Id", 0}, 1141 {ACPI_DMT_UINT16, ACPI_MADT22_OFFSET (GsiBase), "GsiBase", 0}, 1142 ACPI_DMT_TERMINATOR 1143 }; 1144 1145 /* 23: LPC interrupt controller */ 1146 1147 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt23[] = 1148 { 1149 {ACPI_DMT_UINT8, ACPI_MADT23_OFFSET (Version), "Version", 0}, 1150 {ACPI_DMT_UINT64, ACPI_MADT23_OFFSET (Address), "Address", 0}, 1151 {ACPI_DMT_UINT16, ACPI_MADT23_OFFSET (Size), "Size", 0}, 1152 {ACPI_DMT_UINT8, ACPI_MADT23_OFFSET (Cascade), "Cascade", 0}, 1153 ACPI_DMT_TERMINATOR 1154 }; 1155 1156 /* 24: RINTC interrupt controller */ 1157 1158 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt24[] = 1159 { 1160 {ACPI_DMT_UINT8, ACPI_MADT24_OFFSET (Version), "Version", 0}, 1161 {ACPI_DMT_UINT8, ACPI_MADT24_OFFSET (Reserved), "Reserved", 0}, 1162 {ACPI_DMT_UINT32, ACPI_MADT24_OFFSET (Flags), "Flags", 0}, 1163 {ACPI_DMT_UINT64, ACPI_MADT24_OFFSET (HartId), "HartId", 0}, 1164 {ACPI_DMT_UINT32, ACPI_MADT24_OFFSET (Uid), "Uid", 0}, 1165 {ACPI_DMT_UINT32, ACPI_MADT24_OFFSET (ExtIntcId), "ExtIntcId", 0}, 1166 {ACPI_DMT_UINT64, ACPI_MADT24_OFFSET (ImsicAddr), "ImsicAddr", 0}, 1167 {ACPI_DMT_UINT32, ACPI_MADT24_OFFSET (ImsicSize), "ImsicSize", 0}, 1168 ACPI_DMT_TERMINATOR 1169 }; 1170 1171 /* 25: RISC-V IMSIC interrupt controller */ 1172 1173 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt25[] = 1174 { 1175 {ACPI_DMT_UINT8, ACPI_MADT25_OFFSET (Version), "Version", 0}, 1176 {ACPI_DMT_UINT8, ACPI_MADT25_OFFSET (Reserved), "Reserved", 0}, 1177 {ACPI_DMT_UINT32, ACPI_MADT25_OFFSET (Flags), "Flags", 0}, 1178 {ACPI_DMT_UINT16, ACPI_MADT25_OFFSET (NumIds), "NumIds", 0}, 1179 {ACPI_DMT_UINT16, ACPI_MADT25_OFFSET (NumGuestIds), "NumGuestIds", 0}, 1180 {ACPI_DMT_UINT8, ACPI_MADT25_OFFSET (GuestIndexBits), "GuestIndexBits", 0}, 1181 {ACPI_DMT_UINT8, ACPI_MADT25_OFFSET (HartIndexBits), "HartIndexBits", 0}, 1182 {ACPI_DMT_UINT8, ACPI_MADT25_OFFSET (GroupIndexBits), "GroupIndexBits", 0}, 1183 {ACPI_DMT_UINT8, ACPI_MADT25_OFFSET (GroupIndexShift), "GroupIndexShift", 0}, 1184 ACPI_DMT_TERMINATOR 1185 }; 1186 1187 /* 26: RISC-V APLIC interrupt controller */ 1188 1189 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt26[] = 1190 { 1191 {ACPI_DMT_UINT8, ACPI_MADT26_OFFSET (Version), "Version", 0}, 1192 {ACPI_DMT_UINT8, ACPI_MADT26_OFFSET (Id), "Id", 0}, 1193 {ACPI_DMT_UINT32, ACPI_MADT26_OFFSET (Flags), "Flags", 0}, 1194 {ACPI_DMT_UINT64, ACPI_MADT26_OFFSET (HwId), "HwId", 0}, 1195 {ACPI_DMT_UINT16, ACPI_MADT26_OFFSET (NumIdcs), "NumIdcs", 0}, 1196 {ACPI_DMT_UINT16, ACPI_MADT26_OFFSET (NumSources), "NumSources", 0}, 1197 {ACPI_DMT_UINT32, ACPI_MADT26_OFFSET (GsiBase), "GsiBase", 0}, 1198 {ACPI_DMT_UINT64, ACPI_MADT26_OFFSET (BaseAddr), "BaseAddr", 0}, 1199 {ACPI_DMT_UINT32, ACPI_MADT26_OFFSET (Size), "Size", 0}, 1200 ACPI_DMT_TERMINATOR 1201 }; 1202 1203 /* 27: RISC-V PLIC interrupt controller */ 1204 1205 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt27[] = 1206 { 1207 {ACPI_DMT_UINT8, ACPI_MADT27_OFFSET (Version), "Version", 0}, 1208 {ACPI_DMT_UINT8, ACPI_MADT27_OFFSET (Id), "Id", 0}, 1209 {ACPI_DMT_UINT64, ACPI_MADT27_OFFSET (HwId), "HwId", 0}, 1210 {ACPI_DMT_UINT16, ACPI_MADT27_OFFSET (NumIrqs), "NumIrqs", 0}, 1211 {ACPI_DMT_UINT16, ACPI_MADT27_OFFSET (MaxPrio), "MaxPrio", 0}, 1212 {ACPI_DMT_UINT32, ACPI_MADT27_OFFSET (Flags), "Flags", 0}, 1213 {ACPI_DMT_UINT32, ACPI_MADT27_OFFSET (Size), "Size", 0}, 1214 {ACPI_DMT_UINT64, ACPI_MADT27_OFFSET (BaseAddr), "BaseAddr", 0}, 1215 {ACPI_DMT_UINT32, ACPI_MADT27_OFFSET (GsiBase), "GsiBase", 0}, 1216 ACPI_DMT_TERMINATOR 1217 }; 1218 1219 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt28[] = 1220 { 1221 {ACPI_DMT_UINT8, ACPI_MADT28_OFFSET (Version), "Gic version", 0}, 1222 {ACPI_DMT_UINT8, ACPI_MADT28_OFFSET (Reserved), "Reserved", 0}, 1223 {ACPI_DMT_UINT32, ACPI_MADT28_OFFSET (IrsId), "Irs Id", 0}, 1224 {ACPI_DMT_UINT32, ACPI_MADT28_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1225 {ACPI_DMT_FLAG0, ACPI_MADT28_FLAG_OFFSET (Flags,0), "GICV5 IRS non-coherent", 0}, 1226 {ACPI_DMT_UINT32, ACPI_MADT28_OFFSET (Reserved2), "Reserved", 0}, 1227 {ACPI_DMT_UINT64, ACPI_MADT28_OFFSET (ConfigBaseAddress), "Irs Config Frame Physical Base Address", 0}, 1228 {ACPI_DMT_UINT64, ACPI_MADT28_OFFSET (SetlpiBaseAddress), "Irs Setlpi Frame Physical Base Address", 0}, 1229 ACPI_DMT_TERMINATOR 1230 }; 1231 1232 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt29[] = 1233 { 1234 {ACPI_DMT_UINT8, ACPI_MADT29_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1235 {ACPI_DMT_FLAG0, ACPI_MADT29_FLAG_OFFSET (Flags,0), "GICV5 ITS non-coherent", 0}, 1236 {ACPI_DMT_UINT8, ACPI_MADT29_OFFSET (Reserved), "Reserved", 0}, 1237 {ACPI_DMT_UINT32, ACPI_MADT29_OFFSET (TranslatorId), "Gic Its Id", 0}, 1238 {ACPI_DMT_UINT64, ACPI_MADT29_OFFSET (BaseAddress), "Physical Base Address", 0}, 1239 ACPI_DMT_TERMINATOR 1240 }; 1241 1242 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt30[] = 1243 { 1244 {ACPI_DMT_UINT16, ACPI_MADT30_OFFSET (Reserved), "Reserved", 0}, 1245 {ACPI_DMT_UINT32, ACPI_MADT30_OFFSET (LinkedTranslatorId), "Linked Its Id", 0}, 1246 {ACPI_DMT_UINT32, ACPI_MADT30_OFFSET (TranslateFrameId), "Its Transalte Id", 0}, 1247 {ACPI_DMT_UINT32, ACPI_MADT30_OFFSET (Reserved2), "Reserved", 0}, 1248 {ACPI_DMT_UINT64, ACPI_MADT30_OFFSET (BaseAddress), "Its Translate Frame Physical Base Address", 0}, 1249 ACPI_DMT_TERMINATOR 1250 }; 1251 1252 /* 128: OEM data structure */ 1253 1254 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt128[] = 1255 { 1256 {ACPI_DMT_RAW_BUFFER, 0, "OEM Data", 0}, 1257 ACPI_DMT_TERMINATOR 1258 }; 1259 1260 /******************************************************************************* 1261 * 1262 * MCFG - PCI Memory Mapped Configuration table and Subtable 1263 * 1264 ******************************************************************************/ 1265 1266 ACPI_DMTABLE_INFO AcpiDmTableInfoMcfg[] = 1267 { 1268 {ACPI_DMT_UINT64, ACPI_MCFG_OFFSET (Reserved[0]), "Reserved", 0}, 1269 ACPI_DMT_TERMINATOR 1270 }; 1271 1272 ACPI_DMTABLE_INFO AcpiDmTableInfoMcfg0[] = 1273 { 1274 {ACPI_DMT_UINT64, ACPI_MCFG0_OFFSET (Address), "Base Address", 0}, 1275 {ACPI_DMT_UINT16, ACPI_MCFG0_OFFSET (PciSegment), "Segment Group Number", 0}, 1276 {ACPI_DMT_UINT8, ACPI_MCFG0_OFFSET (StartBusNumber), "Start Bus Number", 0}, 1277 {ACPI_DMT_UINT8, ACPI_MCFG0_OFFSET (EndBusNumber), "End Bus Number", 0}, 1278 {ACPI_DMT_UINT32, ACPI_MCFG0_OFFSET (Reserved), "Reserved", 0}, 1279 ACPI_DMT_TERMINATOR 1280 }; 1281 1282 1283 /******************************************************************************* 1284 * 1285 * MCHI - Management Controller Host Interface table 1286 * 1287 ******************************************************************************/ 1288 1289 ACPI_DMTABLE_INFO AcpiDmTableInfoMchi[] = 1290 { 1291 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (InterfaceType), "Interface Type", 0}, 1292 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (Protocol), "Protocol", 0}, 1293 {ACPI_DMT_UINT64, ACPI_MCHI_OFFSET (ProtocolData), "Protocol Data", 0}, 1294 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (InterruptType), "Interrupt Type", 0}, 1295 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (Gpe), "Gpe", 0}, 1296 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciDeviceFlag), "Pci Device Flag", 0}, 1297 {ACPI_DMT_UINT32, ACPI_MCHI_OFFSET (GlobalInterrupt), "Global Interrupt", 0}, 1298 {ACPI_DMT_GAS, ACPI_MCHI_OFFSET (ControlRegister), "Control Register", 0}, 1299 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciSegment), "Pci Segment", 0}, 1300 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciBus), "Pci Bus", 0}, 1301 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciDevice), "Pci Device", 0}, 1302 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciFunction), "Pci Function", 0}, 1303 ACPI_DMT_TERMINATOR 1304 }; 1305 1306 /******************************************************************************* 1307 * 1308 * MPAM - Memory System Resource Partitioning and Monitoring Tables 1309 * Arm's DEN0065 MPAM ACPI 2.0. December 2022. 1310 ******************************************************************************/ 1311 1312 /* MPAM subtables */ 1313 1314 /* 0: MPAM Resource Node Structure - A root MSC table. 1315 * Arm's DEN0065 MPAM ACPI 2.0. Table 4: MPAM MSC node body. 1316 */ 1317 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam0[] = 1318 { 1319 {ACPI_DMT_UINT16, ACPI_MPAM0_OFFSET (Length), "Length", 0}, 1320 {ACPI_DMT_UINT8, ACPI_MPAM0_OFFSET (InterfaceType), "Interface type", 0}, 1321 {ACPI_DMT_UINT8, ACPI_MPAM0_OFFSET (Reserved), "Reserved", 0}, 1322 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (Identifier), "Identifier", 0}, 1323 {ACPI_DMT_UINT64, ACPI_MPAM0_OFFSET (BaseAddress), "Base address", 0}, 1324 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (MMIOSize), "MMIO size", 0}, 1325 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (OverflowInterrupt), "Overflow interrupt", 0}, 1326 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (OverflowInterruptFlags), "Overflow interrupt flags", 0}, 1327 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (Reserved1), "Reserved1", 0}, 1328 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (OverflowInterruptAffinity), "Overflow interrupt affinity", 0}, 1329 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (ErrorInterrupt), "Error interrupt", 0}, 1330 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (ErrorInterruptFlags), "Error interrupt flags", 0}, 1331 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (Reserved2), "Reserved2", 0}, 1332 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (ErrorInterruptAffinity), "Error interrupt affinity", 0}, 1333 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (MaxNrdyUsec), "MAX_NRDY_USEC", 0}, 1334 {ACPI_DMT_NAME8, ACPI_MPAM0_OFFSET (HardwareIdLinkedDevice), "Hardware ID of linked device", 0}, 1335 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (InstanceIdLinkedDevice), "Instance ID of linked device", 0}, 1336 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (NumResourceNodes), "Number of resource nodes", 0}, 1337 1338 ACPI_DMT_TERMINATOR 1339 }; 1340 1341 /* 1: MPAM Resource (RIS) Node Structure - A subtable of MSC Nodes. 1342 * Arm's DEN0065 MPAM ACPI 2.0. Table 9: Resource node. 1343 */ 1344 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1[] = 1345 { 1346 {ACPI_DMT_UINT32, ACPI_MPAM1_OFFSET (Identifier), "Identifier", 0}, 1347 {ACPI_DMT_UINT8, ACPI_MPAM1_OFFSET (RISIndex), "RIS Index", 0}, 1348 {ACPI_DMT_UINT16, ACPI_MPAM1_OFFSET (Reserved1), "Reserved1", 0}, 1349 {ACPI_DMT_MPAM_LOCATOR, ACPI_MPAM1_OFFSET (LocatorType), "Locator type", 0}, 1350 ACPI_DMT_TERMINATOR 1351 }; 1352 1353 /* An RIS field part of the RIS subtable */ 1354 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1Deps[] = 1355 { 1356 {ACPI_DMT_UINT32, 0, "Number of functional dependencies", 0}, 1357 ACPI_DMT_TERMINATOR 1358 }; 1359 1360 /* 1A: MPAM Processor cache locator descriptor. A subtable of RIS. 1361 * Arm's DEN0065 MPAM ACPI 2.0. Table 13. 1362 */ 1363 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1A[] = 1364 { 1365 {ACPI_DMT_UINT64, ACPI_MPAM1A_OFFSET (CacheReference), "Cache reference", 0}, 1366 {ACPI_DMT_UINT32, ACPI_MPAM1A_OFFSET (Reserved), "Reserved", 0}, 1367 ACPI_DMT_TERMINATOR 1368 }; 1369 1370 /* 1B: MPAM Memory locator descriptor. A subtable of RIS. 1371 * Arm's DEN0065 MPAM ACPI 2.0. Table 14. 1372 */ 1373 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1B[] = 1374 { 1375 {ACPI_DMT_UINT64, ACPI_MPAM1B_OFFSET (ProximityDomain), "Proximity domain", 0}, 1376 {ACPI_DMT_UINT32, ACPI_MPAM1B_OFFSET (Reserved), "Reserved", 0}, 1377 ACPI_DMT_TERMINATOR 1378 }; 1379 1380 /* 1C: MPAM SMMU locator descriptor. A subtable of RIS. 1381 * Arm's DEN0065 MPAM ACPI 2.0. Table 15. 1382 */ 1383 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1C[] = 1384 { 1385 {ACPI_DMT_UINT64, ACPI_MPAM1C_OFFSET (SmmuInterface), "SMMU Interface", 0}, 1386 {ACPI_DMT_UINT32, ACPI_MPAM1C_OFFSET (Reserved), "Reserved", 0}, 1387 ACPI_DMT_TERMINATOR 1388 }; 1389 1390 /* 1D: MPAM Memory-side cache locator descriptor. A subtable of RIS. 1391 * Arm's DEN0065 MPAM ACPI 2.0. Table 16. 1392 */ 1393 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1D[] = 1394 { 1395 {ACPI_DMT_UINT56, ACPI_MPAM1D_OFFSET (Reserved), "Reserved", 0}, 1396 {ACPI_DMT_UINT8, ACPI_MPAM1D_OFFSET (Level), "Level", 0}, 1397 {ACPI_DMT_UINT32, ACPI_MPAM1D_OFFSET (Reference), "Reference", 0}, 1398 ACPI_DMT_TERMINATOR 1399 }; 1400 1401 /* 1E: MPAM ACPI device locator descriptor. A subtable of RIS. 1402 * Arm's DEN0065 MPAM ACPI 2.0. Table 17. 1403 */ 1404 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1E[] = 1405 { 1406 {ACPI_DMT_UINT64, ACPI_MPAM1E_OFFSET (AcpiHwId), "ACPI Hardware ID", 0}, 1407 {ACPI_DMT_UINT32, ACPI_MPAM1E_OFFSET (AcpiUniqueId), "ACPI Unique ID", 0}, 1408 ACPI_DMT_TERMINATOR 1409 }; 1410 1411 /* 1F: MPAM Interconnect locator descriptor. A subtable of RIS. 1412 * Arm's DEN0065 MPAM ACPI 2.0. Table 18. 1413 */ 1414 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1F[] = 1415 { 1416 {ACPI_DMT_UINT64, ACPI_MPAM1F_OFFSET (InterConnectDescTblOff), "Interconnect descriptor table offset", 0}, 1417 {ACPI_DMT_UINT32, ACPI_MPAM1F_OFFSET (Reserved), "Reserved", 0}, 1418 ACPI_DMT_TERMINATOR 1419 }; 1420 1421 /* 1G: MPAM Locator structure. 1422 * Arm's DEN0065 MPAM ACPI 2.0. Table 12. 1423 */ 1424 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1G[] = 1425 { 1426 {ACPI_DMT_UINT64, ACPI_MPAM1G_OFFSET (Descriptor1), "Descriptor1", 0}, 1427 {ACPI_DMT_UINT32, ACPI_MPAM1G_OFFSET (Descriptor2), "Descriptor2", 0}, 1428 ACPI_DMT_TERMINATOR 1429 }; 1430 1431 /* 2: MPAM Functional dependency descriptor. 1432 * Arm's DEN0065 MPAM ACPI 2.0. Table 10. 1433 */ 1434 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam2[] = 1435 { 1436 {ACPI_DMT_UINT32, ACPI_MPAM2_OFFSET (Producer), "Producer", 0}, 1437 {ACPI_DMT_UINT32, ACPI_MPAM2_OFFSET (Reserved), "Reserved", 0}, 1438 ACPI_DMT_TERMINATOR 1439 }; 1440 1441 1442 /******************************************************************************* 1443 * 1444 * MPST - Memory Power State Table 1445 * 1446 ******************************************************************************/ 1447 1448 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst[] = 1449 { 1450 {ACPI_DMT_UINT8, ACPI_MPST_OFFSET (ChannelId), "Channel ID", 0}, 1451 {ACPI_DMT_UINT24, ACPI_MPST_OFFSET (Reserved1[0]), "Reserved", 0}, 1452 {ACPI_DMT_UINT16, ACPI_MPST_OFFSET (PowerNodeCount), "Power Node Count", 0}, 1453 {ACPI_DMT_UINT16, ACPI_MPST_OFFSET (Reserved2), "Reserved", 0}, 1454 ACPI_DMT_TERMINATOR 1455 }; 1456 1457 /* MPST subtables */ 1458 1459 /* 0: Memory Power Node Structure */ 1460 1461 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst0[] = 1462 { 1463 {ACPI_DMT_UINT8, ACPI_MPST0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1464 {ACPI_DMT_FLAG0, ACPI_MPST0_FLAG_OFFSET (Flags,0), "Node Enabled", 0}, 1465 {ACPI_DMT_FLAG1, ACPI_MPST0_FLAG_OFFSET (Flags,0), "Power Managed", 0}, 1466 {ACPI_DMT_FLAG2, ACPI_MPST0_FLAG_OFFSET (Flags,0), "Hot Plug Capable", 0}, 1467 1468 {ACPI_DMT_UINT8, ACPI_MPST0_OFFSET (Reserved1), "Reserved", 0}, 1469 {ACPI_DMT_UINT16, ACPI_MPST0_OFFSET (NodeId), "Node ID", 0}, 1470 {ACPI_DMT_UINT32, ACPI_MPST0_OFFSET (Length), "Length", 0}, 1471 {ACPI_DMT_UINT64, ACPI_MPST0_OFFSET (RangeAddress), "Range Address", 0}, 1472 {ACPI_DMT_UINT64, ACPI_MPST0_OFFSET (RangeLength), "Range Length", 0}, 1473 {ACPI_DMT_UINT32, ACPI_MPST0_OFFSET (NumPowerStates), "Num Power States", 0}, 1474 {ACPI_DMT_UINT32, ACPI_MPST0_OFFSET (NumPhysicalComponents), "Num Physical Components", 0}, 1475 ACPI_DMT_TERMINATOR 1476 }; 1477 1478 /* 0A: Sub-subtable - Memory Power State Structure (follows Memory Power Node above) */ 1479 1480 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst0A[] = 1481 { 1482 {ACPI_DMT_UINT8, ACPI_MPST0A_OFFSET (PowerState), "Power State", 0}, 1483 {ACPI_DMT_UINT8, ACPI_MPST0A_OFFSET (InfoIndex), "InfoIndex", 0}, 1484 ACPI_DMT_TERMINATOR 1485 }; 1486 1487 /* 0B: Sub-subtable - Physical Component ID Structure (follows Memory Power State(s) above) */ 1488 1489 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst0B[] = 1490 { 1491 {ACPI_DMT_UINT16, ACPI_MPST0B_OFFSET (ComponentId), "Component Id", 0}, 1492 ACPI_DMT_TERMINATOR 1493 }; 1494 1495 /* 01: Power Characteristics Count (follows all Power Node(s) above) */ 1496 1497 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst1[] = 1498 { 1499 {ACPI_DMT_UINT16, ACPI_MPST1_OFFSET (CharacteristicsCount), "Characteristics Count", 0}, 1500 {ACPI_DMT_UINT16, ACPI_MPST1_OFFSET (Reserved), "Reserved", 0}, 1501 ACPI_DMT_TERMINATOR 1502 }; 1503 1504 /* 02: Memory Power State Characteristics Structure */ 1505 1506 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst2[] = 1507 { 1508 {ACPI_DMT_UINT8, ACPI_MPST2_OFFSET (StructureId), "Structure ID", 0}, 1509 {ACPI_DMT_UINT8, ACPI_MPST2_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1510 {ACPI_DMT_FLAG0, ACPI_MPST2_FLAG_OFFSET (Flags,0), "Memory Preserved", 0}, 1511 {ACPI_DMT_FLAG1, ACPI_MPST2_FLAG_OFFSET (Flags,0), "Auto Entry", 0}, 1512 {ACPI_DMT_FLAG2, ACPI_MPST2_FLAG_OFFSET (Flags,0), "Auto Exit", 0}, 1513 1514 {ACPI_DMT_UINT16, ACPI_MPST2_OFFSET (Reserved1), "Reserved", 0}, 1515 {ACPI_DMT_UINT32, ACPI_MPST2_OFFSET (AveragePower), "Average Power", 0}, 1516 {ACPI_DMT_UINT32, ACPI_MPST2_OFFSET (PowerSaving), "Power Saving", 0}, 1517 {ACPI_DMT_UINT64, ACPI_MPST2_OFFSET (ExitLatency), "Exit Latency", 0}, 1518 {ACPI_DMT_UINT64, ACPI_MPST2_OFFSET (Reserved2), "Reserved", 0}, 1519 ACPI_DMT_TERMINATOR 1520 }; 1521 1522 1523 /******************************************************************************* 1524 * 1525 * MRRM - Memory Range and Region Mapping Table 1526 * 1527 ******************************************************************************/ 1528 1529 ACPI_DMTABLE_INFO AcpiDmTableInfoMrrm[] = 1530 { 1531 {ACPI_DMT_UINT8, ACPI_MRRM_OFFSET (MaxMemRegion), "Max Memory Regions", 0}, 1532 {ACPI_DMT_UINT8, ACPI_MRRM_OFFSET (Flags), "Region Assignment Type", 0}, 1533 {ACPI_DMT_BUF26, ACPI_MRRM_OFFSET (Reserved), "Reserved", 0}, 1534 ACPI_DMT_TERMINATOR 1535 }; 1536 1537 /* MRRM Subtable */ 1538 1539 /* 0: Memory Range entry */ 1540 1541 ACPI_DMTABLE_INFO AcpiDmTableInfoMrrm0[] = 1542 { 1543 {ACPI_DMT_UINT16, ACPI_MRRM0_OFFSET (Header.Type), "Memory Range", 0}, 1544 {ACPI_DMT_UINT16, ACPI_MRRM0_OFFSET (Header.Length), "Length", DT_LENGTH}, 1545 {ACPI_DMT_UINT32, ACPI_MRRM0_OFFSET (Reserved0), "Reserved", 0}, 1546 {ACPI_DMT_UINT64, ACPI_MRRM0_OFFSET (AddrBase), "System Address Base", 0}, 1547 {ACPI_DMT_UINT64, ACPI_MRRM0_OFFSET (AddrLen), "System Address Length", 0}, 1548 {ACPI_DMT_UINT16, ACPI_MRRM0_OFFSET (RegionIdFlags), "Region Valid Flags", 0}, 1549 {ACPI_DMT_UINT8, ACPI_MRRM0_OFFSET (LocalRegionId), "Static Local Region ID", 0}, 1550 {ACPI_DMT_UINT8, ACPI_MRRM0_OFFSET (RemoteRegionId), "Static Remote Region ID", 0}, 1551 {ACPI_DMT_UINT32, ACPI_MRRM0_OFFSET (Reserved1), "Reserved", 0}, 1552 ACPI_DMT_TERMINATOR 1553 }; 1554 1555 1556 /******************************************************************************* 1557 * 1558 * MSCT - Maximum System Characteristics Table (ACPI 4.0) 1559 * 1560 ******************************************************************************/ 1561 1562 ACPI_DMTABLE_INFO AcpiDmTableInfoMsct[] = 1563 { 1564 {ACPI_DMT_UINT32, ACPI_MSCT_OFFSET (ProximityOffset), "Proximity Offset", 0}, 1565 {ACPI_DMT_UINT32, ACPI_MSCT_OFFSET (MaxProximityDomains), "Max Proximity Domains", 0}, 1566 {ACPI_DMT_UINT32, ACPI_MSCT_OFFSET (MaxClockDomains), "Max Clock Domains", 0}, 1567 {ACPI_DMT_UINT64, ACPI_MSCT_OFFSET (MaxAddress), "Max Physical Address", 0}, 1568 ACPI_DMT_TERMINATOR 1569 }; 1570 1571 /* Subtable - Maximum Proximity Domain Information. Version 1 */ 1572 1573 ACPI_DMTABLE_INFO AcpiDmTableInfoMsct0[] = 1574 { 1575 {ACPI_DMT_UINT8, ACPI_MSCT0_OFFSET (Revision), "Revision", 0}, 1576 {ACPI_DMT_UINT8, ACPI_MSCT0_OFFSET (Length), "Length", DT_LENGTH}, 1577 {ACPI_DMT_UINT32, ACPI_MSCT0_OFFSET (RangeStart), "Domain Range Start", 0}, 1578 {ACPI_DMT_UINT32, ACPI_MSCT0_OFFSET (RangeEnd), "Domain Range End", 0}, 1579 {ACPI_DMT_UINT32, ACPI_MSCT0_OFFSET (ProcessorCapacity), "Processor Capacity", 0}, 1580 {ACPI_DMT_UINT64, ACPI_MSCT0_OFFSET (MemoryCapacity), "Memory Capacity", 0}, 1581 ACPI_DMT_TERMINATOR 1582 }; 1583 1584 1585 /******************************************************************************* 1586 * 1587 * NFIT - NVDIMM Firmware Interface Table and Subtables - (ACPI 6.0) 1588 * 1589 ******************************************************************************/ 1590 1591 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit[] = 1592 { 1593 {ACPI_DMT_UINT32, ACPI_NFIT_OFFSET (Reserved), "Reserved", 0}, 1594 ACPI_DMT_TERMINATOR 1595 }; 1596 1597 /* Common Subtable header */ 1598 1599 ACPI_DMTABLE_INFO AcpiDmTableInfoNfitHdr[] = 1600 { 1601 {ACPI_DMT_NFIT, ACPI_NFITH_OFFSET (Type), "Subtable Type", 0}, 1602 {ACPI_DMT_UINT16, ACPI_NFITH_OFFSET (Length), "Length", DT_LENGTH}, 1603 ACPI_DMT_TERMINATOR 1604 }; 1605 1606 /* 0: System Physical Address Range Structure */ 1607 1608 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit0[] = 1609 { 1610 {ACPI_DMT_UINT16, ACPI_NFIT0_OFFSET (RangeIndex), "Range Index", 0}, 1611 {ACPI_DMT_UINT16, ACPI_NFIT0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1612 {ACPI_DMT_FLAG0, ACPI_NFIT0_FLAG_OFFSET (Flags,0), "Add/Online Operation Only", 0}, 1613 {ACPI_DMT_FLAG1, ACPI_NFIT0_FLAG_OFFSET (Flags,0), "Proximity Domain Valid", 0}, 1614 {ACPI_DMT_FLAG2, ACPI_NFIT0_FLAG_OFFSET (Flags,0), "Location Cookie Valid", 0}, 1615 {ACPI_DMT_UINT32, ACPI_NFIT0_OFFSET (Reserved), "Reserved", 0}, 1616 {ACPI_DMT_UINT32, ACPI_NFIT0_OFFSET (ProximityDomain), "Proximity Domain", 0}, 1617 {ACPI_DMT_UUID, ACPI_NFIT0_OFFSET (RangeGuid[0]), "Region Type GUID", 0}, 1618 {ACPI_DMT_UINT64, ACPI_NFIT0_OFFSET (Address), "Address Range Base", 0}, 1619 {ACPI_DMT_UINT64, ACPI_NFIT0_OFFSET (Length), "Address Range Length", 0}, 1620 {ACPI_DMT_UINT64, ACPI_NFIT0_OFFSET (MemoryMapping), "Memory Map Attribute", 0}, 1621 {ACPI_DMT_UINT64, ACPI_NFIT0_OFFSET (LocationCookie), "Location Cookie", 0}, /* ACPI 6.4 */ 1622 ACPI_DMT_TERMINATOR 1623 }; 1624 1625 /* 1: Memory Device to System Address Range Map Structure */ 1626 1627 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit1[] = 1628 { 1629 {ACPI_DMT_UINT32, ACPI_NFIT1_OFFSET (DeviceHandle), "Device Handle", 0}, 1630 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (PhysicalId), "Physical Id", 0}, 1631 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (RegionId), "Region Id", 0}, 1632 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (RangeIndex), "Range Index", 0}, 1633 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (RegionIndex), "Control Region Index", 0}, 1634 {ACPI_DMT_UINT64, ACPI_NFIT1_OFFSET (RegionSize), "Region Size", 0}, 1635 {ACPI_DMT_UINT64, ACPI_NFIT1_OFFSET (RegionOffset), "Region Offset", 0}, 1636 {ACPI_DMT_UINT64, ACPI_NFIT1_OFFSET (Address), "Address Region Base", 0}, 1637 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (InterleaveIndex), "Interleave Index", 0}, 1638 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (InterleaveWays), "Interleave Ways", 0}, 1639 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (Flags), "Flags", DT_FLAG}, 1640 {ACPI_DMT_FLAG0, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Save to device failed", 0}, 1641 {ACPI_DMT_FLAG1, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Restore from device failed", 0}, 1642 {ACPI_DMT_FLAG2, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Platform flush failed", 0}, 1643 {ACPI_DMT_FLAG3, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Device not armed", 0}, 1644 {ACPI_DMT_FLAG4, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Health events observed", 0}, 1645 {ACPI_DMT_FLAG5, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Health events enabled", 0}, 1646 {ACPI_DMT_FLAG6, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Mapping failed", 0}, 1647 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (Reserved), "Reserved", 0}, 1648 ACPI_DMT_TERMINATOR 1649 }; 1650 1651 /* 2: Interleave Structure */ 1652 1653 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit2[] = 1654 { 1655 {ACPI_DMT_UINT16, ACPI_NFIT2_OFFSET (InterleaveIndex), "Interleave Index", 0}, 1656 {ACPI_DMT_UINT16, ACPI_NFIT2_OFFSET (Reserved), "Reserved", 0}, 1657 {ACPI_DMT_UINT32, ACPI_NFIT2_OFFSET (LineCount), "Line Count", 0}, 1658 {ACPI_DMT_UINT32, ACPI_NFIT2_OFFSET (LineSize), "Line Size", 0}, 1659 ACPI_DMT_TERMINATOR 1660 }; 1661 1662 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit2a[] = 1663 { 1664 {ACPI_DMT_UINT32, 0, "Line Offset", DT_OPTIONAL}, 1665 ACPI_DMT_TERMINATOR 1666 }; 1667 1668 /* 3: SMBIOS Management Information Structure */ 1669 1670 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit3[] = 1671 { 1672 {ACPI_DMT_UINT32, ACPI_NFIT3_OFFSET (Reserved), "Reserved", 0}, 1673 ACPI_DMT_TERMINATOR 1674 }; 1675 1676 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit3a[] = 1677 { 1678 {ACPI_DMT_RAW_BUFFER, 0, "SMBIOS Table Entries", DT_OPTIONAL}, 1679 ACPI_DMT_TERMINATOR 1680 }; 1681 1682 /* 4: NVDIMM Control Region Structure */ 1683 1684 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit4[] = 1685 { 1686 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (RegionIndex), "Region Index", 0}, 1687 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (VendorId), "Vendor Id", 0}, 1688 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (DeviceId), "Device Id", 0}, 1689 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (RevisionId), "Revision Id", 0}, 1690 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (SubsystemVendorId), "Subsystem Vendor Id", 0}, 1691 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (SubsystemDeviceId), "Subsystem Device Id", 0}, 1692 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (SubsystemRevisionId), "Subsystem Revision Id", 0}, 1693 {ACPI_DMT_UINT8, ACPI_NFIT4_OFFSET (ValidFields), "Valid Fields", 0}, 1694 {ACPI_DMT_UINT8, ACPI_NFIT4_OFFSET (ManufacturingLocation), "Manufacturing Location", 0}, 1695 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (ManufacturingDate), "Manufacturing Date", 0}, 1696 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (Reserved[0]), "Reserved", 0}, 1697 {ACPI_DMT_UINT32, ACPI_NFIT4_OFFSET (SerialNumber), "Serial Number", 0}, 1698 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (Code), "Code", 0}, 1699 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (Windows), "Window Count", 0}, 1700 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (WindowSize), "Window Size", 0}, 1701 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (CommandOffset), "Command Offset", 0}, 1702 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (CommandSize), "Command Size", 0}, 1703 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (StatusOffset), "Status Offset", 0}, 1704 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (StatusSize), "Status Size", 0}, 1705 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (Flags), "Flags", DT_FLAG}, 1706 {ACPI_DMT_FLAG0, ACPI_NFIT4_FLAG_OFFSET (Flags,0), "Windows buffered", 0}, 1707 {ACPI_DMT_UINT48, ACPI_NFIT4_OFFSET (Reserved1[0]), "Reserved1", 0}, 1708 ACPI_DMT_TERMINATOR 1709 }; 1710 1711 /* 5: NVDIMM Block Data Window Region Structure */ 1712 1713 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit5[] = 1714 { 1715 {ACPI_DMT_UINT16, ACPI_NFIT5_OFFSET (RegionIndex), "Region Index", 0}, 1716 {ACPI_DMT_UINT16, ACPI_NFIT5_OFFSET (Windows), "Window Count", 0}, 1717 {ACPI_DMT_UINT64, ACPI_NFIT5_OFFSET (Offset), "Offset", 0}, 1718 {ACPI_DMT_UINT64, ACPI_NFIT5_OFFSET (Size), "Size", 0}, 1719 {ACPI_DMT_UINT64, ACPI_NFIT5_OFFSET (Capacity), "Capacity", 0}, 1720 {ACPI_DMT_UINT64, ACPI_NFIT5_OFFSET (StartAddress), "Start Address", 0}, 1721 ACPI_DMT_TERMINATOR 1722 }; 1723 1724 /* 6: Flush Hint Address Structure */ 1725 1726 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit6[] = 1727 { 1728 {ACPI_DMT_UINT32, ACPI_NFIT6_OFFSET (DeviceHandle), "Device Handle", 0}, 1729 {ACPI_DMT_UINT16, ACPI_NFIT6_OFFSET (HintCount), "Hint Count", 0}, 1730 {ACPI_DMT_UINT48, ACPI_NFIT6_OFFSET (Reserved[0]), "Reserved", 0}, 1731 ACPI_DMT_TERMINATOR 1732 }; 1733 1734 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit6a[] = 1735 { 1736 {ACPI_DMT_UINT64, 0, "Hint Address", DT_OPTIONAL}, 1737 ACPI_DMT_TERMINATOR 1738 }; 1739 1740 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit7[] = 1741 { 1742 {ACPI_DMT_UINT8, ACPI_NFIT7_OFFSET (HighestCapability), "Highest Capability", 0}, 1743 {ACPI_DMT_UINT24, ACPI_NFIT7_OFFSET (Reserved[0]), "Reserved", 0}, 1744 {ACPI_DMT_UINT32, ACPI_NFIT7_OFFSET (Capabilities), "Capabilities (decoded below)", DT_FLAG}, 1745 {ACPI_DMT_FLAG0, ACPI_NFIT7_FLAG_OFFSET (Capabilities,0), "Cache Flush to NVDIMM", 0}, 1746 {ACPI_DMT_FLAG1, ACPI_NFIT7_FLAG_OFFSET (Capabilities,0), "Memory Flush to NVDIMM", 0}, 1747 {ACPI_DMT_FLAG2, ACPI_NFIT7_FLAG_OFFSET (Capabilities,0), "Memory Mirroring", 0}, 1748 {ACPI_DMT_UINT32, ACPI_NFIT7_OFFSET (Reserved2), "Reserved", 0}, 1749 ACPI_DMT_TERMINATOR 1750 }; 1751 1752 1753 /******************************************************************************* 1754 * 1755 * PCCT - Platform Communications Channel Table (ACPI 5.0) 1756 * 1757 ******************************************************************************/ 1758 1759 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct[] = 1760 { 1761 {ACPI_DMT_UINT32, ACPI_PCCT_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1762 {ACPI_DMT_FLAG0, ACPI_PCCT_FLAG_OFFSET (Flags,0), "Platform", 0}, 1763 {ACPI_DMT_UINT64, ACPI_PCCT_OFFSET (Reserved), "Reserved", 0}, 1764 ACPI_DMT_TERMINATOR 1765 }; 1766 1767 /* PCCT subtables */ 1768 1769 ACPI_DMTABLE_INFO AcpiDmTableInfoPcctHdr[] = 1770 { 1771 {ACPI_DMT_PCCT, ACPI_PCCT0_OFFSET (Header.Type), "Subtable Type", 0}, 1772 {ACPI_DMT_UINT8, ACPI_PCCT0_OFFSET (Header.Length), "Length", DT_LENGTH}, 1773 ACPI_DMT_TERMINATOR 1774 }; 1775 1776 /* 0: Generic Communications Subspace */ 1777 1778 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct0[] = 1779 { 1780 {ACPI_DMT_UINT48, ACPI_PCCT0_OFFSET (Reserved[0]), "Reserved", 0}, 1781 {ACPI_DMT_UINT64, ACPI_PCCT0_OFFSET (BaseAddress), "Base Address", 0}, 1782 {ACPI_DMT_UINT64, ACPI_PCCT0_OFFSET (Length), "Address Length", 0}, 1783 {ACPI_DMT_GAS, ACPI_PCCT0_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 1784 {ACPI_DMT_UINT64, ACPI_PCCT0_OFFSET (PreserveMask), "Preserve Mask", 0}, 1785 {ACPI_DMT_UINT64, ACPI_PCCT0_OFFSET (WriteMask), "Write Mask", 0}, 1786 {ACPI_DMT_UINT32, ACPI_PCCT0_OFFSET (Latency), "Command Latency", 0}, 1787 {ACPI_DMT_UINT32, ACPI_PCCT0_OFFSET (MaxAccessRate), "Maximum Access Rate", 0}, 1788 {ACPI_DMT_UINT16, ACPI_PCCT0_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 1789 ACPI_DMT_TERMINATOR 1790 }; 1791 1792 /* 1: HW-reduced Communications Subspace (ACPI 5.1) */ 1793 1794 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct1[] = 1795 { 1796 {ACPI_DMT_UINT32, ACPI_PCCT1_OFFSET (PlatformInterrupt), "Platform Interrupt", 0}, 1797 {ACPI_DMT_UINT8, ACPI_PCCT1_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG}, 1798 {ACPI_DMT_FLAG0, ACPI_PCCT1_FLAG_OFFSET (Flags,0), "Polarity", 0}, 1799 {ACPI_DMT_FLAG1, ACPI_PCCT1_FLAG_OFFSET (Flags,0), "Mode", 0}, 1800 {ACPI_DMT_UINT8, ACPI_PCCT1_OFFSET (Reserved), "Reserved", 0}, 1801 {ACPI_DMT_UINT64, ACPI_PCCT1_OFFSET (BaseAddress), "Base Address", 0}, 1802 {ACPI_DMT_UINT64, ACPI_PCCT1_OFFSET (Length), "Address Length", 0}, 1803 {ACPI_DMT_GAS, ACPI_PCCT1_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 1804 {ACPI_DMT_UINT64, ACPI_PCCT1_OFFSET (PreserveMask), "Preserve Mask", 0}, 1805 {ACPI_DMT_UINT64, ACPI_PCCT1_OFFSET (WriteMask), "Write Mask", 0}, 1806 {ACPI_DMT_UINT32, ACPI_PCCT1_OFFSET (Latency), "Command Latency", 0}, 1807 {ACPI_DMT_UINT32, ACPI_PCCT1_OFFSET (MaxAccessRate), "Maximum Access Rate", 0}, 1808 {ACPI_DMT_UINT16, ACPI_PCCT1_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 1809 ACPI_DMT_TERMINATOR 1810 }; 1811 1812 /* 2: HW-reduced Communications Subspace Type 2 (ACPI 6.1) */ 1813 1814 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct2[] = 1815 { 1816 {ACPI_DMT_UINT32, ACPI_PCCT2_OFFSET (PlatformInterrupt), "Platform Interrupt", 0}, 1817 {ACPI_DMT_UINT8, ACPI_PCCT2_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG}, 1818 {ACPI_DMT_FLAG0, ACPI_PCCT2_FLAG_OFFSET (Flags,0), "Polarity", 0}, 1819 {ACPI_DMT_FLAG1, ACPI_PCCT2_FLAG_OFFSET (Flags,0), "Mode", 0}, 1820 {ACPI_DMT_UINT8, ACPI_PCCT2_OFFSET (Reserved), "Reserved", 0}, 1821 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (BaseAddress), "Base Address", 0}, 1822 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (Length), "Address Length", 0}, 1823 {ACPI_DMT_GAS, ACPI_PCCT2_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 1824 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (PreserveMask), "Preserve Mask", 0}, 1825 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (WriteMask), "Write Mask", 0}, 1826 {ACPI_DMT_UINT32, ACPI_PCCT2_OFFSET (Latency), "Command Latency", 0}, 1827 {ACPI_DMT_UINT32, ACPI_PCCT2_OFFSET (MaxAccessRate), "Maximum Access Rate", 0}, 1828 {ACPI_DMT_UINT16, ACPI_PCCT2_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 1829 {ACPI_DMT_GAS, ACPI_PCCT2_OFFSET (PlatformAckRegister), "Platform ACK Register", 0}, 1830 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (AckPreserveMask), "ACK Preserve Mask", 0}, 1831 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (AckWriteMask), "ACK Write Mask", 0}, 1832 ACPI_DMT_TERMINATOR 1833 }; 1834 1835 /* 3: Extended PCC Master Subspace Type 3 (ACPI 6.2) */ 1836 1837 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct3[] = 1838 { 1839 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (PlatformInterrupt), "Platform Interrupt", 0}, 1840 {ACPI_DMT_UINT8, ACPI_PCCT3_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG}, 1841 {ACPI_DMT_FLAG0, ACPI_PCCT3_FLAG_OFFSET (Flags,0), "Polarity", 0}, 1842 {ACPI_DMT_FLAG1, ACPI_PCCT3_FLAG_OFFSET (Flags,0), "Mode", 0}, 1843 {ACPI_DMT_UINT8, ACPI_PCCT3_OFFSET (Reserved1), "Reserved", 0}, 1844 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (BaseAddress), "Base Address", 0}, 1845 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (Length), "Address Length", 0}, 1846 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 1847 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (PreserveMask), "Preserve Mask", 0}, 1848 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (WriteMask), "Write Mask", 0}, 1849 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (Latency), "Command Latency", 0}, 1850 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (MaxAccessRate), "Maximum Access Rate", 0}, 1851 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 1852 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (PlatformAckRegister), "Platform ACK Register", 0}, 1853 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (AckPreserveMask), "ACK Preserve Mask", 0}, 1854 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (AckSetMask), "ACK Set Mask", 0}, 1855 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (Reserved2), "Reserved", 0}, 1856 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (CmdCompleteRegister), "Command Complete Register", 0}, 1857 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (CmdCompleteMask), "Command Complete Check Mask", 0}, 1858 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (CmdUpdateRegister), "Command Update Register", 0}, 1859 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (CmdUpdatePreserveMask), "Command Update Preserve Mask", 0}, 1860 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (CmdUpdateSetMask), "Command Update Set Mask", 0}, 1861 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (ErrorStatusRegister), "Error Status Register", 0}, 1862 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (ErrorStatusMask), "Error Status Mask", 0}, 1863 ACPI_DMT_TERMINATOR 1864 }; 1865 1866 /* 4: Extended PCC Slave Subspace Type 4 (ACPI 6.2) */ 1867 1868 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct4[] = 1869 { 1870 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (PlatformInterrupt), "Platform Interrupt", 0}, 1871 {ACPI_DMT_UINT8, ACPI_PCCT4_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG}, 1872 {ACPI_DMT_FLAG0, ACPI_PCCT4_FLAG_OFFSET (Flags,0), "Polarity", 0}, 1873 {ACPI_DMT_FLAG1, ACPI_PCCT4_FLAG_OFFSET (Flags,0), "Mode", 0}, 1874 {ACPI_DMT_UINT8, ACPI_PCCT4_OFFSET (Reserved1), "Reserved", 0}, 1875 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (BaseAddress), "Base Address", 0}, 1876 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (Length), "Address Length", 0}, 1877 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 1878 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (PreserveMask), "Preserve Mask", 0}, 1879 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (WriteMask), "Write Mask", 0}, 1880 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (Latency), "Command Latency", 0}, 1881 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (MaxAccessRate), "Maximum Access Rate", 0}, 1882 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 1883 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (PlatformAckRegister), "Platform ACK Register", 0}, 1884 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (AckPreserveMask), "ACK Preserve Mask", 0}, 1885 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (AckSetMask), "ACK Set Mask", 0}, 1886 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (Reserved2), "Reserved", 0}, 1887 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (CmdCompleteRegister), "Command Complete Register", 0}, 1888 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (CmdCompleteMask), "Command Complete Check Mask", 0}, 1889 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (CmdUpdateRegister), "Command Update Register", 0}, 1890 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (CmdUpdatePreserveMask), "Command Update Preserve Mask", 0}, 1891 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (CmdUpdateSetMask), "Command Update Set Mask", 0}, 1892 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (ErrorStatusRegister), "Error Status Register", 0}, 1893 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (ErrorStatusMask), "Error Status Mask", 0}, 1894 ACPI_DMT_TERMINATOR 1895 }; 1896 1897 /* 5: HW Registers based Communications Subspace */ 1898 1899 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct5[] = 1900 { 1901 {ACPI_DMT_UINT16, ACPI_PCCT5_OFFSET (Version), "Version", 0}, 1902 {ACPI_DMT_UINT64, ACPI_PCCT5_OFFSET (BaseAddress), "Base Address", 0}, 1903 {ACPI_DMT_UINT64, ACPI_PCCT5_OFFSET (Length), "Length", 0}, 1904 {ACPI_DMT_GAS, ACPI_PCCT5_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 1905 {ACPI_DMT_UINT64, ACPI_PCCT5_OFFSET (DoorbellPreserve), "Preserve Mask", 0}, 1906 {ACPI_DMT_UINT64, ACPI_PCCT5_OFFSET (DoorbellWrite), "Write Mask", 0}, 1907 {ACPI_DMT_GAS, ACPI_PCCT5_OFFSET (CmdCompleteRegister), "Command Complete Register", 0}, 1908 {ACPI_DMT_UINT64, ACPI_PCCT5_OFFSET (CmdCompleteMask), "Command Complete Check Mask", 0}, 1909 {ACPI_DMT_GAS, ACPI_PCCT5_OFFSET (ErrorStatusRegister), "Error Status Register", 0}, 1910 {ACPI_DMT_UINT64, ACPI_PCCT5_OFFSET (ErrorStatusMask), "Error Status Mask", 0}, 1911 {ACPI_DMT_UINT32, ACPI_PCCT5_OFFSET (NominalLatency), "Nominal Latency", 0}, 1912 {ACPI_DMT_UINT32, ACPI_PCCT5_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 1913 ACPI_DMT_TERMINATOR 1914 }; 1915 1916 1917 /******************************************************************************* 1918 * 1919 * PDTT - Platform Debug Trigger Table (ACPI 6.2) 1920 * 1921 ******************************************************************************/ 1922 1923 ACPI_DMTABLE_INFO AcpiDmTableInfoPdtt[] = 1924 { 1925 {ACPI_DMT_UINT8, ACPI_PDTT_OFFSET (TriggerCount), "Trigger Count", 0}, 1926 {ACPI_DMT_UINT24, ACPI_PDTT_OFFSET (Reserved), "Reserved", 0}, 1927 {ACPI_DMT_UINT32, ACPI_PDTT_OFFSET (ArrayOffset), "Array Offset", 0}, 1928 ACPI_DMT_TERMINATOR 1929 }; 1930 1931 ACPI_DMTABLE_INFO AcpiDmTableInfoPdtt0[] = 1932 { 1933 {ACPI_DMT_UINT8, ACPI_PDTT0_OFFSET (SubchannelId), "Subchannel Id", 0}, 1934 {ACPI_DMT_UINT8, ACPI_PDTT0_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG}, 1935 {ACPI_DMT_FLAG0, ACPI_PDTT0_FLAG_OFFSET (Flags,0), "Runtime Trigger", 0}, 1936 {ACPI_DMT_FLAG1, ACPI_PDTT0_FLAG_OFFSET (Flags,0), "Wait for Completion", 0}, 1937 {ACPI_DMT_FLAG2, ACPI_PDTT0_FLAG_OFFSET (Flags,0), "Trigger Order", 0}, 1938 ACPI_DMT_TERMINATOR 1939 }; 1940 1941 1942 /******************************************************************************* 1943 * 1944 * PHAT - Platform Health Assessment Table (ACPI 6.4) 1945 * 1946 ******************************************************************************/ 1947 1948 /* Common subtable header */ 1949 1950 ACPI_DMTABLE_INFO AcpiDmTableInfoPhatHdr[] = 1951 { 1952 {ACPI_DMT_PHAT, ACPI_PHATH_OFFSET (Type), "Subtable Type", 0}, 1953 {ACPI_DMT_UINT16, ACPI_PHATH_OFFSET (Length), "Length", DT_LENGTH}, 1954 {ACPI_DMT_UINT8, ACPI_PHATH_OFFSET (Revision), "Revision", 0}, 1955 ACPI_DMT_TERMINATOR 1956 }; 1957 1958 /* 0: Firmware version table */ 1959 1960 ACPI_DMTABLE_INFO AcpiDmTableInfoPhat0[] = 1961 { 1962 {ACPI_DMT_UINT24, ACPI_PHAT0_OFFSET (Reserved), "Reserved", 0}, 1963 {ACPI_DMT_UINT32, ACPI_PHAT0_OFFSET (ElementCount), "Element Count", 0}, 1964 ACPI_DMT_TERMINATOR 1965 }; 1966 1967 ACPI_DMTABLE_INFO AcpiDmTableInfoPhat0a[] = 1968 { 1969 {ACPI_DMT_UUID, ACPI_PHAT0A_OFFSET (Guid), "GUID", 0}, 1970 {ACPI_DMT_UINT64, ACPI_PHAT0A_OFFSET (VersionValue), "Version Value", 0}, 1971 {ACPI_DMT_UINT32, ACPI_PHAT0A_OFFSET (ProducerId), "Producer ID", 0}, 1972 ACPI_DMT_TERMINATOR 1973 }; 1974 1975 /* 1: Firmware Health Data Record */ 1976 1977 ACPI_DMTABLE_INFO AcpiDmTableInfoPhat1[] = 1978 { 1979 {ACPI_DMT_UINT16, ACPI_PHAT1_OFFSET (Reserved), "Reserved", 0}, 1980 {ACPI_DMT_UINT8, ACPI_PHAT1_OFFSET (Health), "Health", 0}, 1981 {ACPI_DMT_UUID, ACPI_PHAT1_OFFSET (DeviceGuid), "Device GUID", 0}, 1982 {ACPI_DMT_UINT32, ACPI_PHAT1_OFFSET (DeviceSpecificOffset), "Device-Specific Offset", 0}, 1983 ACPI_DMT_TERMINATOR 1984 }; 1985 1986 ACPI_DMTABLE_INFO AcpiDmTableInfoPhat1a[] = 1987 { 1988 {ACPI_DMT_UNICODE, 0, "Device Path", 0}, 1989 ACPI_DMT_TERMINATOR 1990 }; 1991 1992 ACPI_DMTABLE_INFO AcpiDmTableInfoPhat1b[] = 1993 { 1994 {ACPI_DMT_RAW_BUFFER, 0, "Device-Specific Data", DT_OPTIONAL}, 1995 ACPI_DMT_TERMINATOR 1996 }; 1997 1998 1999 /******************************************************************************* 2000 * 2001 * PMTT - Platform Memory Topology Table 2002 * 2003 ******************************************************************************/ 2004 2005 ACPI_DMTABLE_INFO AcpiDmTableInfoPmtt[] = 2006 { 2007 {ACPI_DMT_UINT32, ACPI_PMTT_OFFSET (MemoryDeviceCount), "Memory Device Count", 0}, 2008 ACPI_DMT_TERMINATOR 2009 }; 2010 2011 /* Common Subtable header (one per Subtable) */ 2012 2013 #define ACPI_DM_PMTT_HEADER \ 2014 {ACPI_DMT_PMTT, ACPI_PMTTH_OFFSET (Type), "Subtable Type", 0}, \ 2015 {ACPI_DMT_UINT8, ACPI_PMTTH_OFFSET (Reserved1), "Reserved", 0}, \ 2016 {ACPI_DMT_UINT16, ACPI_PMTTH_OFFSET (Length), "Length", DT_LENGTH}, \ 2017 {ACPI_DMT_UINT16, ACPI_PMTTH_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, \ 2018 {ACPI_DMT_FLAG0, ACPI_PMTTH_FLAG_OFFSET (Flags,0), "Top-level Device", 0}, \ 2019 {ACPI_DMT_FLAG1, ACPI_PMTTH_FLAG_OFFSET (Flags,0), "Physical Element", 0}, \ 2020 {ACPI_DMT_FLAGS2, ACPI_PMTTH_FLAG_OFFSET (Flags,0), "Memory Type", 0}, \ 2021 {ACPI_DMT_UINT16, ACPI_PMTTH_OFFSET (Reserved2), "Reserved", 0}, \ 2022 {ACPI_DMT_UINT32, ACPI_PMTTH_OFFSET (MemoryDeviceCount), "Memory Device Count", 0} 2023 2024 /* PMTT Subtables */ 2025 2026 /* 0: Socket */ 2027 2028 ACPI_DMTABLE_INFO AcpiDmTableInfoPmtt0[] = 2029 { 2030 ACPI_DM_PMTT_HEADER, 2031 {ACPI_DMT_UINT16, ACPI_PMTT0_OFFSET (SocketId), "Socket ID", 0}, 2032 {ACPI_DMT_UINT16, ACPI_PMTT0_OFFSET (Reserved), "Reserved", 0}, 2033 ACPI_DMT_TERMINATOR 2034 }; 2035 2036 /* 1: Memory Controller */ 2037 2038 ACPI_DMTABLE_INFO AcpiDmTableInfoPmtt1[] = 2039 { 2040 ACPI_DM_PMTT_HEADER, 2041 {ACPI_DMT_UINT16, ACPI_PMTT1_OFFSET (ControllerId), "Controller ID", 0}, 2042 {ACPI_DMT_UINT16, ACPI_PMTT1_OFFSET (Reserved), "Reserved", 0}, 2043 ACPI_DMT_TERMINATOR 2044 }; 2045 2046 /* 2: Physical Component */ 2047 2048 ACPI_DMTABLE_INFO AcpiDmTableInfoPmtt2[] = 2049 { 2050 ACPI_DM_PMTT_HEADER, 2051 {ACPI_DMT_UINT32, ACPI_PMTT2_OFFSET (BiosHandle), "Bios Handle", 0}, 2052 ACPI_DMT_TERMINATOR 2053 }; 2054 2055 /* 0xFF: Vendor Specific */ 2056 2057 ACPI_DMTABLE_INFO AcpiDmTableInfoPmttVendor[] = 2058 { 2059 ACPI_DM_PMTT_HEADER, 2060 {ACPI_DMT_UUID, ACPI_PMTT_VENDOR_OFFSET (TypeUuid), "Type Uuid", 0}, 2061 {ACPI_DMT_PMTT_VENDOR, ACPI_PMTT_VENDOR_OFFSET (Specific), "Vendor Data", 0}, 2062 ACPI_DMT_TERMINATOR 2063 }; 2064 2065 2066 /******************************************************************************* 2067 * 2068 * PPTT - Processor Properties Topology Table (ACPI 6.2) 2069 * 2070 ******************************************************************************/ 2071 2072 /* Main table consists of only the standard ACPI header - subtables follow */ 2073 2074 /* Common Subtable header (one per Subtable) */ 2075 2076 ACPI_DMTABLE_INFO AcpiDmTableInfoPpttHdr[] = 2077 { 2078 {ACPI_DMT_PPTT, ACPI_PPTTH_OFFSET (Type), "Subtable Type", 0}, 2079 {ACPI_DMT_UINT8, ACPI_PPTTH_OFFSET (Length), "Length", 0}, 2080 ACPI_DMT_TERMINATOR 2081 }; 2082 2083 /* 0: Processor hierarchy node */ 2084 2085 ACPI_DMTABLE_INFO AcpiDmTableInfoPptt0[] = 2086 { 2087 {ACPI_DMT_UINT16, ACPI_PPTT0_OFFSET (Reserved), "Reserved", 0}, 2088 {ACPI_DMT_UINT32, ACPI_PPTT0_OFFSET (Flags), "Flags (decoded below)", 0}, 2089 {ACPI_DMT_FLAG0, ACPI_PPTT0_FLAG_OFFSET (Flags,0), "Physical package", 0}, 2090 {ACPI_DMT_FLAG1, ACPI_PPTT0_FLAG_OFFSET (Flags,0), "ACPI Processor ID valid", 0}, 2091 {ACPI_DMT_FLAG2, ACPI_PPTT0_FLAG_OFFSET (Flags,0), "Processor is a thread", 0}, 2092 {ACPI_DMT_FLAG3, ACPI_PPTT0_FLAG_OFFSET (Flags,0), "Node is a leaf", 0}, 2093 {ACPI_DMT_FLAG4, ACPI_PPTT0_FLAG_OFFSET (Flags,0), "Identical Implementation", 0}, 2094 {ACPI_DMT_UINT32, ACPI_PPTT0_OFFSET (Parent), "Parent", 0}, 2095 {ACPI_DMT_UINT32, ACPI_PPTT0_OFFSET (AcpiProcessorId), "ACPI Processor ID", 0}, 2096 {ACPI_DMT_UINT32, ACPI_PPTT0_OFFSET (NumberOfPrivResources), "Private Resource Number", 0}, 2097 ACPI_DMT_TERMINATOR 2098 }; 2099 2100 ACPI_DMTABLE_INFO AcpiDmTableInfoPptt0a[] = 2101 { 2102 {ACPI_DMT_UINT32, 0, "Private Resource", DT_OPTIONAL}, 2103 ACPI_DMT_TERMINATOR 2104 }; 2105 2106 /* 1: Cache type */ 2107 2108 ACPI_DMTABLE_INFO AcpiDmTableInfoPptt1[] = 2109 { 2110 {ACPI_DMT_UINT16, ACPI_PPTT1_OFFSET (Reserved), "Reserved", 0}, 2111 {ACPI_DMT_UINT32, ACPI_PPTT1_OFFSET (Flags), "Flags (decoded below)", 0}, 2112 {ACPI_DMT_FLAG0, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Size valid", 0}, 2113 {ACPI_DMT_FLAG1, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Number of Sets valid", 0}, 2114 {ACPI_DMT_FLAG2, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Associativity valid", 0}, 2115 {ACPI_DMT_FLAG3, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Allocation Type valid", 0}, 2116 {ACPI_DMT_FLAG4, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Cache Type valid", 0}, 2117 {ACPI_DMT_FLAG5, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Write Policy valid", 0}, 2118 {ACPI_DMT_FLAG6, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Line Size valid", 0}, 2119 {ACPI_DMT_FLAG7, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Cache ID valid", 0}, 2120 {ACPI_DMT_UINT32, ACPI_PPTT1_OFFSET (NextLevelOfCache), "Next Level of Cache", 0}, 2121 {ACPI_DMT_UINT32, ACPI_PPTT1_OFFSET (Size), "Size", 0}, 2122 {ACPI_DMT_UINT32, ACPI_PPTT1_OFFSET (NumberOfSets), "Number of Sets", 0}, 2123 {ACPI_DMT_UINT8, ACPI_PPTT1_OFFSET (Associativity), "Associativity", 0}, 2124 {ACPI_DMT_UINT8, ACPI_PPTT1_OFFSET (Attributes), "Attributes", 0}, 2125 {ACPI_DMT_FLAGS0, ACPI_PPTT1_OFFSET (Attributes), "Allocation Type", 0}, 2126 {ACPI_DMT_FLAGS2, ACPI_PPTT1_OFFSET (Attributes), "Cache Type", 0}, 2127 {ACPI_DMT_FLAG4, ACPI_PPTT1_OFFSET (Attributes), "Write Policy", 0}, 2128 {ACPI_DMT_UINT16, ACPI_PPTT1_OFFSET (LineSize), "Line Size", 0}, 2129 ACPI_DMT_TERMINATOR 2130 }; 2131 2132 /* 1: cache type v1 */ 2133 2134 ACPI_DMTABLE_INFO AcpiDmTableInfoPptt1a[] = 2135 { 2136 {ACPI_DMT_UINT16, ACPI_PPTT1A_OFFSET (Reserved), "Reserved", 0}, 2137 {ACPI_DMT_UINT32, ACPI_PPTT1A_OFFSET (Flags), "Flags (decoded below)", 0}, 2138 {ACPI_DMT_FLAG0, ACPI_PPTT1A_FLAG_OFFSET (Flags,0), "Size valid", 0}, 2139 {ACPI_DMT_FLAG1, ACPI_PPTT1A_FLAG_OFFSET (Flags,0), "Number of Sets valid", 0}, 2140 {ACPI_DMT_FLAG2, ACPI_PPTT1A_FLAG_OFFSET (Flags,0), "Associativity valid", 0}, 2141 {ACPI_DMT_FLAG3, ACPI_PPTT1A_FLAG_OFFSET (Flags,0), "Allocation Type valid", 0}, 2142 {ACPI_DMT_FLAG4, ACPI_PPTT1A_FLAG_OFFSET (Flags,0), "Cache Type valid", 0}, 2143 {ACPI_DMT_FLAG5, ACPI_PPTT1A_FLAG_OFFSET (Flags,0), "Write Policy valid", 0}, 2144 {ACPI_DMT_FLAG6, ACPI_PPTT1A_FLAG_OFFSET (Flags,0), "Line Size valid", 0}, 2145 {ACPI_DMT_FLAG7, ACPI_PPTT1A_FLAG_OFFSET (Flags,0), "Cache ID valid", 0}, 2146 {ACPI_DMT_UINT32, ACPI_PPTT1A_OFFSET (NextLevelOfCache), "Next Level of Cache", 0}, 2147 {ACPI_DMT_UINT32, ACPI_PPTT1A_OFFSET (Size), "Size", 0}, 2148 {ACPI_DMT_UINT32, ACPI_PPTT1A_OFFSET (NumberOfSets), "Number of Sets", 0}, 2149 {ACPI_DMT_UINT8, ACPI_PPTT1A_OFFSET (Associativity), "Associativity", 0}, 2150 {ACPI_DMT_UINT8, ACPI_PPTT1A_OFFSET (Attributes), "Attributes", 0}, 2151 {ACPI_DMT_FLAGS0, ACPI_PPTT1A_OFFSET (Attributes), "Allocation Type", 0}, 2152 {ACPI_DMT_FLAGS2, ACPI_PPTT1A_OFFSET (Attributes), "Cache Type", 0}, 2153 {ACPI_DMT_FLAG4, ACPI_PPTT1A_OFFSET (Attributes), "Write Policy", 0}, 2154 {ACPI_DMT_UINT16, ACPI_PPTT1A_OFFSET (LineSize), "Line Size", 0}, 2155 {ACPI_DMT_UINT32, ACPI_PPTT1A_OFFSET (CacheId), "Cache ID", 0}, 2156 ACPI_DMT_TERMINATOR 2157 }; 2158 2159 /* 2: ID */ 2160 2161 ACPI_DMTABLE_INFO AcpiDmTableInfoPptt2[] = 2162 { 2163 {ACPI_DMT_UINT16, ACPI_PPTT2_OFFSET (Reserved), "Reserved", 0}, 2164 {ACPI_DMT_UINT32, ACPI_PPTT2_OFFSET (VendorId), "Vendor ID", 0}, 2165 {ACPI_DMT_UINT64, ACPI_PPTT2_OFFSET (Level1Id), "Level1 ID", 0}, 2166 {ACPI_DMT_UINT64, ACPI_PPTT2_OFFSET (Level2Id), "Level2 ID", 0}, 2167 {ACPI_DMT_UINT16, ACPI_PPTT2_OFFSET (MajorRev), "Major revision", 0}, 2168 {ACPI_DMT_UINT16, ACPI_PPTT2_OFFSET (MinorRev), "Minor revision", 0}, 2169 {ACPI_DMT_UINT16, ACPI_PPTT2_OFFSET (SpinRev), "Spin revision", 0}, 2170 ACPI_DMT_TERMINATOR 2171 }; 2172 2173 2174 /******************************************************************************* 2175 * 2176 * PRMT - Platform Runtime Mechanism Table 2177 * Version 1 2178 * 2179 ******************************************************************************/ 2180 2181 ACPI_DMTABLE_INFO AcpiDmTableInfoPrmtHdr[] = 2182 { 2183 {ACPI_DMT_UUID, ACPI_PRMTH_OFFSET (PlatformGuid[0]), "Platform GUID", 0}, 2184 {ACPI_DMT_UINT32, ACPI_PRMTH_OFFSET (ModuleInfoOffset), "Module info offset", 0}, 2185 {ACPI_DMT_UINT32, ACPI_PRMTH_OFFSET (ModuleInfoCount), "Module info count", 0}, 2186 ACPI_DMT_NEW_LINE, 2187 ACPI_DMT_TERMINATOR 2188 2189 }; 2190 2191 ACPI_DMTABLE_INFO AcpiDmTableInfoPrmtModule[] = 2192 { 2193 {ACPI_DMT_UINT16, ACPI_PRMT0_OFFSET (Revision), "Revision", 0}, 2194 {ACPI_DMT_UINT16, ACPI_PRMT0_OFFSET (Length), "Length", 0}, 2195 {ACPI_DMT_UUID, ACPI_PRMT0_OFFSET (ModuleGuid[0]), "Module GUID", 0}, 2196 {ACPI_DMT_UINT16, ACPI_PRMT0_OFFSET (MajorRev), "Major Revision", 0}, 2197 {ACPI_DMT_UINT16, ACPI_PRMT0_OFFSET (MinorRev), "Minor Revision", 0}, 2198 {ACPI_DMT_UINT16, ACPI_PRMT0_OFFSET (HandlerInfoCount), "Handler Info Count", 0}, 2199 {ACPI_DMT_UINT32, ACPI_PRMT0_OFFSET (HandlerInfoOffset), "Handler Info Offset", 0}, 2200 {ACPI_DMT_UINT64, ACPI_PRMT0_OFFSET (MmioListPointer), "Mmio List pointer", 0}, 2201 ACPI_DMT_NEW_LINE, 2202 ACPI_DMT_TERMINATOR 2203 2204 }; 2205 2206 ACPI_DMTABLE_INFO AcpiDmTableInfoPrmtHandler[] = 2207 { 2208 {ACPI_DMT_UINT16, ACPI_PRMT1_OFFSET (Revision), "Revision", 0}, 2209 {ACPI_DMT_UINT16, ACPI_PRMT1_OFFSET (Length), "Length", 0}, 2210 {ACPI_DMT_UUID, ACPI_PRMT1_OFFSET (HandlerGuid[0]), "Handler GUID", 0}, 2211 {ACPI_DMT_UINT64, ACPI_PRMT1_OFFSET (HandlerAddress), "Handler address", 0}, 2212 {ACPI_DMT_UINT64, ACPI_PRMT1_OFFSET (StaticDataBufferAddress),"Static Data Address", 0}, 2213 {ACPI_DMT_UINT64, ACPI_PRMT1_OFFSET (AcpiParamBufferAddress), "ACPI Parameter Address", 0}, 2214 ACPI_DMT_NEW_LINE, 2215 ACPI_DMT_TERMINATOR 2216 2217 }; 2218 2219 2220 /******************************************************************************* 2221 * 2222 * RASF - RAS Feature table 2223 * 2224 ******************************************************************************/ 2225 2226 ACPI_DMTABLE_INFO AcpiDmTableInfoRasf[] = 2227 { 2228 {ACPI_DMT_BUF12, ACPI_RASF_OFFSET (ChannelId[0]), "Channel ID", 0}, 2229 ACPI_DMT_TERMINATOR 2230 }; 2231 2232 2233 /******************************************************************************* 2234 * 2235 * RAS2 - RAS2 Feature table (ACPI 6.5) 2236 * 2237 ******************************************************************************/ 2238 2239 ACPI_DMTABLE_INFO AcpiDmTableInfoRas2[] = 2240 { 2241 {ACPI_DMT_UINT16, ACPI_RAS2_OFFSET (Reserved), "Reserved", 0}, 2242 {ACPI_DMT_UINT16, ACPI_RAS2_OFFSET (NumPccDescs), "Number of PCC Descriptors", 0}, 2243 ACPI_DMT_TERMINATOR 2244 }; 2245 2246 /* RAS2 PCC Descriptor */ 2247 2248 ACPI_DMTABLE_INFO AcpiDmTableInfoRas2PccDesc[] = 2249 { 2250 {ACPI_DMT_UINT8, ACPI_RAS2_PCC_DESC_OFFSET (ChannelId), "Channel ID", 0}, 2251 {ACPI_DMT_UINT16, ACPI_RAS2_PCC_DESC_OFFSET (Reserved), "Reserved", 0}, 2252 {ACPI_DMT_UINT8, ACPI_RAS2_PCC_DESC_OFFSET (FeatureType), "Feature Type", 0}, 2253 {ACPI_DMT_UINT32, ACPI_RAS2_PCC_DESC_OFFSET (Instance), "Instance", 0}, 2254 ACPI_DMT_TERMINATOR 2255 }; 2256 2257 2258 /******************************************************************************* 2259 * 2260 * RGRT - Regulatory Graphics Resource Table 2261 * 2262 ******************************************************************************/ 2263 2264 ACPI_DMTABLE_INFO AcpiDmTableInfoRgrt[] = 2265 { 2266 {ACPI_DMT_UINT16, ACPI_RGRT_OFFSET (Version), "Version", 0}, 2267 {ACPI_DMT_RGRT, ACPI_RGRT_OFFSET (ImageType), "Image Type", 0}, 2268 {ACPI_DMT_UINT8, ACPI_RGRT_OFFSET (Reserved), "Reserved", 0}, 2269 ACPI_DMT_TERMINATOR 2270 }; 2271 2272 /* 2273 * We treat the binary image field as its own subtable (to make 2274 * ACPI_DMT_RAW_BUFFER work properly). 2275 */ 2276 ACPI_DMTABLE_INFO AcpiDmTableInfoRgrt0[] = 2277 { 2278 {ACPI_DMT_RAW_BUFFER, 0, "Image", 0}, 2279 ACPI_DMT_TERMINATOR 2280 }; 2281 2282 2283 /******************************************************************************* 2284 * 2285 * RHCT - RISC-V Hart Capabilities Table 2286 * 2287 ******************************************************************************/ 2288 2289 ACPI_DMTABLE_INFO AcpiDmTableInfoRhct[] = 2290 { 2291 {ACPI_DMT_UINT32, ACPI_RHCT_OFFSET (Flags), "Flags", 0}, 2292 {ACPI_DMT_UINT64, ACPI_RHCT_OFFSET (TimeBaseFreq), "Timer Base Frequency", 0}, 2293 {ACPI_DMT_UINT32, ACPI_RHCT_OFFSET (NodeCount), "Number of nodes", 0}, 2294 {ACPI_DMT_UINT32, ACPI_RHCT_OFFSET (NodeOffset), "Offset to the node array", 0}, 2295 ACPI_DMT_TERMINATOR 2296 }; 2297 2298 2299 /* Common Subtable header (one per Subtable) */ 2300 2301 ACPI_DMTABLE_INFO AcpiDmTableInfoRhctNodeHdr[] = 2302 { 2303 {ACPI_DMT_RHCT, ACPI_RHCTH_OFFSET (Type), "Subtable Type", 0}, 2304 {ACPI_DMT_UINT16, ACPI_RHCTH_OFFSET (Length), "Length", DT_LENGTH}, 2305 {ACPI_DMT_UINT16, ACPI_RHCTH_OFFSET (Revision), "Revision", 0}, 2306 ACPI_DMT_TERMINATOR 2307 }; 2308 2309 /* 0: ISA string type */ 2310 2311 ACPI_DMTABLE_INFO AcpiDmTableInfoRhctIsa1[] = 2312 { 2313 {ACPI_DMT_UINT16, ACPI_RHCT0_OFFSET (IsaLength), "ISA string length", 0}, 2314 {ACPI_DMT_STRING, ACPI_RHCT0_OFFSET (Isa[0]), "ISA string", 0}, 2315 ACPI_DMT_TERMINATOR 2316 }; 2317 2318 2319 /* Optional padding field */ 2320 2321 ACPI_DMTABLE_INFO AcpiDmTableInfoRhctIsaPad[] = 2322 { 2323 {ACPI_DMT_RAW_BUFFER, 0, "Optional Padding", DT_OPTIONAL}, 2324 ACPI_DMT_TERMINATOR 2325 }; 2326 2327 /* 1: CMO node type */ 2328 2329 ACPI_DMTABLE_INFO AcpiDmTableInfoRhctCmo1[] = 2330 { 2331 {ACPI_DMT_UINT8, ACPI_RHCT1_OFFSET (Reserved), "Reserved", 0}, 2332 {ACPI_DMT_UINT8, ACPI_RHCT1_OFFSET (CbomSize), "CBOM Block Size", 0}, 2333 {ACPI_DMT_UINT8, ACPI_RHCT1_OFFSET (CbopSize), "CBOP Block Size", 0}, 2334 {ACPI_DMT_UINT8, ACPI_RHCT1_OFFSET (CbozSize), "CBOZ Block Size", 0}, 2335 ACPI_DMT_TERMINATOR 2336 }; 2337 2338 /* 2: MMU node type */ 2339 2340 ACPI_DMTABLE_INFO AcpiDmTableInfoRhctMmu1[] = 2341 { 2342 {ACPI_DMT_UINT8, ACPI_RHCT2_OFFSET (Reserved), "Reserved", 0}, 2343 {ACPI_DMT_UINT8, ACPI_RHCT2_OFFSET (MmuType), "MMU Type", 0}, 2344 ACPI_DMT_TERMINATOR 2345 }; 2346 2347 /* 0xFFFF: Hart Info type */ 2348 2349 ACPI_DMTABLE_INFO AcpiDmTableInfoRhctHartInfo1[] = 2350 { 2351 {ACPI_DMT_UINT16, ACPI_RHCTFFFF_OFFSET (NumOffsets), "Number of offsets", 0}, 2352 {ACPI_DMT_UINT32, ACPI_RHCTFFFF_OFFSET (Uid), "Processor UID", 0}, 2353 ACPI_DMT_TERMINATOR 2354 }; 2355 2356 2357 ACPI_DMTABLE_INFO AcpiDmTableInfoRhctHartInfo2[] = 2358 { 2359 {ACPI_DMT_UINT32, 0, "Nodes", DT_OPTIONAL}, 2360 ACPI_DMT_TERMINATOR 2361 }; 2362 2363 2364 /******************************************************************************* 2365 * 2366 * RIMT - RISC-V IO Mapping Table 2367 * 2368 * https://github.com/riscv-non-isa/riscv-acpi-rimt 2369 * 2370 ******************************************************************************/ 2371 2372 ACPI_DMTABLE_INFO AcpiDmTableInfoRimt[] = 2373 { 2374 {ACPI_DMT_UINT32, ACPI_RIMT_OFFSET (NumNodes), "Number of RIMT Nodes", 0}, 2375 {ACPI_DMT_UINT32, ACPI_RIMT_OFFSET (NodeOffset), "Offset to RIMT Node Array", 0}, 2376 {ACPI_DMT_UINT32, ACPI_RIMT_OFFSET (Reserved), "Reserved", 0}, 2377 ACPI_DMT_TERMINATOR 2378 }; 2379 2380 2381 /* Common Subtable header (one per Subtable) */ 2382 2383 ACPI_DMTABLE_INFO AcpiDmTableInfoRimtNodeHdr[] = 2384 { 2385 {ACPI_DMT_UINT8, ACPI_RIMTH_OFFSET (Type), "Type", 0}, 2386 {ACPI_DMT_UINT8, ACPI_RIMTH_OFFSET (Revision), "Revision", 0}, 2387 {ACPI_DMT_UINT16, ACPI_RIMTH_OFFSET (Length), "Length", 0}, 2388 {ACPI_DMT_UINT16, ACPI_RIMTH_OFFSET (Reserved), "Reserved", 0}, 2389 {ACPI_DMT_UINT16, ACPI_RIMTH_OFFSET (Id), "ID", 0}, 2390 ACPI_DMT_TERMINATOR 2391 }; 2392 2393 /* 0: IOMMU Node type */ 2394 2395 ACPI_DMTABLE_INFO AcpiDmTableInfoRimtIommu[] = 2396 { 2397 {ACPI_DMT_NAME8, ACPI_RIMTI_OFFSET (HardwareId), "Hardware ID", 0}, 2398 {ACPI_DMT_UINT64, ACPI_RIMTI_OFFSET (BaseAddress), "Base Address", 0}, 2399 {ACPI_DMT_UINT32, ACPI_RIMTI_OFFSET (Flags), "Flags", 0}, 2400 {ACPI_DMT_UINT32, ACPI_RIMTI_OFFSET (ProximityDomain), "Proximity Domain", 0}, 2401 {ACPI_DMT_UINT16, ACPI_RIMTI_OFFSET (PcieSegmentNumber), "PCIe Segment number", 0}, 2402 {ACPI_DMT_UINT16, ACPI_RIMTI_OFFSET (PcieBdf), "PCIe B/D/F", 0}, 2403 {ACPI_DMT_UINT16, ACPI_RIMTI_OFFSET (NumInterruptWires), "Number of interrupt wires", 0}, 2404 {ACPI_DMT_UINT16, ACPI_RIMTI_OFFSET (InterruptWireOffset), "Interrupt wire array offset", 0}, 2405 ACPI_DMT_TERMINATOR 2406 }; 2407 2408 2409 ACPI_DMTABLE_INFO AcpiDmTableInfoRimtIommuWire[] = 2410 { 2411 {ACPI_DMT_UINT32, ACPI_RIMTW_OFFSET (IrqNum), "Interrupt Number", 0}, 2412 {ACPI_DMT_UINT32, ACPI_RIMTW_OFFSET (Flags), "Flags", 0}, 2413 ACPI_DMT_TERMINATOR 2414 }; 2415 2416 /* 1: PCIE Root Complex Node type */ 2417 2418 ACPI_DMTABLE_INFO AcpiDmTableInfoRimtPcieRc[] = 2419 { 2420 {ACPI_DMT_UINT32, ACPI_RIMTP_OFFSET (Flags), "Flags", 0}, 2421 {ACPI_DMT_UINT16, ACPI_RIMTP_OFFSET (Reserved), "Reserved", 0}, 2422 {ACPI_DMT_UINT16, ACPI_RIMTP_OFFSET (PcieSegmentNumber), "PCIe Segment number", 0}, 2423 {ACPI_DMT_UINT16, ACPI_RIMTP_OFFSET (IdMappingOffset), "ID mapping array offset", 0}, 2424 {ACPI_DMT_UINT16, ACPI_RIMTP_OFFSET (NumIdMappings), "Number of ID mappings", 0}, 2425 ACPI_DMT_TERMINATOR 2426 }; 2427 2428 ACPI_DMTABLE_INFO AcpiDmTableInfoRimtIdMapping[] = 2429 { 2430 {ACPI_DMT_UINT32, ACPI_RIMTM_OFFSET (SourceIdBase), "Source ID Base", 0}, 2431 {ACPI_DMT_UINT32, ACPI_RIMTM_OFFSET (NumIds), "Number of IDs", 0}, 2432 {ACPI_DMT_UINT32, ACPI_RIMTM_OFFSET (DestIdBase), "Destination Device ID Base", 0}, 2433 {ACPI_DMT_UINT32, ACPI_RIMTM_OFFSET (DestOffset), "Destination IOMMU Offset", 0}, 2434 {ACPI_DMT_UINT32, ACPI_RIMTM_OFFSET (Flags), "Flags", 0}, 2435 ACPI_DMT_TERMINATOR 2436 }; 2437 2438 /* 2: Platform Device Node type */ 2439 2440 ACPI_DMTABLE_INFO AcpiDmTableInfoRimtPlatDev[] = 2441 { 2442 {ACPI_DMT_UINT16, ACPI_RIMTN_OFFSET (IdMappingOffset), "ID mapping array offset", 0}, 2443 {ACPI_DMT_UINT16, ACPI_RIMTN_OFFSET (NumIdMappings), "Number of ID mappings", 0}, 2444 {ACPI_DMT_STRING, ACPI_RIMTN_OFFSET (DeviceName[0]), "Device Object Name", 0}, 2445 ACPI_DMT_TERMINATOR 2446 }; 2447 2448 ACPI_DMTABLE_INFO AcpiDmTableInfoRimtPlatDevPad[] = 2449 { 2450 {ACPI_DMT_RAW_BUFFER, 0, "Padding", DT_OPTIONAL}, 2451 ACPI_DMT_TERMINATOR 2452 }; 2453 2454 2455 /******************************************************************************* 2456 * 2457 * S3PT - S3 Performance Table 2458 * 2459 ******************************************************************************/ 2460 2461 ACPI_DMTABLE_INFO AcpiDmTableInfoS3pt[] = 2462 { 2463 {ACPI_DMT_SIG, ACPI_S3PT_OFFSET (Signature[0]), "Signature", 0}, 2464 {ACPI_DMT_UINT32, ACPI_S3PT_OFFSET (Length), "Length", DT_LENGTH}, 2465 ACPI_DMT_TERMINATOR 2466 }; 2467 2468 /* S3PT subtable header */ 2469 2470 ACPI_DMTABLE_INFO AcpiDmTableInfoS3ptHdr[] = 2471 { 2472 {ACPI_DMT_UINT16, ACPI_S3PTH_OFFSET (Type), "Type", 0}, 2473 {ACPI_DMT_UINT8, ACPI_S3PTH_OFFSET (Length), "Length", DT_LENGTH}, 2474 {ACPI_DMT_UINT8, ACPI_S3PTH_OFFSET (Revision), "Revision", 0}, 2475 ACPI_DMT_TERMINATOR 2476 }; 2477 2478 /* 0: Basic S3 Resume Performance Record */ 2479 2480 ACPI_DMTABLE_INFO AcpiDmTableInfoS3pt0[] = 2481 { 2482 {ACPI_DMT_UINT32, ACPI_S3PT0_OFFSET (ResumeCount), "Resume Count", 0}, 2483 {ACPI_DMT_UINT64, ACPI_S3PT0_OFFSET (FullResume), "Full Resume", 0}, 2484 {ACPI_DMT_UINT64, ACPI_S3PT0_OFFSET (AverageResume), "Average Resume", 0}, 2485 ACPI_DMT_TERMINATOR 2486 }; 2487 2488 /* 1: Basic S3 Suspend Performance Record */ 2489 2490 ACPI_DMTABLE_INFO AcpiDmTableInfoS3pt1[] = 2491 { 2492 {ACPI_DMT_UINT64, ACPI_S3PT1_OFFSET (SuspendStart), "Suspend Start", 0}, 2493 {ACPI_DMT_UINT64, ACPI_S3PT1_OFFSET (SuspendEnd), "Suspend End", 0}, 2494 ACPI_DMT_TERMINATOR 2495 }; 2496 2497 2498 /******************************************************************************* 2499 * 2500 * SBST - Smart Battery Specification Table 2501 * 2502 ******************************************************************************/ 2503 2504 ACPI_DMTABLE_INFO AcpiDmTableInfoSbst[] = 2505 { 2506 {ACPI_DMT_UINT32, ACPI_SBST_OFFSET (WarningLevel), "Warning Level", 0}, 2507 {ACPI_DMT_UINT32, ACPI_SBST_OFFSET (LowLevel), "Low Level", 0}, 2508 {ACPI_DMT_UINT32, ACPI_SBST_OFFSET (CriticalLevel), "Critical Level", 0}, 2509 ACPI_DMT_TERMINATOR 2510 }; 2511 2512 2513 /******************************************************************************* 2514 * 2515 * SDEI - Software Delegated Exception Interface Descriptor Table 2516 * 2517 ******************************************************************************/ 2518 2519 ACPI_DMTABLE_INFO AcpiDmTableInfoSdei[] = 2520 { 2521 ACPI_DMT_TERMINATOR 2522 }; 2523 2524 2525 /******************************************************************************* 2526 * 2527 * SDEV - Secure Devices Table (ACPI 6.2) 2528 * 2529 ******************************************************************************/ 2530 2531 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev[] = 2532 { 2533 ACPI_DMT_TERMINATOR 2534 }; 2535 2536 /* Common Subtable header (one per Subtable) */ 2537 2538 ACPI_DMTABLE_INFO AcpiDmTableInfoSdevHdr[] = 2539 { 2540 {ACPI_DMT_SDEV, ACPI_SDEVH_OFFSET (Type), "Subtable Type", 0}, 2541 {ACPI_DMT_UINT8, ACPI_SDEVH_OFFSET (Flags), "Flags (decoded below)", 0}, 2542 {ACPI_DMT_FLAG0, ACPI_SDEVH_FLAG_OFFSET (Flags,0), "Allow handoff to unsecure OS", 0}, 2543 {ACPI_DMT_FLAG1, ACPI_SDEVH_FLAG_OFFSET (Flags,0), "Secure access components present", 0}, 2544 {ACPI_DMT_UINT16, ACPI_SDEVH_OFFSET (Length), "Length", DT_LENGTH}, 2545 ACPI_DMT_TERMINATOR 2546 }; 2547 2548 /* SDEV Subtables */ 2549 2550 /* 0: Namespace Device Based Secure Device Structure */ 2551 2552 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev0[] = 2553 { 2554 {ACPI_DMT_UINT16, ACPI_SDEV0_OFFSET (DeviceIdOffset), "Device ID Offset", 0}, 2555 {ACPI_DMT_UINT16, ACPI_SDEV0_OFFSET (DeviceIdLength), "Device ID Length", 0}, 2556 {ACPI_DMT_UINT16, ACPI_SDEV0_OFFSET (VendorDataOffset), "Vendor Data Offset", 0}, 2557 {ACPI_DMT_UINT16, ACPI_SDEV0_OFFSET (VendorDataLength), "Vendor Data Length", 0}, 2558 ACPI_DMT_TERMINATOR 2559 }; 2560 2561 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev0a[] = 2562 { 2563 {ACPI_DMT_STRING, 0, "Namepath", 0}, 2564 ACPI_DMT_TERMINATOR 2565 }; 2566 2567 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev0b[] = 2568 { 2569 {ACPI_DMT_UINT16, ACPI_SDEV0B_OFFSET (SecureComponentOffset), "Secure Access Components Offset", 0}, 2570 {ACPI_DMT_UINT16, ACPI_SDEV0B_OFFSET (SecureComponentLength), "Secure Access Components Length", 0}, 2571 ACPI_DMT_TERMINATOR 2572 }; 2573 2574 /* Secure access components */ 2575 2576 /* Common secure access components header secure access component */ 2577 2578 ACPI_DMTABLE_INFO AcpiDmTableInfoSdevSecCompHdr[] = 2579 { 2580 {ACPI_DMT_UINT8, ACPI_SDEVCH_OFFSET (Type), "Secure Component Type", 0}, 2581 {ACPI_DMT_UINT8, ACPI_SDEVCH_OFFSET (Flags), "Flags (decoded below)", 0}, 2582 {ACPI_DMT_UINT16, ACPI_SDEVCH_OFFSET (Length), "Length", 0}, 2583 ACPI_DMT_TERMINATOR 2584 }; 2585 2586 /* 0: Identification Based Secure Access Component */ 2587 2588 ACPI_DMTABLE_INFO AcpiDmTableInfoSdevSecCompId[] = 2589 { 2590 {ACPI_DMT_UINT16, ACPI_SDEVC0_OFFSET (HardwareIdOffset), "Hardware ID Offset", 0}, 2591 {ACPI_DMT_UINT16, ACPI_SDEVC0_OFFSET (HardwareIdLength), "Hardware ID Length", 0}, 2592 {ACPI_DMT_UINT16, ACPI_SDEVC0_OFFSET (SubsystemIdOffset), "Subsystem ID Offset", 0}, 2593 {ACPI_DMT_UINT16, ACPI_SDEVC0_OFFSET (SubsystemIdLength), "Subsystem ID Length", 0}, 2594 {ACPI_DMT_UINT16, ACPI_SDEVC0_OFFSET (HardwareRevision), "Hardware Revision", 0}, 2595 {ACPI_DMT_UINT8, ACPI_SDEVC0_OFFSET (HardwareRevPresent), "Hardware Rev Present", 0}, 2596 {ACPI_DMT_UINT8, ACPI_SDEVC0_OFFSET (ClassCodePresent), "Class Code Present", 0}, 2597 {ACPI_DMT_UINT8, ACPI_SDEVC0_OFFSET (PciBaseClass), "PCI Base Class", 0}, 2598 {ACPI_DMT_UINT8, ACPI_SDEVC0_OFFSET (PciSubClass), "PCI SubClass", 0}, 2599 {ACPI_DMT_UINT8, ACPI_SDEVC0_OFFSET (PciProgrammingXface), "PCI Programming Xface", 0}, 2600 ACPI_DMT_TERMINATOR 2601 }; 2602 2603 /* 1: Memory Based Secure Access Component */ 2604 2605 ACPI_DMTABLE_INFO AcpiDmTableInfoSdevSecCompMem[] = 2606 { 2607 {ACPI_DMT_UINT32, ACPI_SDEVC1_OFFSET (Reserved), "Reserved", 0}, 2608 {ACPI_DMT_UINT64, ACPI_SDEVC1_OFFSET (MemoryBaseAddress), "Memory Base Address", 0}, 2609 {ACPI_DMT_UINT64, ACPI_SDEVC1_OFFSET (MemoryLength), "Memory Length", 0}, 2610 ACPI_DMT_TERMINATOR 2611 }; 2612 2613 2614 /* 1: PCIe Endpoint Device Based Device Structure */ 2615 2616 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev1[] = 2617 { 2618 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (Segment), "Segment", 0}, 2619 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (StartBus), "Start Bus", 0}, 2620 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (PathOffset), "Path Offset", 0}, 2621 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (PathLength), "Path Length", 0}, 2622 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (VendorDataOffset), "Vendor Data Offset", 0}, 2623 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (VendorDataLength), "Vendor Data Length", 0}, 2624 ACPI_DMT_TERMINATOR 2625 }; 2626 2627 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev1a[] = 2628 { 2629 {ACPI_DMT_UINT8, ACPI_SDEV1A_OFFSET (Device), "Device", 0}, 2630 {ACPI_DMT_UINT8, ACPI_SDEV1A_OFFSET (Function), "Function", 0}, 2631 ACPI_DMT_TERMINATOR 2632 }; 2633 2634 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev1b[] = 2635 { 2636 {ACPI_DMT_RAW_BUFFER, 0, "Vendor Data", 0}, /*, DT_OPTIONAL}, */ 2637 ACPI_DMT_TERMINATOR 2638 }; 2639 2640 /*! [End] no source code translation !*/ 2641