1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (c) 2018 BayLibre, SAS.
4 * Author: Jerome Brunet <jbrunet@baylibre.com>
5 */
6
7 #include <linux/auxiliary_bus.h>
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
10 #include <linux/init.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/platform_device.h>
14 #include <linux/regmap.h>
15 #include <linux/reset.h>
16 #include <linux/slab.h>
17
18 #include "meson-clkc-utils.h"
19 #include "clk-regmap.h"
20 #include "clk-phase.h"
21 #include "sclk-div.h"
22
23 #include <dt-bindings/clock/axg-audio-clkc.h>
24
25 /* Audio clock register offsets */
26 #define AUDIO_CLK_GATE_EN 0x000
27 #define AUDIO_MCLK_A_CTRL 0x004
28 #define AUDIO_MCLK_B_CTRL 0x008
29 #define AUDIO_MCLK_C_CTRL 0x00C
30 #define AUDIO_MCLK_D_CTRL 0x010
31 #define AUDIO_MCLK_E_CTRL 0x014
32 #define AUDIO_MCLK_F_CTRL 0x018
33 #define AUDIO_MST_PAD_CTRL0 0x01c
34 #define AUDIO_MST_PAD_CTRL1 0x020
35 #define AUDIO_SW_RESET 0x024
36 #define AUDIO_MST_A_SCLK_CTRL0 0x040
37 #define AUDIO_MST_A_SCLK_CTRL1 0x044
38 #define AUDIO_MST_B_SCLK_CTRL0 0x048
39 #define AUDIO_MST_B_SCLK_CTRL1 0x04C
40 #define AUDIO_MST_C_SCLK_CTRL0 0x050
41 #define AUDIO_MST_C_SCLK_CTRL1 0x054
42 #define AUDIO_MST_D_SCLK_CTRL0 0x058
43 #define AUDIO_MST_D_SCLK_CTRL1 0x05C
44 #define AUDIO_MST_E_SCLK_CTRL0 0x060
45 #define AUDIO_MST_E_SCLK_CTRL1 0x064
46 #define AUDIO_MST_F_SCLK_CTRL0 0x068
47 #define AUDIO_MST_F_SCLK_CTRL1 0x06C
48 #define AUDIO_CLK_TDMIN_A_CTRL 0x080
49 #define AUDIO_CLK_TDMIN_B_CTRL 0x084
50 #define AUDIO_CLK_TDMIN_C_CTRL 0x088
51 #define AUDIO_CLK_TDMIN_LB_CTRL 0x08C
52 #define AUDIO_CLK_TDMOUT_A_CTRL 0x090
53 #define AUDIO_CLK_TDMOUT_B_CTRL 0x094
54 #define AUDIO_CLK_TDMOUT_C_CTRL 0x098
55 #define AUDIO_CLK_SPDIFIN_CTRL 0x09C
56 #define AUDIO_CLK_SPDIFOUT_CTRL 0x0A0
57 #define AUDIO_CLK_RESAMPLE_CTRL 0x0A4
58 #define AUDIO_CLK_LOCKER_CTRL 0x0A8
59 #define AUDIO_CLK_PDMIN_CTRL0 0x0AC
60 #define AUDIO_CLK_PDMIN_CTRL1 0x0B0
61 #define AUDIO_CLK_SPDIFOUT_B_CTRL 0x0B4
62
63 /* SM1 introduce new register and some shifts :( */
64 #define AUDIO_CLK_GATE_EN1 0x004
65 #define AUDIO_SM1_MCLK_A_CTRL 0x008
66 #define AUDIO_SM1_MCLK_B_CTRL 0x00C
67 #define AUDIO_SM1_MCLK_C_CTRL 0x010
68 #define AUDIO_SM1_MCLK_D_CTRL 0x014
69 #define AUDIO_SM1_MCLK_E_CTRL 0x018
70 #define AUDIO_SM1_MCLK_F_CTRL 0x01C
71 #define AUDIO_SM1_MST_PAD_CTRL0 0x020
72 #define AUDIO_SM1_MST_PAD_CTRL1 0x024
73 #define AUDIO_SM1_SW_RESET0 0x028
74 #define AUDIO_SM1_SW_RESET1 0x02C
75 #define AUDIO_CLK81_CTRL 0x030
76 #define AUDIO_CLK81_EN 0x034
77 #define AUDIO_EARCRX_CMDC_CLK_CTRL 0x0D0
78 #define AUDIO_EARCRX_DMAC_CLK_CTRL 0x0D4
79
80 #define AUD_GATE(_name, _reg, _bit, _pname, _iflags) { \
81 .data = &(struct clk_regmap_gate_data){ \
82 .offset = (_reg), \
83 .bit_idx = (_bit), \
84 }, \
85 .hw.init = &(struct clk_init_data) { \
86 .name = "aud_"#_name, \
87 .ops = &clk_regmap_gate_ops, \
88 .parent_names = (const char *[]){ #_pname }, \
89 .num_parents = 1, \
90 .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \
91 }, \
92 }
93
94 #define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags) { \
95 .data = &(struct clk_regmap_mux_data){ \
96 .offset = (_reg), \
97 .mask = (_mask), \
98 .shift = (_shift), \
99 .flags = (_dflags), \
100 }, \
101 .hw.init = &(struct clk_init_data){ \
102 .name = "aud_"#_name, \
103 .ops = &clk_regmap_mux_ops, \
104 .parent_data = _pdata, \
105 .num_parents = ARRAY_SIZE(_pdata), \
106 .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \
107 }, \
108 }
109
110 #define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) { \
111 .data = &(struct clk_regmap_div_data){ \
112 .offset = (_reg), \
113 .shift = (_shift), \
114 .width = (_width), \
115 .flags = (_dflags), \
116 }, \
117 .hw.init = &(struct clk_init_data){ \
118 .name = "aud_"#_name, \
119 .ops = &clk_regmap_divider_ops, \
120 .parent_names = (const char *[]){ #_pname }, \
121 .num_parents = 1, \
122 .flags = (_iflags), \
123 }, \
124 }
125
126 #define AUD_PCLK_GATE(_name, _reg, _bit) { \
127 .data = &(struct clk_regmap_gate_data){ \
128 .offset = (_reg), \
129 .bit_idx = (_bit), \
130 }, \
131 .hw.init = &(struct clk_init_data) { \
132 .name = "aud_"#_name, \
133 .ops = &clk_regmap_gate_ops, \
134 .parent_names = (const char *[]){ "aud_top" }, \
135 .num_parents = 1, \
136 }, \
137 }
138
139 #define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width, \
140 _hi_shift, _hi_width, _pname, _iflags) { \
141 .data = &(struct meson_sclk_div_data) { \
142 .div = { \
143 .reg_off = (_reg), \
144 .shift = (_div_shift), \
145 .width = (_div_width), \
146 }, \
147 .hi = { \
148 .reg_off = (_reg), \
149 .shift = (_hi_shift), \
150 .width = (_hi_width), \
151 }, \
152 }, \
153 .hw.init = &(struct clk_init_data) { \
154 .name = "aud_"#_name, \
155 .ops = &meson_sclk_div_ops, \
156 .parent_names = (const char *[]){ #_pname }, \
157 .num_parents = 1, \
158 .flags = (_iflags), \
159 }, \
160 }
161
162 #define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \
163 _pname, _iflags) { \
164 .data = &(struct meson_clk_triphase_data) { \
165 .ph0 = { \
166 .reg_off = (_reg), \
167 .shift = (_shift0), \
168 .width = (_width), \
169 }, \
170 .ph1 = { \
171 .reg_off = (_reg), \
172 .shift = (_shift1), \
173 .width = (_width), \
174 }, \
175 .ph2 = { \
176 .reg_off = (_reg), \
177 .shift = (_shift2), \
178 .width = (_width), \
179 }, \
180 }, \
181 .hw.init = &(struct clk_init_data) { \
182 .name = "aud_"#_name, \
183 .ops = &meson_clk_triphase_ops, \
184 .parent_names = (const char *[]){ #_pname }, \
185 .num_parents = 1, \
186 .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \
187 }, \
188 }
189
190 #define AUD_PHASE(_name, _reg, _width, _shift, _pname, _iflags) { \
191 .data = &(struct meson_clk_phase_data) { \
192 .ph = { \
193 .reg_off = (_reg), \
194 .shift = (_shift), \
195 .width = (_width), \
196 }, \
197 }, \
198 .hw.init = &(struct clk_init_data) { \
199 .name = "aud_"#_name, \
200 .ops = &meson_clk_phase_ops, \
201 .parent_names = (const char *[]){ #_pname }, \
202 .num_parents = 1, \
203 .flags = (_iflags), \
204 }, \
205 }
206
207 #define AUD_SCLK_WS(_name, _reg, _width, _shift_ph, _shift_ws, _pname, \
208 _iflags) { \
209 .data = &(struct meson_sclk_ws_inv_data) { \
210 .ph = { \
211 .reg_off = (_reg), \
212 .shift = (_shift_ph), \
213 .width = (_width), \
214 }, \
215 .ws = { \
216 .reg_off = (_reg), \
217 .shift = (_shift_ws), \
218 .width = (_width), \
219 }, \
220 }, \
221 .hw.init = &(struct clk_init_data) { \
222 .name = "aud_"#_name, \
223 .ops = &meson_clk_phase_ops, \
224 .parent_names = (const char *[]){ #_pname }, \
225 .num_parents = 1, \
226 .flags = (_iflags), \
227 }, \
228 }
229
230 /* Audio Master Clocks */
231 static const struct clk_parent_data mst_mux_parent_data[] = {
232 { .fw_name = "mst_in0", },
233 { .fw_name = "mst_in1", },
234 { .fw_name = "mst_in2", },
235 { .fw_name = "mst_in3", },
236 { .fw_name = "mst_in4", },
237 { .fw_name = "mst_in5", },
238 { .fw_name = "mst_in6", },
239 { .fw_name = "mst_in7", },
240 };
241
242 #define AUD_MST_MUX(_name, _reg, _flag) \
243 AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag, \
244 mst_mux_parent_data, 0)
245 #define AUD_MST_DIV(_name, _reg, _flag) \
246 AUD_DIV(_name##_div, _reg, 0, 16, _flag, \
247 aud_##_name##_sel, CLK_SET_RATE_PARENT)
248 #define AUD_MST_MCLK_GATE(_name, _reg) \
249 AUD_GATE(_name, _reg, 31, aud_##_name##_div, \
250 CLK_SET_RATE_PARENT)
251
252 #define AUD_MST_MCLK_MUX(_name, _reg) \
253 AUD_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST)
254 #define AUD_MST_MCLK_DIV(_name, _reg) \
255 AUD_MST_DIV(_name, _reg, CLK_DIVIDER_ROUND_CLOSEST)
256
257 #define AUD_MST_SYS_MUX(_name, _reg) \
258 AUD_MST_MUX(_name, _reg, 0)
259 #define AUD_MST_SYS_DIV(_name, _reg) \
260 AUD_MST_DIV(_name, _reg, 0)
261
262 /* Sample Clocks */
263 #define AUD_MST_SCLK_PRE_EN(_name, _reg) \
264 AUD_GATE(mst_##_name##_sclk_pre_en, _reg, 31, \
265 aud_mst_##_name##_mclk, 0)
266 #define AUD_MST_SCLK_DIV(_name, _reg) \
267 AUD_SCLK_DIV(mst_##_name##_sclk_div, _reg, 20, 10, 0, 0, \
268 aud_mst_##_name##_sclk_pre_en, \
269 CLK_SET_RATE_PARENT)
270 #define AUD_MST_SCLK_POST_EN(_name, _reg) \
271 AUD_GATE(mst_##_name##_sclk_post_en, _reg, 30, \
272 aud_mst_##_name##_sclk_div, CLK_SET_RATE_PARENT)
273 #define AUD_MST_SCLK(_name, _reg) \
274 AUD_TRIPHASE(mst_##_name##_sclk, _reg, 1, 0, 2, 4, \
275 aud_mst_##_name##_sclk_post_en, CLK_SET_RATE_PARENT)
276
277 #define AUD_MST_LRCLK_DIV(_name, _reg) \
278 AUD_SCLK_DIV(mst_##_name##_lrclk_div, _reg, 0, 10, 10, 10, \
279 aud_mst_##_name##_sclk_post_en, 0)
280 #define AUD_MST_LRCLK(_name, _reg) \
281 AUD_TRIPHASE(mst_##_name##_lrclk, _reg, 1, 1, 3, 5, \
282 aud_mst_##_name##_lrclk_div, CLK_SET_RATE_PARENT)
283
284 /* TDM bit clock sources */
285 static const struct clk_parent_data tdm_sclk_parent_data[] = {
286 { .name = "aud_mst_a_sclk", .index = -1, },
287 { .name = "aud_mst_b_sclk", .index = -1, },
288 { .name = "aud_mst_c_sclk", .index = -1, },
289 { .name = "aud_mst_d_sclk", .index = -1, },
290 { .name = "aud_mst_e_sclk", .index = -1, },
291 { .name = "aud_mst_f_sclk", .index = -1, },
292 { .fw_name = "slv_sclk0", },
293 { .fw_name = "slv_sclk1", },
294 { .fw_name = "slv_sclk2", },
295 { .fw_name = "slv_sclk3", },
296 { .fw_name = "slv_sclk4", },
297 { .fw_name = "slv_sclk5", },
298 { .fw_name = "slv_sclk6", },
299 { .fw_name = "slv_sclk7", },
300 { .fw_name = "slv_sclk8", },
301 { .fw_name = "slv_sclk9", },
302 };
303
304 /* TDM sample clock sources */
305 static const struct clk_parent_data tdm_lrclk_parent_data[] = {
306 { .name = "aud_mst_a_lrclk", .index = -1, },
307 { .name = "aud_mst_b_lrclk", .index = -1, },
308 { .name = "aud_mst_c_lrclk", .index = -1, },
309 { .name = "aud_mst_d_lrclk", .index = -1, },
310 { .name = "aud_mst_e_lrclk", .index = -1, },
311 { .name = "aud_mst_f_lrclk", .index = -1, },
312 { .fw_name = "slv_lrclk0", },
313 { .fw_name = "slv_lrclk1", },
314 { .fw_name = "slv_lrclk2", },
315 { .fw_name = "slv_lrclk3", },
316 { .fw_name = "slv_lrclk4", },
317 { .fw_name = "slv_lrclk5", },
318 { .fw_name = "slv_lrclk6", },
319 { .fw_name = "slv_lrclk7", },
320 { .fw_name = "slv_lrclk8", },
321 { .fw_name = "slv_lrclk9", },
322 };
323
324 #define AUD_TDM_SCLK_MUX(_name, _reg) \
325 AUD_MUX(tdm##_name##_sclk_sel, _reg, 0xf, 24, \
326 CLK_MUX_ROUND_CLOSEST, tdm_sclk_parent_data, 0)
327 #define AUD_TDM_SCLK_PRE_EN(_name, _reg) \
328 AUD_GATE(tdm##_name##_sclk_pre_en, _reg, 31, \
329 aud_tdm##_name##_sclk_sel, CLK_SET_RATE_PARENT)
330 #define AUD_TDM_SCLK_POST_EN(_name, _reg) \
331 AUD_GATE(tdm##_name##_sclk_post_en, _reg, 30, \
332 aud_tdm##_name##_sclk_pre_en, CLK_SET_RATE_PARENT)
333 #define AUD_TDM_SCLK(_name, _reg) \
334 AUD_PHASE(tdm##_name##_sclk, _reg, 1, 29, \
335 aud_tdm##_name##_sclk_post_en, \
336 CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT)
337 #define AUD_TDM_SCLK_WS(_name, _reg) \
338 AUD_SCLK_WS(tdm##_name##_sclk, _reg, 1, 29, 28, \
339 aud_tdm##_name##_sclk_post_en, \
340 CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT)
341
342 #define AUD_TDM_LRLCK(_name, _reg) \
343 AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20, \
344 CLK_MUX_ROUND_CLOSEST, tdm_lrclk_parent_data, 0)
345
346 /* Pad master clock sources */
347 static const struct clk_parent_data mclk_pad_ctrl_parent_data[] = {
348 { .name = "aud_mst_a_mclk", .index = -1, },
349 { .name = "aud_mst_b_mclk", .index = -1, },
350 { .name = "aud_mst_c_mclk", .index = -1, },
351 { .name = "aud_mst_d_mclk", .index = -1, },
352 { .name = "aud_mst_e_mclk", .index = -1, },
353 { .name = "aud_mst_f_mclk", .index = -1, },
354 };
355
356 /* Pad bit clock sources */
357 static const struct clk_parent_data sclk_pad_ctrl_parent_data[] = {
358 { .name = "aud_mst_a_sclk", .index = -1, },
359 { .name = "aud_mst_b_sclk", .index = -1, },
360 { .name = "aud_mst_c_sclk", .index = -1, },
361 { .name = "aud_mst_d_sclk", .index = -1, },
362 { .name = "aud_mst_e_sclk", .index = -1, },
363 { .name = "aud_mst_f_sclk", .index = -1, },
364 };
365
366 /* Pad sample clock sources */
367 static const struct clk_parent_data lrclk_pad_ctrl_parent_data[] = {
368 { .name = "aud_mst_a_lrclk", .index = -1, },
369 { .name = "aud_mst_b_lrclk", .index = -1, },
370 { .name = "aud_mst_c_lrclk", .index = -1, },
371 { .name = "aud_mst_d_lrclk", .index = -1, },
372 { .name = "aud_mst_e_lrclk", .index = -1, },
373 { .name = "aud_mst_f_lrclk", .index = -1, },
374 };
375
376 #define AUD_TDM_PAD_CTRL(_name, _reg, _shift, _parents) \
377 AUD_MUX(_name, _reg, 0x7, _shift, 0, _parents, \
378 CLK_SET_RATE_NO_REPARENT)
379
380 /* Common Clocks */
381 static struct clk_regmap ddr_arb =
382 AUD_PCLK_GATE(ddr_arb, AUDIO_CLK_GATE_EN, 0);
383 static struct clk_regmap pdm =
384 AUD_PCLK_GATE(pdm, AUDIO_CLK_GATE_EN, 1);
385 static struct clk_regmap tdmin_a =
386 AUD_PCLK_GATE(tdmin_a, AUDIO_CLK_GATE_EN, 2);
387 static struct clk_regmap tdmin_b =
388 AUD_PCLK_GATE(tdmin_b, AUDIO_CLK_GATE_EN, 3);
389 static struct clk_regmap tdmin_c =
390 AUD_PCLK_GATE(tdmin_c, AUDIO_CLK_GATE_EN, 4);
391 static struct clk_regmap tdmin_lb =
392 AUD_PCLK_GATE(tdmin_lb, AUDIO_CLK_GATE_EN, 5);
393 static struct clk_regmap tdmout_a =
394 AUD_PCLK_GATE(tdmout_a, AUDIO_CLK_GATE_EN, 6);
395 static struct clk_regmap tdmout_b =
396 AUD_PCLK_GATE(tdmout_b, AUDIO_CLK_GATE_EN, 7);
397 static struct clk_regmap tdmout_c =
398 AUD_PCLK_GATE(tdmout_c, AUDIO_CLK_GATE_EN, 8);
399 static struct clk_regmap frddr_a =
400 AUD_PCLK_GATE(frddr_a, AUDIO_CLK_GATE_EN, 9);
401 static struct clk_regmap frddr_b =
402 AUD_PCLK_GATE(frddr_b, AUDIO_CLK_GATE_EN, 10);
403 static struct clk_regmap frddr_c =
404 AUD_PCLK_GATE(frddr_c, AUDIO_CLK_GATE_EN, 11);
405 static struct clk_regmap toddr_a =
406 AUD_PCLK_GATE(toddr_a, AUDIO_CLK_GATE_EN, 12);
407 static struct clk_regmap toddr_b =
408 AUD_PCLK_GATE(toddr_b, AUDIO_CLK_GATE_EN, 13);
409 static struct clk_regmap toddr_c =
410 AUD_PCLK_GATE(toddr_c, AUDIO_CLK_GATE_EN, 14);
411 static struct clk_regmap loopback =
412 AUD_PCLK_GATE(loopback, AUDIO_CLK_GATE_EN, 15);
413 static struct clk_regmap spdifin =
414 AUD_PCLK_GATE(spdifin, AUDIO_CLK_GATE_EN, 16);
415 static struct clk_regmap spdifout =
416 AUD_PCLK_GATE(spdifout, AUDIO_CLK_GATE_EN, 17);
417 static struct clk_regmap resample =
418 AUD_PCLK_GATE(resample, AUDIO_CLK_GATE_EN, 18);
419 static struct clk_regmap power_detect =
420 AUD_PCLK_GATE(power_detect, AUDIO_CLK_GATE_EN, 19);
421
422 static struct clk_regmap spdifout_clk_sel =
423 AUD_MST_MCLK_MUX(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
424 static struct clk_regmap pdm_dclk_sel =
425 AUD_MST_MCLK_MUX(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
426 static struct clk_regmap spdifin_clk_sel =
427 AUD_MST_SYS_MUX(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
428 static struct clk_regmap pdm_sysclk_sel =
429 AUD_MST_SYS_MUX(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
430 static struct clk_regmap spdifout_b_clk_sel =
431 AUD_MST_MCLK_MUX(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
432
433 static struct clk_regmap spdifout_clk_div =
434 AUD_MST_MCLK_DIV(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
435 static struct clk_regmap pdm_dclk_div =
436 AUD_MST_MCLK_DIV(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
437 static struct clk_regmap spdifin_clk_div =
438 AUD_MST_SYS_DIV(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
439 static struct clk_regmap pdm_sysclk_div =
440 AUD_MST_SYS_DIV(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
441 static struct clk_regmap spdifout_b_clk_div =
442 AUD_MST_MCLK_DIV(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
443
444 static struct clk_regmap spdifout_clk =
445 AUD_MST_MCLK_GATE(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
446 static struct clk_regmap spdifin_clk =
447 AUD_MST_MCLK_GATE(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
448 static struct clk_regmap pdm_dclk =
449 AUD_MST_MCLK_GATE(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
450 static struct clk_regmap pdm_sysclk =
451 AUD_MST_MCLK_GATE(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
452 static struct clk_regmap spdifout_b_clk =
453 AUD_MST_MCLK_GATE(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
454
455 static struct clk_regmap mst_a_sclk_pre_en =
456 AUD_MST_SCLK_PRE_EN(a, AUDIO_MST_A_SCLK_CTRL0);
457 static struct clk_regmap mst_b_sclk_pre_en =
458 AUD_MST_SCLK_PRE_EN(b, AUDIO_MST_B_SCLK_CTRL0);
459 static struct clk_regmap mst_c_sclk_pre_en =
460 AUD_MST_SCLK_PRE_EN(c, AUDIO_MST_C_SCLK_CTRL0);
461 static struct clk_regmap mst_d_sclk_pre_en =
462 AUD_MST_SCLK_PRE_EN(d, AUDIO_MST_D_SCLK_CTRL0);
463 static struct clk_regmap mst_e_sclk_pre_en =
464 AUD_MST_SCLK_PRE_EN(e, AUDIO_MST_E_SCLK_CTRL0);
465 static struct clk_regmap mst_f_sclk_pre_en =
466 AUD_MST_SCLK_PRE_EN(f, AUDIO_MST_F_SCLK_CTRL0);
467
468 static struct clk_regmap mst_a_sclk_div =
469 AUD_MST_SCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
470 static struct clk_regmap mst_b_sclk_div =
471 AUD_MST_SCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
472 static struct clk_regmap mst_c_sclk_div =
473 AUD_MST_SCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
474 static struct clk_regmap mst_d_sclk_div =
475 AUD_MST_SCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
476 static struct clk_regmap mst_e_sclk_div =
477 AUD_MST_SCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
478 static struct clk_regmap mst_f_sclk_div =
479 AUD_MST_SCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
480
481 static struct clk_regmap mst_a_sclk_post_en =
482 AUD_MST_SCLK_POST_EN(a, AUDIO_MST_A_SCLK_CTRL0);
483 static struct clk_regmap mst_b_sclk_post_en =
484 AUD_MST_SCLK_POST_EN(b, AUDIO_MST_B_SCLK_CTRL0);
485 static struct clk_regmap mst_c_sclk_post_en =
486 AUD_MST_SCLK_POST_EN(c, AUDIO_MST_C_SCLK_CTRL0);
487 static struct clk_regmap mst_d_sclk_post_en =
488 AUD_MST_SCLK_POST_EN(d, AUDIO_MST_D_SCLK_CTRL0);
489 static struct clk_regmap mst_e_sclk_post_en =
490 AUD_MST_SCLK_POST_EN(e, AUDIO_MST_E_SCLK_CTRL0);
491 static struct clk_regmap mst_f_sclk_post_en =
492 AUD_MST_SCLK_POST_EN(f, AUDIO_MST_F_SCLK_CTRL0);
493
494 static struct clk_regmap mst_a_sclk =
495 AUD_MST_SCLK(a, AUDIO_MST_A_SCLK_CTRL1);
496 static struct clk_regmap mst_b_sclk =
497 AUD_MST_SCLK(b, AUDIO_MST_B_SCLK_CTRL1);
498 static struct clk_regmap mst_c_sclk =
499 AUD_MST_SCLK(c, AUDIO_MST_C_SCLK_CTRL1);
500 static struct clk_regmap mst_d_sclk =
501 AUD_MST_SCLK(d, AUDIO_MST_D_SCLK_CTRL1);
502 static struct clk_regmap mst_e_sclk =
503 AUD_MST_SCLK(e, AUDIO_MST_E_SCLK_CTRL1);
504 static struct clk_regmap mst_f_sclk =
505 AUD_MST_SCLK(f, AUDIO_MST_F_SCLK_CTRL1);
506
507 static struct clk_regmap mst_a_lrclk_div =
508 AUD_MST_LRCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
509 static struct clk_regmap mst_b_lrclk_div =
510 AUD_MST_LRCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
511 static struct clk_regmap mst_c_lrclk_div =
512 AUD_MST_LRCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
513 static struct clk_regmap mst_d_lrclk_div =
514 AUD_MST_LRCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
515 static struct clk_regmap mst_e_lrclk_div =
516 AUD_MST_LRCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
517 static struct clk_regmap mst_f_lrclk_div =
518 AUD_MST_LRCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
519
520 static struct clk_regmap mst_a_lrclk =
521 AUD_MST_LRCLK(a, AUDIO_MST_A_SCLK_CTRL1);
522 static struct clk_regmap mst_b_lrclk =
523 AUD_MST_LRCLK(b, AUDIO_MST_B_SCLK_CTRL1);
524 static struct clk_regmap mst_c_lrclk =
525 AUD_MST_LRCLK(c, AUDIO_MST_C_SCLK_CTRL1);
526 static struct clk_regmap mst_d_lrclk =
527 AUD_MST_LRCLK(d, AUDIO_MST_D_SCLK_CTRL1);
528 static struct clk_regmap mst_e_lrclk =
529 AUD_MST_LRCLK(e, AUDIO_MST_E_SCLK_CTRL1);
530 static struct clk_regmap mst_f_lrclk =
531 AUD_MST_LRCLK(f, AUDIO_MST_F_SCLK_CTRL1);
532
533 static struct clk_regmap tdmin_a_sclk_sel =
534 AUD_TDM_SCLK_MUX(in_a, AUDIO_CLK_TDMIN_A_CTRL);
535 static struct clk_regmap tdmin_b_sclk_sel =
536 AUD_TDM_SCLK_MUX(in_b, AUDIO_CLK_TDMIN_B_CTRL);
537 static struct clk_regmap tdmin_c_sclk_sel =
538 AUD_TDM_SCLK_MUX(in_c, AUDIO_CLK_TDMIN_C_CTRL);
539 static struct clk_regmap tdmin_lb_sclk_sel =
540 AUD_TDM_SCLK_MUX(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
541 static struct clk_regmap tdmout_a_sclk_sel =
542 AUD_TDM_SCLK_MUX(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
543 static struct clk_regmap tdmout_b_sclk_sel =
544 AUD_TDM_SCLK_MUX(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
545 static struct clk_regmap tdmout_c_sclk_sel =
546 AUD_TDM_SCLK_MUX(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
547
548 static struct clk_regmap tdmin_a_sclk_pre_en =
549 AUD_TDM_SCLK_PRE_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL);
550 static struct clk_regmap tdmin_b_sclk_pre_en =
551 AUD_TDM_SCLK_PRE_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL);
552 static struct clk_regmap tdmin_c_sclk_pre_en =
553 AUD_TDM_SCLK_PRE_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL);
554 static struct clk_regmap tdmin_lb_sclk_pre_en =
555 AUD_TDM_SCLK_PRE_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
556 static struct clk_regmap tdmout_a_sclk_pre_en =
557 AUD_TDM_SCLK_PRE_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
558 static struct clk_regmap tdmout_b_sclk_pre_en =
559 AUD_TDM_SCLK_PRE_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
560 static struct clk_regmap tdmout_c_sclk_pre_en =
561 AUD_TDM_SCLK_PRE_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
562
563 static struct clk_regmap tdmin_a_sclk_post_en =
564 AUD_TDM_SCLK_POST_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL);
565 static struct clk_regmap tdmin_b_sclk_post_en =
566 AUD_TDM_SCLK_POST_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL);
567 static struct clk_regmap tdmin_c_sclk_post_en =
568 AUD_TDM_SCLK_POST_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL);
569 static struct clk_regmap tdmin_lb_sclk_post_en =
570 AUD_TDM_SCLK_POST_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
571 static struct clk_regmap tdmout_a_sclk_post_en =
572 AUD_TDM_SCLK_POST_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
573 static struct clk_regmap tdmout_b_sclk_post_en =
574 AUD_TDM_SCLK_POST_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
575 static struct clk_regmap tdmout_c_sclk_post_en =
576 AUD_TDM_SCLK_POST_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
577
578 static struct clk_regmap tdmin_a_sclk =
579 AUD_TDM_SCLK(in_a, AUDIO_CLK_TDMIN_A_CTRL);
580 static struct clk_regmap tdmin_b_sclk =
581 AUD_TDM_SCLK(in_b, AUDIO_CLK_TDMIN_B_CTRL);
582 static struct clk_regmap tdmin_c_sclk =
583 AUD_TDM_SCLK(in_c, AUDIO_CLK_TDMIN_C_CTRL);
584 static struct clk_regmap tdmin_lb_sclk =
585 AUD_TDM_SCLK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
586
587 static struct clk_regmap tdmin_a_lrclk =
588 AUD_TDM_LRLCK(in_a, AUDIO_CLK_TDMIN_A_CTRL);
589 static struct clk_regmap tdmin_b_lrclk =
590 AUD_TDM_LRLCK(in_b, AUDIO_CLK_TDMIN_B_CTRL);
591 static struct clk_regmap tdmin_c_lrclk =
592 AUD_TDM_LRLCK(in_c, AUDIO_CLK_TDMIN_C_CTRL);
593 static struct clk_regmap tdmin_lb_lrclk =
594 AUD_TDM_LRLCK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
595 static struct clk_regmap tdmout_a_lrclk =
596 AUD_TDM_LRLCK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
597 static struct clk_regmap tdmout_b_lrclk =
598 AUD_TDM_LRLCK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
599 static struct clk_regmap tdmout_c_lrclk =
600 AUD_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
601
602 /* AXG Clocks */
603 static struct clk_regmap axg_tdmout_a_sclk =
604 AUD_TDM_SCLK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
605 static struct clk_regmap axg_tdmout_b_sclk =
606 AUD_TDM_SCLK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
607 static struct clk_regmap axg_tdmout_c_sclk =
608 AUD_TDM_SCLK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
609
610 /* AXG/G12A Clocks */
611 static struct clk_hw axg_aud_top = {
612 .init = &(struct clk_init_data) {
613 /* Provide aud_top signal name on axg and g12a */
614 .name = "aud_top",
615 .ops = &(const struct clk_ops) {},
616 .parent_data = &(const struct clk_parent_data) {
617 .fw_name = "pclk",
618 },
619 .num_parents = 1,
620 },
621 };
622
623 static struct clk_regmap mst_a_mclk_sel =
624 AUD_MST_MCLK_MUX(mst_a_mclk, AUDIO_MCLK_A_CTRL);
625 static struct clk_regmap mst_b_mclk_sel =
626 AUD_MST_MCLK_MUX(mst_b_mclk, AUDIO_MCLK_B_CTRL);
627 static struct clk_regmap mst_c_mclk_sel =
628 AUD_MST_MCLK_MUX(mst_c_mclk, AUDIO_MCLK_C_CTRL);
629 static struct clk_regmap mst_d_mclk_sel =
630 AUD_MST_MCLK_MUX(mst_d_mclk, AUDIO_MCLK_D_CTRL);
631 static struct clk_regmap mst_e_mclk_sel =
632 AUD_MST_MCLK_MUX(mst_e_mclk, AUDIO_MCLK_E_CTRL);
633 static struct clk_regmap mst_f_mclk_sel =
634 AUD_MST_MCLK_MUX(mst_f_mclk, AUDIO_MCLK_F_CTRL);
635
636 static struct clk_regmap mst_a_mclk_div =
637 AUD_MST_MCLK_DIV(mst_a_mclk, AUDIO_MCLK_A_CTRL);
638 static struct clk_regmap mst_b_mclk_div =
639 AUD_MST_MCLK_DIV(mst_b_mclk, AUDIO_MCLK_B_CTRL);
640 static struct clk_regmap mst_c_mclk_div =
641 AUD_MST_MCLK_DIV(mst_c_mclk, AUDIO_MCLK_C_CTRL);
642 static struct clk_regmap mst_d_mclk_div =
643 AUD_MST_MCLK_DIV(mst_d_mclk, AUDIO_MCLK_D_CTRL);
644 static struct clk_regmap mst_e_mclk_div =
645 AUD_MST_MCLK_DIV(mst_e_mclk, AUDIO_MCLK_E_CTRL);
646 static struct clk_regmap mst_f_mclk_div =
647 AUD_MST_MCLK_DIV(mst_f_mclk, AUDIO_MCLK_F_CTRL);
648
649 static struct clk_regmap mst_a_mclk =
650 AUD_MST_MCLK_GATE(mst_a_mclk, AUDIO_MCLK_A_CTRL);
651 static struct clk_regmap mst_b_mclk =
652 AUD_MST_MCLK_GATE(mst_b_mclk, AUDIO_MCLK_B_CTRL);
653 static struct clk_regmap mst_c_mclk =
654 AUD_MST_MCLK_GATE(mst_c_mclk, AUDIO_MCLK_C_CTRL);
655 static struct clk_regmap mst_d_mclk =
656 AUD_MST_MCLK_GATE(mst_d_mclk, AUDIO_MCLK_D_CTRL);
657 static struct clk_regmap mst_e_mclk =
658 AUD_MST_MCLK_GATE(mst_e_mclk, AUDIO_MCLK_E_CTRL);
659 static struct clk_regmap mst_f_mclk =
660 AUD_MST_MCLK_GATE(mst_f_mclk, AUDIO_MCLK_F_CTRL);
661
662 /* G12a clocks */
663 static struct clk_regmap g12a_tdm_mclk_pad_0 = AUD_TDM_PAD_CTRL(
664 mclk_pad_0, AUDIO_MST_PAD_CTRL0, 0, mclk_pad_ctrl_parent_data);
665 static struct clk_regmap g12a_tdm_mclk_pad_1 = AUD_TDM_PAD_CTRL(
666 mclk_pad_1, AUDIO_MST_PAD_CTRL0, 4, mclk_pad_ctrl_parent_data);
667 static struct clk_regmap g12a_tdm_lrclk_pad_0 = AUD_TDM_PAD_CTRL(
668 lrclk_pad_0, AUDIO_MST_PAD_CTRL1, 16, lrclk_pad_ctrl_parent_data);
669 static struct clk_regmap g12a_tdm_lrclk_pad_1 = AUD_TDM_PAD_CTRL(
670 lrclk_pad_1, AUDIO_MST_PAD_CTRL1, 20, lrclk_pad_ctrl_parent_data);
671 static struct clk_regmap g12a_tdm_lrclk_pad_2 = AUD_TDM_PAD_CTRL(
672 lrclk_pad_2, AUDIO_MST_PAD_CTRL1, 24, lrclk_pad_ctrl_parent_data);
673 static struct clk_regmap g12a_tdm_sclk_pad_0 = AUD_TDM_PAD_CTRL(
674 sclk_pad_0, AUDIO_MST_PAD_CTRL1, 0, sclk_pad_ctrl_parent_data);
675 static struct clk_regmap g12a_tdm_sclk_pad_1 = AUD_TDM_PAD_CTRL(
676 sclk_pad_1, AUDIO_MST_PAD_CTRL1, 4, sclk_pad_ctrl_parent_data);
677 static struct clk_regmap g12a_tdm_sclk_pad_2 = AUD_TDM_PAD_CTRL(
678 sclk_pad_2, AUDIO_MST_PAD_CTRL1, 8, sclk_pad_ctrl_parent_data);
679
680 static struct clk_regmap g12a_tdmout_a_sclk =
681 AUD_TDM_SCLK_WS(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
682 static struct clk_regmap g12a_tdmout_b_sclk =
683 AUD_TDM_SCLK_WS(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
684 static struct clk_regmap g12a_tdmout_c_sclk =
685 AUD_TDM_SCLK_WS(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
686
687 static struct clk_regmap toram =
688 AUD_PCLK_GATE(toram, AUDIO_CLK_GATE_EN, 20);
689 static struct clk_regmap spdifout_b =
690 AUD_PCLK_GATE(spdifout_b, AUDIO_CLK_GATE_EN, 21);
691 static struct clk_regmap eqdrc =
692 AUD_PCLK_GATE(eqdrc, AUDIO_CLK_GATE_EN, 22);
693
694 /* SM1 Clocks */
695 static struct clk_regmap sm1_clk81_en = {
696 .data = &(struct clk_regmap_gate_data){
697 .offset = AUDIO_CLK81_EN,
698 .bit_idx = 31,
699 },
700 .hw.init = &(struct clk_init_data) {
701 .name = "aud_clk81_en",
702 .ops = &clk_regmap_gate_ops,
703 .parent_data = &(const struct clk_parent_data) {
704 .fw_name = "pclk",
705 },
706 .num_parents = 1,
707 },
708 };
709
710 static struct clk_regmap sm1_sysclk_a_div = {
711 .data = &(struct clk_regmap_div_data){
712 .offset = AUDIO_CLK81_CTRL,
713 .shift = 0,
714 .width = 8,
715 },
716 .hw.init = &(struct clk_init_data) {
717 .name = "aud_sysclk_a_div",
718 .ops = &clk_regmap_divider_ops,
719 .parent_hws = (const struct clk_hw *[]) {
720 &sm1_clk81_en.hw,
721 },
722 .num_parents = 1,
723 .flags = CLK_SET_RATE_PARENT,
724 },
725 };
726
727 static struct clk_regmap sm1_sysclk_a_en = {
728 .data = &(struct clk_regmap_gate_data){
729 .offset = AUDIO_CLK81_CTRL,
730 .bit_idx = 8,
731 },
732 .hw.init = &(struct clk_init_data) {
733 .name = "aud_sysclk_a_en",
734 .ops = &clk_regmap_gate_ops,
735 .parent_hws = (const struct clk_hw *[]) {
736 &sm1_sysclk_a_div.hw,
737 },
738 .num_parents = 1,
739 .flags = CLK_SET_RATE_PARENT,
740 },
741 };
742
743 static struct clk_regmap sm1_sysclk_b_div = {
744 .data = &(struct clk_regmap_div_data){
745 .offset = AUDIO_CLK81_CTRL,
746 .shift = 16,
747 .width = 8,
748 },
749 .hw.init = &(struct clk_init_data) {
750 .name = "aud_sysclk_b_div",
751 .ops = &clk_regmap_divider_ops,
752 .parent_hws = (const struct clk_hw *[]) {
753 &sm1_clk81_en.hw,
754 },
755 .num_parents = 1,
756 .flags = CLK_SET_RATE_PARENT,
757 },
758 };
759
760 static struct clk_regmap sm1_sysclk_b_en = {
761 .data = &(struct clk_regmap_gate_data){
762 .offset = AUDIO_CLK81_CTRL,
763 .bit_idx = 24,
764 },
765 .hw.init = &(struct clk_init_data) {
766 .name = "aud_sysclk_b_en",
767 .ops = &clk_regmap_gate_ops,
768 .parent_hws = (const struct clk_hw *[]) {
769 &sm1_sysclk_b_div.hw,
770 },
771 .num_parents = 1,
772 .flags = CLK_SET_RATE_PARENT,
773 },
774 };
775
776 static const struct clk_hw *sm1_aud_top_parents[] = {
777 &sm1_sysclk_a_en.hw,
778 &sm1_sysclk_b_en.hw,
779 };
780
781 static struct clk_regmap sm1_aud_top = {
782 .data = &(struct clk_regmap_mux_data){
783 .offset = AUDIO_CLK81_CTRL,
784 .mask = 0x1,
785 .shift = 31,
786 },
787 .hw.init = &(struct clk_init_data){
788 .name = "aud_top",
789 .ops = &clk_regmap_mux_ops,
790 .parent_hws = sm1_aud_top_parents,
791 .num_parents = ARRAY_SIZE(sm1_aud_top_parents),
792 .flags = CLK_SET_RATE_NO_REPARENT,
793 },
794 };
795
796 static struct clk_regmap resample_b =
797 AUD_PCLK_GATE(resample_b, AUDIO_CLK_GATE_EN, 26);
798 static struct clk_regmap tovad =
799 AUD_PCLK_GATE(tovad, AUDIO_CLK_GATE_EN, 27);
800 static struct clk_regmap locker =
801 AUD_PCLK_GATE(locker, AUDIO_CLK_GATE_EN, 28);
802 static struct clk_regmap spdifin_lb =
803 AUD_PCLK_GATE(spdifin_lb, AUDIO_CLK_GATE_EN, 29);
804 static struct clk_regmap frddr_d =
805 AUD_PCLK_GATE(frddr_d, AUDIO_CLK_GATE_EN1, 0);
806 static struct clk_regmap toddr_d =
807 AUD_PCLK_GATE(toddr_d, AUDIO_CLK_GATE_EN1, 1);
808 static struct clk_regmap loopback_b =
809 AUD_PCLK_GATE(loopback_b, AUDIO_CLK_GATE_EN1, 2);
810 static struct clk_regmap earcrx =
811 AUD_PCLK_GATE(earcrx, AUDIO_CLK_GATE_EN1, 6);
812
813
814 static struct clk_regmap sm1_mst_a_mclk_sel =
815 AUD_MST_MCLK_MUX(mst_a_mclk, AUDIO_SM1_MCLK_A_CTRL);
816 static struct clk_regmap sm1_mst_b_mclk_sel =
817 AUD_MST_MCLK_MUX(mst_b_mclk, AUDIO_SM1_MCLK_B_CTRL);
818 static struct clk_regmap sm1_mst_c_mclk_sel =
819 AUD_MST_MCLK_MUX(mst_c_mclk, AUDIO_SM1_MCLK_C_CTRL);
820 static struct clk_regmap sm1_mst_d_mclk_sel =
821 AUD_MST_MCLK_MUX(mst_d_mclk, AUDIO_SM1_MCLK_D_CTRL);
822 static struct clk_regmap sm1_mst_e_mclk_sel =
823 AUD_MST_MCLK_MUX(mst_e_mclk, AUDIO_SM1_MCLK_E_CTRL);
824 static struct clk_regmap sm1_mst_f_mclk_sel =
825 AUD_MST_MCLK_MUX(mst_f_mclk, AUDIO_SM1_MCLK_F_CTRL);
826 static struct clk_regmap sm1_earcrx_cmdc_clk_sel =
827 AUD_MST_MCLK_MUX(earcrx_cmdc_clk, AUDIO_EARCRX_CMDC_CLK_CTRL);
828 static struct clk_regmap sm1_earcrx_dmac_clk_sel =
829 AUD_MST_MCLK_MUX(earcrx_dmac_clk, AUDIO_EARCRX_DMAC_CLK_CTRL);
830
831 static struct clk_regmap sm1_mst_a_mclk_div =
832 AUD_MST_MCLK_DIV(mst_a_mclk, AUDIO_SM1_MCLK_A_CTRL);
833 static struct clk_regmap sm1_mst_b_mclk_div =
834 AUD_MST_MCLK_DIV(mst_b_mclk, AUDIO_SM1_MCLK_B_CTRL);
835 static struct clk_regmap sm1_mst_c_mclk_div =
836 AUD_MST_MCLK_DIV(mst_c_mclk, AUDIO_SM1_MCLK_C_CTRL);
837 static struct clk_regmap sm1_mst_d_mclk_div =
838 AUD_MST_MCLK_DIV(mst_d_mclk, AUDIO_SM1_MCLK_D_CTRL);
839 static struct clk_regmap sm1_mst_e_mclk_div =
840 AUD_MST_MCLK_DIV(mst_e_mclk, AUDIO_SM1_MCLK_E_CTRL);
841 static struct clk_regmap sm1_mst_f_mclk_div =
842 AUD_MST_MCLK_DIV(mst_f_mclk, AUDIO_SM1_MCLK_F_CTRL);
843 static struct clk_regmap sm1_earcrx_cmdc_clk_div =
844 AUD_MST_MCLK_DIV(earcrx_cmdc_clk, AUDIO_EARCRX_CMDC_CLK_CTRL);
845 static struct clk_regmap sm1_earcrx_dmac_clk_div =
846 AUD_MST_MCLK_DIV(earcrx_dmac_clk, AUDIO_EARCRX_DMAC_CLK_CTRL);
847
848
849 static struct clk_regmap sm1_mst_a_mclk =
850 AUD_MST_MCLK_GATE(mst_a_mclk, AUDIO_SM1_MCLK_A_CTRL);
851 static struct clk_regmap sm1_mst_b_mclk =
852 AUD_MST_MCLK_GATE(mst_b_mclk, AUDIO_SM1_MCLK_B_CTRL);
853 static struct clk_regmap sm1_mst_c_mclk =
854 AUD_MST_MCLK_GATE(mst_c_mclk, AUDIO_SM1_MCLK_C_CTRL);
855 static struct clk_regmap sm1_mst_d_mclk =
856 AUD_MST_MCLK_GATE(mst_d_mclk, AUDIO_SM1_MCLK_D_CTRL);
857 static struct clk_regmap sm1_mst_e_mclk =
858 AUD_MST_MCLK_GATE(mst_e_mclk, AUDIO_SM1_MCLK_E_CTRL);
859 static struct clk_regmap sm1_mst_f_mclk =
860 AUD_MST_MCLK_GATE(mst_f_mclk, AUDIO_SM1_MCLK_F_CTRL);
861 static struct clk_regmap sm1_earcrx_cmdc_clk =
862 AUD_MST_MCLK_GATE(earcrx_cmdc_clk, AUDIO_EARCRX_CMDC_CLK_CTRL);
863 static struct clk_regmap sm1_earcrx_dmac_clk =
864 AUD_MST_MCLK_GATE(earcrx_dmac_clk, AUDIO_EARCRX_DMAC_CLK_CTRL);
865
866 static struct clk_regmap sm1_tdm_mclk_pad_0 = AUD_TDM_PAD_CTRL(
867 tdm_mclk_pad_0, AUDIO_SM1_MST_PAD_CTRL0, 0, mclk_pad_ctrl_parent_data);
868 static struct clk_regmap sm1_tdm_mclk_pad_1 = AUD_TDM_PAD_CTRL(
869 tdm_mclk_pad_1, AUDIO_SM1_MST_PAD_CTRL0, 4, mclk_pad_ctrl_parent_data);
870 static struct clk_regmap sm1_tdm_lrclk_pad_0 = AUD_TDM_PAD_CTRL(
871 tdm_lrclk_pad_0, AUDIO_SM1_MST_PAD_CTRL1, 16, lrclk_pad_ctrl_parent_data);
872 static struct clk_regmap sm1_tdm_lrclk_pad_1 = AUD_TDM_PAD_CTRL(
873 tdm_lrclk_pad_1, AUDIO_SM1_MST_PAD_CTRL1, 20, lrclk_pad_ctrl_parent_data);
874 static struct clk_regmap sm1_tdm_lrclk_pad_2 = AUD_TDM_PAD_CTRL(
875 tdm_lrclk_pad_2, AUDIO_SM1_MST_PAD_CTRL1, 24, lrclk_pad_ctrl_parent_data);
876 static struct clk_regmap sm1_tdm_sclk_pad_0 = AUD_TDM_PAD_CTRL(
877 tdm_sclk_pad_0, AUDIO_SM1_MST_PAD_CTRL1, 0, sclk_pad_ctrl_parent_data);
878 static struct clk_regmap sm1_tdm_sclk_pad_1 = AUD_TDM_PAD_CTRL(
879 tdm_sclk_pad_1, AUDIO_SM1_MST_PAD_CTRL1, 4, sclk_pad_ctrl_parent_data);
880 static struct clk_regmap sm1_tdm_sclk_pad_2 = AUD_TDM_PAD_CTRL(
881 tdm_sclk_pad_2, AUDIO_SM1_MST_PAD_CTRL1, 8, sclk_pad_ctrl_parent_data);
882
883 /*
884 * Array of all clocks provided by this provider
885 * The input clocks of the controller will be populated at runtime
886 */
887 static struct clk_hw *axg_audio_hw_clks[] = {
888 [AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
889 [AUD_CLKID_PDM] = &pdm.hw,
890 [AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
891 [AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
892 [AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
893 [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
894 [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
895 [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
896 [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
897 [AUD_CLKID_FRDDR_A] = &frddr_a.hw,
898 [AUD_CLKID_FRDDR_B] = &frddr_b.hw,
899 [AUD_CLKID_FRDDR_C] = &frddr_c.hw,
900 [AUD_CLKID_TODDR_A] = &toddr_a.hw,
901 [AUD_CLKID_TODDR_B] = &toddr_b.hw,
902 [AUD_CLKID_TODDR_C] = &toddr_c.hw,
903 [AUD_CLKID_LOOPBACK] = &loopback.hw,
904 [AUD_CLKID_SPDIFIN] = &spdifin.hw,
905 [AUD_CLKID_SPDIFOUT] = &spdifout.hw,
906 [AUD_CLKID_RESAMPLE] = &resample.hw,
907 [AUD_CLKID_POWER_DETECT] = &power_detect.hw,
908 [AUD_CLKID_MST_A_MCLK_SEL] = &mst_a_mclk_sel.hw,
909 [AUD_CLKID_MST_B_MCLK_SEL] = &mst_b_mclk_sel.hw,
910 [AUD_CLKID_MST_C_MCLK_SEL] = &mst_c_mclk_sel.hw,
911 [AUD_CLKID_MST_D_MCLK_SEL] = &mst_d_mclk_sel.hw,
912 [AUD_CLKID_MST_E_MCLK_SEL] = &mst_e_mclk_sel.hw,
913 [AUD_CLKID_MST_F_MCLK_SEL] = &mst_f_mclk_sel.hw,
914 [AUD_CLKID_MST_A_MCLK_DIV] = &mst_a_mclk_div.hw,
915 [AUD_CLKID_MST_B_MCLK_DIV] = &mst_b_mclk_div.hw,
916 [AUD_CLKID_MST_C_MCLK_DIV] = &mst_c_mclk_div.hw,
917 [AUD_CLKID_MST_D_MCLK_DIV] = &mst_d_mclk_div.hw,
918 [AUD_CLKID_MST_E_MCLK_DIV] = &mst_e_mclk_div.hw,
919 [AUD_CLKID_MST_F_MCLK_DIV] = &mst_f_mclk_div.hw,
920 [AUD_CLKID_MST_A_MCLK] = &mst_a_mclk.hw,
921 [AUD_CLKID_MST_B_MCLK] = &mst_b_mclk.hw,
922 [AUD_CLKID_MST_C_MCLK] = &mst_c_mclk.hw,
923 [AUD_CLKID_MST_D_MCLK] = &mst_d_mclk.hw,
924 [AUD_CLKID_MST_E_MCLK] = &mst_e_mclk.hw,
925 [AUD_CLKID_MST_F_MCLK] = &mst_f_mclk.hw,
926 [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
927 [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
928 [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
929 [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
930 [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
931 [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
932 [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
933 [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
934 [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
935 [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
936 [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
937 [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
938 [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
939 [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
940 [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
941 [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
942 [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
943 [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
944 [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
945 [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
946 [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
947 [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
948 [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
949 [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
950 [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
951 [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
952 [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
953 [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
954 [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
955 [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
956 [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
957 [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
958 [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
959 [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
960 [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
961 [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
962 [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
963 [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
964 [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
965 [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
966 [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
967 [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
968 [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
969 [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
970 [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
971 [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
972 [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
973 [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
974 [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
975 [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
976 [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
977 [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
978 [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
979 [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
980 [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
981 [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
982 [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
983 [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
984 [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
985 [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
986 [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
987 [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
988 [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
989 [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
990 [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
991 [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
992 [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
993 [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
994 [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
995 [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
996 [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
997 [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
998 [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
999 [AUD_CLKID_TDMOUT_A_SCLK] = &axg_tdmout_a_sclk.hw,
1000 [AUD_CLKID_TDMOUT_B_SCLK] = &axg_tdmout_b_sclk.hw,
1001 [AUD_CLKID_TDMOUT_C_SCLK] = &axg_tdmout_c_sclk.hw,
1002 [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
1003 [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
1004 [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
1005 [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
1006 [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
1007 [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
1008 [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
1009 [AUD_CLKID_TOP] = &axg_aud_top,
1010 };
1011
1012 /*
1013 * Array of all G12A clocks provided by this provider
1014 * The input clocks of the controller will be populated at runtime
1015 */
1016 static struct clk_hw *g12a_audio_hw_clks[] = {
1017 [AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
1018 [AUD_CLKID_PDM] = &pdm.hw,
1019 [AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
1020 [AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
1021 [AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
1022 [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
1023 [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
1024 [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
1025 [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
1026 [AUD_CLKID_FRDDR_A] = &frddr_a.hw,
1027 [AUD_CLKID_FRDDR_B] = &frddr_b.hw,
1028 [AUD_CLKID_FRDDR_C] = &frddr_c.hw,
1029 [AUD_CLKID_TODDR_A] = &toddr_a.hw,
1030 [AUD_CLKID_TODDR_B] = &toddr_b.hw,
1031 [AUD_CLKID_TODDR_C] = &toddr_c.hw,
1032 [AUD_CLKID_LOOPBACK] = &loopback.hw,
1033 [AUD_CLKID_SPDIFIN] = &spdifin.hw,
1034 [AUD_CLKID_SPDIFOUT] = &spdifout.hw,
1035 [AUD_CLKID_RESAMPLE] = &resample.hw,
1036 [AUD_CLKID_POWER_DETECT] = &power_detect.hw,
1037 [AUD_CLKID_SPDIFOUT_B] = &spdifout_b.hw,
1038 [AUD_CLKID_MST_A_MCLK_SEL] = &mst_a_mclk_sel.hw,
1039 [AUD_CLKID_MST_B_MCLK_SEL] = &mst_b_mclk_sel.hw,
1040 [AUD_CLKID_MST_C_MCLK_SEL] = &mst_c_mclk_sel.hw,
1041 [AUD_CLKID_MST_D_MCLK_SEL] = &mst_d_mclk_sel.hw,
1042 [AUD_CLKID_MST_E_MCLK_SEL] = &mst_e_mclk_sel.hw,
1043 [AUD_CLKID_MST_F_MCLK_SEL] = &mst_f_mclk_sel.hw,
1044 [AUD_CLKID_MST_A_MCLK_DIV] = &mst_a_mclk_div.hw,
1045 [AUD_CLKID_MST_B_MCLK_DIV] = &mst_b_mclk_div.hw,
1046 [AUD_CLKID_MST_C_MCLK_DIV] = &mst_c_mclk_div.hw,
1047 [AUD_CLKID_MST_D_MCLK_DIV] = &mst_d_mclk_div.hw,
1048 [AUD_CLKID_MST_E_MCLK_DIV] = &mst_e_mclk_div.hw,
1049 [AUD_CLKID_MST_F_MCLK_DIV] = &mst_f_mclk_div.hw,
1050 [AUD_CLKID_MST_A_MCLK] = &mst_a_mclk.hw,
1051 [AUD_CLKID_MST_B_MCLK] = &mst_b_mclk.hw,
1052 [AUD_CLKID_MST_C_MCLK] = &mst_c_mclk.hw,
1053 [AUD_CLKID_MST_D_MCLK] = &mst_d_mclk.hw,
1054 [AUD_CLKID_MST_E_MCLK] = &mst_e_mclk.hw,
1055 [AUD_CLKID_MST_F_MCLK] = &mst_f_mclk.hw,
1056 [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
1057 [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
1058 [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
1059 [AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &spdifout_b_clk_sel.hw,
1060 [AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &spdifout_b_clk_div.hw,
1061 [AUD_CLKID_SPDIFOUT_B_CLK] = &spdifout_b_clk.hw,
1062 [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
1063 [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
1064 [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
1065 [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
1066 [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
1067 [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
1068 [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
1069 [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
1070 [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
1071 [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
1072 [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
1073 [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
1074 [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
1075 [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
1076 [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
1077 [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
1078 [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
1079 [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
1080 [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
1081 [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
1082 [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
1083 [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
1084 [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
1085 [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
1086 [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
1087 [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
1088 [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
1089 [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
1090 [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
1091 [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
1092 [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
1093 [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
1094 [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
1095 [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
1096 [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
1097 [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
1098 [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
1099 [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
1100 [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
1101 [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
1102 [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
1103 [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
1104 [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
1105 [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
1106 [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
1107 [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
1108 [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
1109 [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
1110 [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
1111 [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
1112 [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
1113 [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
1114 [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
1115 [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
1116 [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
1117 [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
1118 [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
1119 [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
1120 [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
1121 [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
1122 [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
1123 [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
1124 [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
1125 [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
1126 [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
1127 [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
1128 [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
1129 [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
1130 [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
1131 [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
1132 [AUD_CLKID_TDMOUT_A_SCLK] = &g12a_tdmout_a_sclk.hw,
1133 [AUD_CLKID_TDMOUT_B_SCLK] = &g12a_tdmout_b_sclk.hw,
1134 [AUD_CLKID_TDMOUT_C_SCLK] = &g12a_tdmout_c_sclk.hw,
1135 [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
1136 [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
1137 [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
1138 [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
1139 [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
1140 [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
1141 [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
1142 [AUD_CLKID_TDM_MCLK_PAD0] = &g12a_tdm_mclk_pad_0.hw,
1143 [AUD_CLKID_TDM_MCLK_PAD1] = &g12a_tdm_mclk_pad_1.hw,
1144 [AUD_CLKID_TDM_LRCLK_PAD0] = &g12a_tdm_lrclk_pad_0.hw,
1145 [AUD_CLKID_TDM_LRCLK_PAD1] = &g12a_tdm_lrclk_pad_1.hw,
1146 [AUD_CLKID_TDM_LRCLK_PAD2] = &g12a_tdm_lrclk_pad_2.hw,
1147 [AUD_CLKID_TDM_SCLK_PAD0] = &g12a_tdm_sclk_pad_0.hw,
1148 [AUD_CLKID_TDM_SCLK_PAD1] = &g12a_tdm_sclk_pad_1.hw,
1149 [AUD_CLKID_TDM_SCLK_PAD2] = &g12a_tdm_sclk_pad_2.hw,
1150 [AUD_CLKID_TOP] = &axg_aud_top,
1151 };
1152
1153 /*
1154 * Array of all SM1 clocks provided by this provider
1155 * The input clocks of the controller will be populated at runtime
1156 */
1157 static struct clk_hw *sm1_audio_hw_clks[] = {
1158 [AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
1159 [AUD_CLKID_PDM] = &pdm.hw,
1160 [AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
1161 [AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
1162 [AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
1163 [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
1164 [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
1165 [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
1166 [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
1167 [AUD_CLKID_FRDDR_A] = &frddr_a.hw,
1168 [AUD_CLKID_FRDDR_B] = &frddr_b.hw,
1169 [AUD_CLKID_FRDDR_C] = &frddr_c.hw,
1170 [AUD_CLKID_TODDR_A] = &toddr_a.hw,
1171 [AUD_CLKID_TODDR_B] = &toddr_b.hw,
1172 [AUD_CLKID_TODDR_C] = &toddr_c.hw,
1173 [AUD_CLKID_LOOPBACK] = &loopback.hw,
1174 [AUD_CLKID_SPDIFIN] = &spdifin.hw,
1175 [AUD_CLKID_SPDIFOUT] = &spdifout.hw,
1176 [AUD_CLKID_RESAMPLE] = &resample.hw,
1177 [AUD_CLKID_SPDIFOUT_B] = &spdifout_b.hw,
1178 [AUD_CLKID_MST_A_MCLK_SEL] = &sm1_mst_a_mclk_sel.hw,
1179 [AUD_CLKID_MST_B_MCLK_SEL] = &sm1_mst_b_mclk_sel.hw,
1180 [AUD_CLKID_MST_C_MCLK_SEL] = &sm1_mst_c_mclk_sel.hw,
1181 [AUD_CLKID_MST_D_MCLK_SEL] = &sm1_mst_d_mclk_sel.hw,
1182 [AUD_CLKID_MST_E_MCLK_SEL] = &sm1_mst_e_mclk_sel.hw,
1183 [AUD_CLKID_MST_F_MCLK_SEL] = &sm1_mst_f_mclk_sel.hw,
1184 [AUD_CLKID_MST_A_MCLK_DIV] = &sm1_mst_a_mclk_div.hw,
1185 [AUD_CLKID_MST_B_MCLK_DIV] = &sm1_mst_b_mclk_div.hw,
1186 [AUD_CLKID_MST_C_MCLK_DIV] = &sm1_mst_c_mclk_div.hw,
1187 [AUD_CLKID_MST_D_MCLK_DIV] = &sm1_mst_d_mclk_div.hw,
1188 [AUD_CLKID_MST_E_MCLK_DIV] = &sm1_mst_e_mclk_div.hw,
1189 [AUD_CLKID_MST_F_MCLK_DIV] = &sm1_mst_f_mclk_div.hw,
1190 [AUD_CLKID_MST_A_MCLK] = &sm1_mst_a_mclk.hw,
1191 [AUD_CLKID_MST_B_MCLK] = &sm1_mst_b_mclk.hw,
1192 [AUD_CLKID_MST_C_MCLK] = &sm1_mst_c_mclk.hw,
1193 [AUD_CLKID_MST_D_MCLK] = &sm1_mst_d_mclk.hw,
1194 [AUD_CLKID_MST_E_MCLK] = &sm1_mst_e_mclk.hw,
1195 [AUD_CLKID_MST_F_MCLK] = &sm1_mst_f_mclk.hw,
1196 [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
1197 [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
1198 [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
1199 [AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &spdifout_b_clk_sel.hw,
1200 [AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &spdifout_b_clk_div.hw,
1201 [AUD_CLKID_SPDIFOUT_B_CLK] = &spdifout_b_clk.hw,
1202 [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
1203 [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
1204 [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
1205 [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
1206 [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
1207 [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
1208 [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
1209 [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
1210 [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
1211 [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
1212 [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
1213 [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
1214 [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
1215 [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
1216 [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
1217 [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
1218 [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
1219 [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
1220 [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
1221 [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
1222 [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
1223 [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
1224 [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
1225 [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
1226 [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
1227 [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
1228 [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
1229 [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
1230 [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
1231 [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
1232 [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
1233 [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
1234 [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
1235 [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
1236 [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
1237 [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
1238 [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
1239 [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
1240 [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
1241 [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
1242 [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
1243 [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
1244 [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
1245 [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
1246 [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
1247 [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
1248 [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
1249 [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
1250 [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
1251 [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
1252 [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
1253 [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
1254 [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
1255 [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
1256 [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
1257 [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
1258 [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
1259 [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
1260 [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
1261 [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
1262 [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
1263 [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
1264 [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
1265 [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
1266 [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
1267 [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
1268 [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
1269 [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
1270 [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
1271 [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
1272 [AUD_CLKID_TDMOUT_A_SCLK] = &g12a_tdmout_a_sclk.hw,
1273 [AUD_CLKID_TDMOUT_B_SCLK] = &g12a_tdmout_b_sclk.hw,
1274 [AUD_CLKID_TDMOUT_C_SCLK] = &g12a_tdmout_c_sclk.hw,
1275 [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
1276 [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
1277 [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
1278 [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
1279 [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
1280 [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
1281 [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
1282 [AUD_CLKID_TDM_MCLK_PAD0] = &sm1_tdm_mclk_pad_0.hw,
1283 [AUD_CLKID_TDM_MCLK_PAD1] = &sm1_tdm_mclk_pad_1.hw,
1284 [AUD_CLKID_TDM_LRCLK_PAD0] = &sm1_tdm_lrclk_pad_0.hw,
1285 [AUD_CLKID_TDM_LRCLK_PAD1] = &sm1_tdm_lrclk_pad_1.hw,
1286 [AUD_CLKID_TDM_LRCLK_PAD2] = &sm1_tdm_lrclk_pad_2.hw,
1287 [AUD_CLKID_TDM_SCLK_PAD0] = &sm1_tdm_sclk_pad_0.hw,
1288 [AUD_CLKID_TDM_SCLK_PAD1] = &sm1_tdm_sclk_pad_1.hw,
1289 [AUD_CLKID_TDM_SCLK_PAD2] = &sm1_tdm_sclk_pad_2.hw,
1290 [AUD_CLKID_TOP] = &sm1_aud_top.hw,
1291 [AUD_CLKID_TORAM] = &toram.hw,
1292 [AUD_CLKID_EQDRC] = &eqdrc.hw,
1293 [AUD_CLKID_RESAMPLE_B] = &resample_b.hw,
1294 [AUD_CLKID_TOVAD] = &tovad.hw,
1295 [AUD_CLKID_LOCKER] = &locker.hw,
1296 [AUD_CLKID_SPDIFIN_LB] = &spdifin_lb.hw,
1297 [AUD_CLKID_FRDDR_D] = &frddr_d.hw,
1298 [AUD_CLKID_TODDR_D] = &toddr_d.hw,
1299 [AUD_CLKID_LOOPBACK_B] = &loopback_b.hw,
1300 [AUD_CLKID_CLK81_EN] = &sm1_clk81_en.hw,
1301 [AUD_CLKID_SYSCLK_A_DIV] = &sm1_sysclk_a_div.hw,
1302 [AUD_CLKID_SYSCLK_A_EN] = &sm1_sysclk_a_en.hw,
1303 [AUD_CLKID_SYSCLK_B_DIV] = &sm1_sysclk_b_div.hw,
1304 [AUD_CLKID_SYSCLK_B_EN] = &sm1_sysclk_b_en.hw,
1305 [AUD_CLKID_EARCRX] = &earcrx.hw,
1306 [AUD_CLKID_EARCRX_CMDC_SEL] = &sm1_earcrx_cmdc_clk_sel.hw,
1307 [AUD_CLKID_EARCRX_CMDC_DIV] = &sm1_earcrx_cmdc_clk_div.hw,
1308 [AUD_CLKID_EARCRX_CMDC] = &sm1_earcrx_cmdc_clk.hw,
1309 [AUD_CLKID_EARCRX_DMAC_SEL] = &sm1_earcrx_dmac_clk_sel.hw,
1310 [AUD_CLKID_EARCRX_DMAC_DIV] = &sm1_earcrx_dmac_clk_div.hw,
1311 [AUD_CLKID_EARCRX_DMAC] = &sm1_earcrx_dmac_clk.hw,
1312 };
1313
1314 static struct regmap_config axg_audio_regmap_cfg = {
1315 .reg_bits = 32,
1316 .val_bits = 32,
1317 .reg_stride = 4,
1318 };
1319
1320 struct audioclk_data {
1321 struct meson_clk_hw_data hw_clks;
1322 const char *rst_drvname;
1323 unsigned int max_register;
1324 };
1325
axg_audio_clkc_probe(struct platform_device * pdev)1326 static int axg_audio_clkc_probe(struct platform_device *pdev)
1327 {
1328 struct device *dev = &pdev->dev;
1329 const struct audioclk_data *data;
1330 struct auxiliary_device *auxdev;
1331 struct regmap *map;
1332 void __iomem *regs;
1333 struct clk_hw *hw;
1334 struct clk *clk;
1335 int ret, i;
1336
1337 data = of_device_get_match_data(dev);
1338 if (!data)
1339 return -EINVAL;
1340
1341 regs = devm_platform_ioremap_resource(pdev, 0);
1342 if (IS_ERR(regs))
1343 return PTR_ERR(regs);
1344
1345 axg_audio_regmap_cfg.max_register = data->max_register;
1346 map = devm_regmap_init_mmio(dev, regs, &axg_audio_regmap_cfg);
1347 if (IS_ERR(map)) {
1348 dev_err(dev, "failed to init regmap: %ld\n", PTR_ERR(map));
1349 return PTR_ERR(map);
1350 }
1351
1352 /* Get the mandatory peripheral clock */
1353 clk = devm_clk_get_enabled(dev, "pclk");
1354 if (IS_ERR(clk))
1355 return PTR_ERR(clk);
1356
1357 ret = device_reset(dev);
1358 if (ret) {
1359 dev_err_probe(dev, ret, "failed to reset device\n");
1360 return ret;
1361 }
1362
1363 /* Take care to skip the registered input clocks */
1364 for (i = AUD_CLKID_DDR_ARB; i < data->hw_clks.num; i++) {
1365 const char *name;
1366
1367 hw = data->hw_clks.hws[i];
1368 /* array might be sparse */
1369 if (!hw)
1370 continue;
1371
1372 name = hw->init->name;
1373
1374 ret = devm_clk_hw_register(dev, hw);
1375 if (ret) {
1376 dev_err(dev, "failed to register clock %s\n", name);
1377 return ret;
1378 }
1379 }
1380
1381 ret = devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->hw_clks);
1382 if (ret)
1383 return ret;
1384
1385 /* Register auxiliary reset driver when applicable */
1386 if (data->rst_drvname) {
1387 auxdev = __devm_auxiliary_device_create(dev, dev->driver->name,
1388 data->rst_drvname, NULL, 0);
1389 if (!auxdev)
1390 return -ENODEV;
1391 }
1392
1393 return 0;
1394 }
1395
1396 static const struct audioclk_data axg_audioclk_data = {
1397 .hw_clks = {
1398 .hws = axg_audio_hw_clks,
1399 .num = ARRAY_SIZE(axg_audio_hw_clks),
1400 },
1401 .max_register = AUDIO_CLK_PDMIN_CTRL1,
1402 };
1403
1404 static const struct audioclk_data g12a_audioclk_data = {
1405 .hw_clks = {
1406 .hws = g12a_audio_hw_clks,
1407 .num = ARRAY_SIZE(g12a_audio_hw_clks),
1408 },
1409 .rst_drvname = "rst-g12a",
1410 .max_register = AUDIO_CLK_SPDIFOUT_B_CTRL,
1411 };
1412
1413 static const struct audioclk_data sm1_audioclk_data = {
1414 .hw_clks = {
1415 .hws = sm1_audio_hw_clks,
1416 .num = ARRAY_SIZE(sm1_audio_hw_clks),
1417 },
1418 .rst_drvname = "rst-sm1",
1419 .max_register = AUDIO_EARCRX_DMAC_CLK_CTRL,
1420 };
1421
1422 static const struct of_device_id clkc_match_table[] = {
1423 {
1424 .compatible = "amlogic,axg-audio-clkc",
1425 .data = &axg_audioclk_data
1426 }, {
1427 .compatible = "amlogic,g12a-audio-clkc",
1428 .data = &g12a_audioclk_data
1429 }, {
1430 .compatible = "amlogic,sm1-audio-clkc",
1431 .data = &sm1_audioclk_data
1432 }, {}
1433 };
1434 MODULE_DEVICE_TABLE(of, clkc_match_table);
1435
1436 static struct platform_driver axg_audio_driver = {
1437 .probe = axg_audio_clkc_probe,
1438 .driver = {
1439 .name = "axg-audio-clkc",
1440 .of_match_table = clkc_match_table,
1441 },
1442 };
1443 module_platform_driver(axg_audio_driver);
1444
1445 MODULE_DESCRIPTION("Amlogic AXG/G12A/SM1 Audio Clock driver");
1446 MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
1447 MODULE_LICENSE("GPL");
1448 MODULE_IMPORT_NS("CLK_MESON");
1449