1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH12K_REG_H 8 #define ATH12K_REG_H 9 10 #include <linux/kernel.h> 11 #include <net/regulatory.h> 12 13 struct ath12k_base; 14 struct ath12k; 15 16 #define ATH12K_REG_UPDATE_TIMEOUT_HZ (3 * HZ) 17 18 #define ATH12K_2GHZ_MAX_FREQUENCY 2495 19 #define ATH12K_5GHZ_MAX_FREQUENCY 5920 20 21 /* DFS regdomains supported by Firmware */ 22 enum ath12k_dfs_region { 23 ATH12K_DFS_REG_UNSET, 24 ATH12K_DFS_REG_FCC, 25 ATH12K_DFS_REG_ETSI, 26 ATH12K_DFS_REG_MKK, 27 ATH12K_DFS_REG_CN, 28 ATH12K_DFS_REG_KR, 29 ATH12K_DFS_REG_MKK_N, 30 ATH12K_DFS_REG_UNDEF, 31 }; 32 33 enum ath12k_reg_cc_code { 34 REG_SET_CC_STATUS_PASS = 0, 35 REG_CURRENT_ALPHA2_NOT_FOUND = 1, 36 REG_INIT_ALPHA2_NOT_FOUND = 2, 37 REG_SET_CC_CHANGE_NOT_ALLOWED = 3, 38 REG_SET_CC_STATUS_NO_MEMORY = 4, 39 REG_SET_CC_STATUS_FAIL = 5, 40 }; 41 42 struct ath12k_reg_rule { 43 u16 start_freq; 44 u16 end_freq; 45 u16 max_bw; 46 u8 reg_power; 47 u8 ant_gain; 48 u16 flags; 49 bool psd_flag; 50 u16 psd_eirp; 51 }; 52 53 struct ath12k_reg_info { 54 enum ath12k_reg_cc_code status_code; 55 u8 num_phy; 56 u8 phy_id; 57 u16 reg_dmn_pair; 58 u16 ctry_code; 59 u8 alpha2[REG_ALPHA2_LEN + 1]; 60 u32 dfs_region; 61 u32 phybitmap; 62 bool is_ext_reg_event; 63 u32 min_bw_2g; 64 u32 max_bw_2g; 65 u32 min_bw_5g; 66 u32 max_bw_5g; 67 u32 num_2g_reg_rules; 68 u32 num_5g_reg_rules; 69 struct ath12k_reg_rule *reg_rules_2g_ptr; 70 struct ath12k_reg_rule *reg_rules_5g_ptr; 71 enum wmi_reg_6g_client_type client_type; 72 bool rnr_tpe_usable; 73 bool unspecified_ap_usable; 74 /* TODO: All 6G related info can be stored only for required 75 * combination instead of all types, to optimize memory usage. 76 */ 77 u8 domain_code_6g_ap[WMI_REG_CURRENT_MAX_AP_TYPE]; 78 u8 domain_code_6g_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; 79 u32 domain_code_6g_super_id; 80 u32 min_bw_6g_ap[WMI_REG_CURRENT_MAX_AP_TYPE]; 81 u32 max_bw_6g_ap[WMI_REG_CURRENT_MAX_AP_TYPE]; 82 u32 min_bw_6g_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; 83 u32 max_bw_6g_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; 84 u32 num_6g_reg_rules_ap[WMI_REG_CURRENT_MAX_AP_TYPE]; 85 u32 num_6g_reg_rules_cl[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; 86 struct ath12k_reg_rule *reg_rules_6g_ap_ptr[WMI_REG_CURRENT_MAX_AP_TYPE]; 87 struct ath12k_reg_rule *reg_rules_6g_client_ptr 88 [WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; 89 }; 90 91 /* Phy bitmaps */ 92 enum ath12k_reg_phy_bitmap { 93 ATH12K_REG_PHY_BITMAP_NO11AX = BIT(5), 94 ATH12K_REG_PHY_BITMAP_NO11BE = BIT(6), 95 }; 96 97 enum ath12k_reg_status { 98 ATH12K_REG_STATUS_VALID, 99 ATH12K_REG_STATUS_DROP, 100 ATH12K_REG_STATUS_FALLBACK, 101 }; 102 103 void ath12k_reg_init(struct ieee80211_hw *hw); 104 void ath12k_reg_free(struct ath12k_base *ab); 105 void ath12k_regd_update_work(struct work_struct *work); 106 struct ieee80211_regdomain *ath12k_reg_build_regd(struct ath12k_base *ab, 107 struct ath12k_reg_info *reg_info, 108 enum wmi_vdev_type vdev_type, 109 enum ieee80211_ap_reg_power power_type); 110 int ath12k_regd_update(struct ath12k *ar, bool init); 111 int ath12k_reg_update_chan_list(struct ath12k *ar, bool wait); 112 113 void ath12k_reg_reset_reg_info(struct ath12k_reg_info *reg_info); 114 int ath12k_reg_handle_chan_list(struct ath12k_base *ab, 115 struct ath12k_reg_info *reg_info, 116 enum wmi_vdev_type vdev_type, 117 enum ieee80211_ap_reg_power power_type); 118 void ath12k_regd_update_chan_list_work(struct work_struct *work); 119 enum wmi_reg_6g_ap_type 120 ath12k_reg_ap_pwr_convert(enum ieee80211_ap_reg_power power_type); 121 enum ath12k_reg_status ath12k_reg_validate_reg_info(struct ath12k_base *ab, 122 struct ath12k_reg_info *reg_info); 123 #endif 124