1 /*
2 * ASPEED SoC family
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 *
6 * Copyright 2016 IBM Corp.
7 *
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
10 */
11
12 #ifndef ASPEED_SOC_H
13 #define ASPEED_SOC_H
14
15 #include "hw/cpu/a15mpcore.h"
16 #include "hw/arm/armv7m.h"
17 #include "hw/intc/aspeed_vic.h"
18 #include "hw/intc/aspeed_intc.h"
19 #include "hw/misc/aspeed_scu.h"
20 #include "hw/adc/aspeed_adc.h"
21 #include "hw/misc/aspeed_sdmc.h"
22 #include "hw/misc/aspeed_xdma.h"
23 #include "hw/timer/aspeed_timer.h"
24 #include "hw/rtc/aspeed_rtc.h"
25 #include "hw/i2c/aspeed_i2c.h"
26 #include "hw/misc/aspeed_i3c.h"
27 #include "hw/ssi/aspeed_smc.h"
28 #include "hw/misc/aspeed_hace.h"
29 #include "hw/misc/aspeed_sbc.h"
30 #include "hw/misc/aspeed_sli.h"
31 #include "hw/watchdog/wdt_aspeed.h"
32 #include "hw/net/ftgmac100.h"
33 #include "target/arm/cpu.h"
34 #include "hw/gpio/aspeed_gpio.h"
35 #include "hw/sd/aspeed_sdhci.h"
36 #include "hw/usb/hcd-ehci.h"
37 #include "qom/object.h"
38 #include "hw/misc/aspeed_lpc.h"
39 #include "hw/misc/unimp.h"
40 #include "hw/misc/aspeed_peci.h"
41 #include "hw/fsi/aspeed_apb2opb.h"
42 #include "hw/char/serial-mm.h"
43 #include "hw/intc/arm_gicv3.h"
44
45 #define ASPEED_SPIS_NUM 3
46 #define ASPEED_EHCIS_NUM 4
47 #define ASPEED_WDTS_NUM 8
48 #define ASPEED_CPUS_NUM 4
49 #define ASPEED_MACS_NUM 4
50 #define ASPEED_UARTS_NUM 13
51 #define ASPEED_JTAG_NUM 2
52
53 struct AspeedSoCState {
54 DeviceState parent;
55
56 MemoryRegion *memory;
57 MemoryRegion *dram_mr;
58 MemoryRegion dram_container;
59 MemoryRegion sram;
60 MemoryRegion spi_boot_container;
61 MemoryRegion spi_boot;
62 MemoryRegion vbootrom;
63 AddressSpace dram_as;
64 AspeedRtcState rtc;
65 AspeedTimerCtrlState timerctrl;
66 AspeedI2CState i2c;
67 AspeedI3CState i3c;
68 AspeedSCUState scu;
69 AspeedSCUState scuio;
70 AspeedHACEState hace;
71 AspeedXDMAState xdma;
72 AspeedADCState adc;
73 AspeedSMCState fmc;
74 AspeedSMCState spi[ASPEED_SPIS_NUM];
75 EHCISysBusState ehci[ASPEED_EHCIS_NUM];
76 AspeedSBCState sbc;
77 AspeedSLIState sli;
78 AspeedSLIState sliio;
79 MemoryRegion secsram;
80 UnimplementedDeviceState sbc_unimplemented;
81 AspeedSDMCState sdmc;
82 AspeedWDTState wdt[ASPEED_WDTS_NUM];
83 FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
84 AspeedMiiState mii[ASPEED_MACS_NUM];
85 AspeedGPIOState gpio;
86 AspeedGPIOState gpio_1_8v;
87 AspeedSDHCIState sdhci;
88 AspeedSDHCIState emmc;
89 AspeedLPCState lpc;
90 AspeedPECIState peci;
91 SerialMM uart[ASPEED_UARTS_NUM];
92 Clock *sysclk;
93 UnimplementedDeviceState iomem;
94 UnimplementedDeviceState iomem0;
95 UnimplementedDeviceState iomem1;
96 UnimplementedDeviceState video;
97 UnimplementedDeviceState emmc_boot_controller;
98 UnimplementedDeviceState dpmcu;
99 UnimplementedDeviceState pwm;
100 UnimplementedDeviceState espi;
101 UnimplementedDeviceState udc;
102 UnimplementedDeviceState sgpiom;
103 UnimplementedDeviceState ltpi;
104 UnimplementedDeviceState jtag[ASPEED_JTAG_NUM];
105 AspeedAPB2OPBState fsi[2];
106 };
107
108 #define TYPE_ASPEED_SOC "aspeed-soc"
109 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
110
111 struct Aspeed2400SoCState {
112 AspeedSoCState parent;
113
114 ARMCPU cpu[ASPEED_CPUS_NUM];
115 AspeedVICState vic;
116 };
117
118 #define TYPE_ASPEED2400_SOC "aspeed2400-soc"
119 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC)
120
121 struct Aspeed2600SoCState {
122 AspeedSoCState parent;
123
124 A15MPPrivState a7mpcore;
125 ARMCPU cpu[ASPEED_CPUS_NUM]; /* XXX belong to a7mpcore */
126 };
127
128 #define TYPE_ASPEED2600_SOC "aspeed2600-soc"
129 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC)
130
131 struct Aspeed27x0SoCState {
132 AspeedSoCState parent;
133
134 ARMCPU cpu[ASPEED_CPUS_NUM];
135 AspeedINTCState intc[2];
136 GICv3State gic;
137 MemoryRegion dram_empty;
138 };
139
140 #define TYPE_ASPEED27X0_SOC "aspeed27x0-soc"
141 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SoCState, ASPEED27X0_SOC)
142
143 struct Aspeed10x0SoCState {
144 AspeedSoCState parent;
145
146 ARMv7MState armv7m;
147 };
148
149 struct Aspeed27x0SSPSoCState {
150 AspeedSoCState parent;
151 AspeedINTCState intc[2];
152 UnimplementedDeviceState ipc[2];
153 UnimplementedDeviceState scuio;
154
155 ARMv7MState armv7m;
156 };
157
158 #define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc"
159 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SSPSoCState, ASPEED27X0SSP_SOC)
160
161 struct Aspeed27x0TSPSoCState {
162 AspeedSoCState parent;
163 AspeedINTCState intc[2];
164 UnimplementedDeviceState ipc[2];
165 UnimplementedDeviceState scuio;
166
167 ARMv7MState armv7m;
168 };
169
170 #define TYPE_ASPEED27X0TSP_SOC "aspeed27x0tsp-soc"
171 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0TSPSoCState, ASPEED27X0TSP_SOC)
172
173 #define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
174 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC)
175
176 struct AspeedSoCClass {
177 DeviceClass parent_class;
178
179 /** valid_cpu_types: NULL terminated array of a single CPU type. */
180 const char * const *valid_cpu_types;
181 uint32_t silicon_rev;
182 uint64_t sram_size;
183 uint64_t secsram_size;
184 int spis_num;
185 int ehcis_num;
186 int wdts_num;
187 int macs_num;
188 int uarts_num;
189 int uarts_base;
190 const int *irqmap;
191 const hwaddr *memmap;
192 uint32_t num_cpus;
193 qemu_irq (*get_irq)(AspeedSoCState *s, int dev);
194 bool (*boot_from_emmc)(AspeedSoCState *s);
195 };
196
197 const char *aspeed_soc_cpu_type(AspeedSoCClass *sc);
198
199 enum {
200 ASPEED_DEV_VBOOTROM,
201 ASPEED_DEV_SPI_BOOT,
202 ASPEED_DEV_IOMEM,
203 ASPEED_DEV_IOMEM0,
204 ASPEED_DEV_IOMEM1,
205 ASPEED_DEV_LTPI,
206 ASPEED_DEV_UART0,
207 ASPEED_DEV_UART1,
208 ASPEED_DEV_UART2,
209 ASPEED_DEV_UART3,
210 ASPEED_DEV_UART4,
211 ASPEED_DEV_UART5,
212 ASPEED_DEV_UART6,
213 ASPEED_DEV_UART7,
214 ASPEED_DEV_UART8,
215 ASPEED_DEV_UART9,
216 ASPEED_DEV_UART10,
217 ASPEED_DEV_UART11,
218 ASPEED_DEV_UART12,
219 ASPEED_DEV_UART13,
220 ASPEED_DEV_VUART,
221 ASPEED_DEV_FMC,
222 ASPEED_DEV_SPI0,
223 ASPEED_DEV_SPI1,
224 ASPEED_DEV_SPI2,
225 ASPEED_DEV_EHCI1,
226 ASPEED_DEV_EHCI2,
227 ASPEED_DEV_EHCI3,
228 ASPEED_DEV_EHCI4,
229 ASPEED_DEV_VIC,
230 ASPEED_DEV_INTC,
231 ASPEED_DEV_INTCIO,
232 ASPEED_DEV_SDMC,
233 ASPEED_DEV_SCU,
234 ASPEED_DEV_ADC,
235 ASPEED_DEV_SBC,
236 ASPEED_DEV_SECSRAM,
237 ASPEED_DEV_EMMC_BC,
238 ASPEED_DEV_VIDEO,
239 ASPEED_DEV_SRAM,
240 ASPEED_DEV_SDHCI,
241 ASPEED_DEV_GPIO,
242 ASPEED_DEV_GPIO_1_8V,
243 ASPEED_DEV_RTC,
244 ASPEED_DEV_TIMER1,
245 ASPEED_DEV_TIMER2,
246 ASPEED_DEV_TIMER3,
247 ASPEED_DEV_TIMER4,
248 ASPEED_DEV_TIMER5,
249 ASPEED_DEV_TIMER6,
250 ASPEED_DEV_TIMER7,
251 ASPEED_DEV_TIMER8,
252 ASPEED_DEV_WDT,
253 ASPEED_DEV_PWM,
254 ASPEED_DEV_LPC,
255 ASPEED_DEV_IBT,
256 ASPEED_DEV_I2C,
257 ASPEED_DEV_PECI,
258 ASPEED_DEV_ETH1,
259 ASPEED_DEV_ETH2,
260 ASPEED_DEV_ETH3,
261 ASPEED_DEV_ETH4,
262 ASPEED_DEV_MII1,
263 ASPEED_DEV_MII2,
264 ASPEED_DEV_MII3,
265 ASPEED_DEV_MII4,
266 ASPEED_DEV_SDRAM,
267 ASPEED_DEV_XDMA,
268 ASPEED_DEV_EMMC,
269 ASPEED_DEV_KCS,
270 ASPEED_DEV_HACE,
271 ASPEED_DEV_DPMCU,
272 ASPEED_DEV_DP,
273 ASPEED_DEV_I3C,
274 ASPEED_DEV_ESPI,
275 ASPEED_DEV_UDC,
276 ASPEED_DEV_SGPIOM,
277 ASPEED_DEV_JTAG0,
278 ASPEED_DEV_JTAG1,
279 ASPEED_DEV_FSI1,
280 ASPEED_DEV_FSI2,
281 ASPEED_DEV_SCUIO,
282 ASPEED_DEV_SLI,
283 ASPEED_DEV_SLIIO,
284 ASPEED_GIC_DIST,
285 ASPEED_GIC_REDIST,
286 ASPEED_DEV_IPC0,
287 ASPEED_DEV_IPC1,
288 };
289
290 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev);
291 bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp);
292 void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr);
293 bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp);
294 void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr);
295 void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
296 const char *name, hwaddr addr,
297 uint64_t size);
298 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
299 unsigned int count, int unit0);
300
aspeed_uart_index(int uart_dev)301 static inline int aspeed_uart_index(int uart_dev)
302 {
303 return uart_dev - ASPEED_DEV_UART0;
304 }
305
aspeed_uart_first(AspeedSoCClass * sc)306 static inline int aspeed_uart_first(AspeedSoCClass *sc)
307 {
308 return aspeed_uart_index(sc->uarts_base);
309 }
310
aspeed_uart_last(AspeedSoCClass * sc)311 static inline int aspeed_uart_last(AspeedSoCClass *sc)
312 {
313 return aspeed_uart_first(sc) + sc->uarts_num - 1;
314 }
315
316 #endif /* ASPEED_SOC_H */
317