1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
73
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
77
78 /*
79 * Modules parameters.
80 */
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
91 extern int radeon_tv;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
97
98 /*
99 * Copy from radeon_drv.h so we don't have to include both and have conflicting
100 * symbol;
101 */
102 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
103 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
104 /* RADEON_IB_POOL_SIZE must be a power of 2 */
105 #define RADEON_IB_POOL_SIZE 16
106 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
107 #define RADEONFB_CONN_LIMIT 4
108 #define RADEON_BIOS_NUM_SCRATCH 8
109
110 /* max number of rings */
111 #define RADEON_NUM_RINGS 3
112
113 /* internal ring indices */
114 /* r1xx+ has gfx CP ring */
115 #define RADEON_RING_TYPE_GFX_INDEX 0
116
117 /* cayman has 2 compute CP rings */
118 #define CAYMAN_RING_TYPE_CP1_INDEX 1
119 #define CAYMAN_RING_TYPE_CP2_INDEX 2
120
121 /* hardcode those limit for now */
122 #define RADEON_VA_RESERVED_SIZE (8 << 20)
123 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
124
125 /*
126 * Errata workarounds.
127 */
128 enum radeon_pll_errata {
129 CHIP_ERRATA_R300_CG = 0x00000001,
130 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
131 CHIP_ERRATA_PLL_DELAY = 0x00000004
132 };
133
134
135 struct radeon_device;
136
137
138 /*
139 * BIOS.
140 */
141 #define ATRM_BIOS_PAGE 4096
142
143 #if defined(CONFIG_VGA_SWITCHEROO)
144 bool radeon_atrm_supported(struct pci_dev *pdev);
145 int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
146 #else
radeon_atrm_supported(struct pci_dev * pdev)147 static inline bool radeon_atrm_supported(struct pci_dev *pdev)
148 {
149 return false;
150 }
151
radeon_atrm_get_bios_chunk(uint8_t * bios,int offset,int len)152 static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
153 return -EINVAL;
154 }
155 #endif
156 bool radeon_get_bios(struct radeon_device *rdev);
157
158
159 /*
160 * Mutex which allows recursive locking from the same process.
161 */
162 struct radeon_mutex {
163 struct mutex mutex;
164 struct task_struct *owner;
165 int level;
166 };
167
radeon_mutex_init(struct radeon_mutex * mutex)168 static inline void radeon_mutex_init(struct radeon_mutex *mutex)
169 {
170 mutex_init(&mutex->mutex);
171 mutex->owner = NULL;
172 mutex->level = 0;
173 }
174
radeon_mutex_lock(struct radeon_mutex * mutex)175 static inline void radeon_mutex_lock(struct radeon_mutex *mutex)
176 {
177 if (mutex_trylock(&mutex->mutex)) {
178 /* The mutex was unlocked before, so it's ours now */
179 mutex->owner = current;
180 } else if (mutex->owner != current) {
181 /* Another process locked the mutex, take it */
182 mutex_lock(&mutex->mutex);
183 mutex->owner = current;
184 }
185 /* Otherwise the mutex was already locked by this process */
186
187 mutex->level++;
188 }
189
radeon_mutex_unlock(struct radeon_mutex * mutex)190 static inline void radeon_mutex_unlock(struct radeon_mutex *mutex)
191 {
192 if (--mutex->level > 0)
193 return;
194
195 mutex->owner = NULL;
196 mutex_unlock(&mutex->mutex);
197 }
198
199
200 /*
201 * Dummy page
202 */
203 struct radeon_dummy_page {
204 struct page *page;
205 dma_addr_t addr;
206 };
207 int radeon_dummy_page_init(struct radeon_device *rdev);
208 void radeon_dummy_page_fini(struct radeon_device *rdev);
209
210
211 /*
212 * Clocks
213 */
214 struct radeon_clock {
215 struct radeon_pll p1pll;
216 struct radeon_pll p2pll;
217 struct radeon_pll dcpll;
218 struct radeon_pll spll;
219 struct radeon_pll mpll;
220 /* 10 Khz units */
221 uint32_t default_mclk;
222 uint32_t default_sclk;
223 uint32_t default_dispclk;
224 uint32_t dp_extclk;
225 uint32_t max_pixel_clock;
226 };
227
228 /*
229 * Power management
230 */
231 int radeon_pm_init(struct radeon_device *rdev);
232 void radeon_pm_fini(struct radeon_device *rdev);
233 void radeon_pm_compute_clocks(struct radeon_device *rdev);
234 void radeon_pm_suspend(struct radeon_device *rdev);
235 void radeon_pm_resume(struct radeon_device *rdev);
236 void radeon_combios_get_power_modes(struct radeon_device *rdev);
237 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
238 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
239 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u16 *voltage);
240 void rs690_pm_info(struct radeon_device *rdev);
241 extern int rv6xx_get_temp(struct radeon_device *rdev);
242 extern int rv770_get_temp(struct radeon_device *rdev);
243 extern int evergreen_get_temp(struct radeon_device *rdev);
244 extern int sumo_get_temp(struct radeon_device *rdev);
245
246 /*
247 * Fences.
248 */
249 struct radeon_fence_driver {
250 uint32_t scratch_reg;
251 uint64_t gpu_addr;
252 volatile uint32_t *cpu_addr;
253 atomic_t seq;
254 uint32_t last_seq;
255 unsigned long last_jiffies;
256 unsigned long last_timeout;
257 wait_queue_head_t queue;
258 struct list_head created;
259 struct list_head emitted;
260 struct list_head signaled;
261 bool initialized;
262 };
263
264 struct radeon_fence {
265 struct radeon_device *rdev;
266 struct kref kref;
267 struct list_head list;
268 /* protected by radeon_fence.lock */
269 uint32_t seq;
270 bool emitted;
271 bool signaled;
272 /* RB, DMA, etc. */
273 int ring;
274 struct radeon_semaphore *semaphore;
275 };
276
277 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
278 int radeon_fence_driver_init(struct radeon_device *rdev);
279 void radeon_fence_driver_fini(struct radeon_device *rdev);
280 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
281 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
282 void radeon_fence_process(struct radeon_device *rdev, int ring);
283 bool radeon_fence_signaled(struct radeon_fence *fence);
284 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
285 int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
286 int radeon_fence_wait_last(struct radeon_device *rdev, int ring);
287 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
288 void radeon_fence_unref(struct radeon_fence **fence);
289 int radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
290
291 /*
292 * Tiling registers
293 */
294 struct radeon_surface_reg {
295 struct radeon_bo *bo;
296 };
297
298 #define RADEON_GEM_MAX_SURFACES 8
299
300 /*
301 * TTM.
302 */
303 struct radeon_mman {
304 struct ttm_bo_global_ref bo_global_ref;
305 struct drm_global_reference mem_global_ref;
306 struct ttm_bo_device bdev;
307 bool mem_global_referenced;
308 bool initialized;
309 };
310
311 /* bo virtual address in a specific vm */
312 struct radeon_bo_va {
313 /* bo list is protected by bo being reserved */
314 struct list_head bo_list;
315 /* vm list is protected by vm mutex */
316 struct list_head vm_list;
317 /* constant after initialization */
318 struct radeon_vm *vm;
319 struct radeon_bo *bo;
320 uint64_t soffset;
321 uint64_t eoffset;
322 uint32_t flags;
323 bool valid;
324 };
325
326 struct radeon_bo {
327 /* Protected by gem.mutex */
328 struct list_head list;
329 /* Protected by tbo.reserved */
330 u32 placements[3];
331 struct ttm_placement placement;
332 struct ttm_buffer_object tbo;
333 struct ttm_bo_kmap_obj kmap;
334 unsigned pin_count;
335 void *kptr;
336 u32 tiling_flags;
337 u32 pitch;
338 int surface_reg;
339 /* list of all virtual address to which this bo
340 * is associated to
341 */
342 struct list_head va;
343 /* Constant after initialization */
344 struct radeon_device *rdev;
345 struct drm_gem_object gem_base;
346 };
347 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
348
349 struct radeon_bo_list {
350 struct ttm_validate_buffer tv;
351 struct radeon_bo *bo;
352 uint64_t gpu_offset;
353 unsigned rdomain;
354 unsigned wdomain;
355 u32 tiling_flags;
356 };
357
358 /* sub-allocation manager, it has to be protected by another lock.
359 * By conception this is an helper for other part of the driver
360 * like the indirect buffer or semaphore, which both have their
361 * locking.
362 *
363 * Principe is simple, we keep a list of sub allocation in offset
364 * order (first entry has offset == 0, last entry has the highest
365 * offset).
366 *
367 * When allocating new object we first check if there is room at
368 * the end total_size - (last_object_offset + last_object_size) >=
369 * alloc_size. If so we allocate new object there.
370 *
371 * When there is not enough room at the end, we start waiting for
372 * each sub object until we reach object_offset+object_size >=
373 * alloc_size, this object then become the sub object we return.
374 *
375 * Alignment can't be bigger than page size.
376 *
377 * Hole are not considered for allocation to keep things simple.
378 * Assumption is that there won't be hole (all object on same
379 * alignment).
380 */
381 struct radeon_sa_manager {
382 struct radeon_bo *bo;
383 struct list_head sa_bo;
384 unsigned size;
385 uint64_t gpu_addr;
386 void *cpu_ptr;
387 uint32_t domain;
388 };
389
390 struct radeon_sa_bo;
391
392 /* sub-allocation buffer */
393 struct radeon_sa_bo {
394 struct list_head list;
395 struct radeon_sa_manager *manager;
396 unsigned offset;
397 unsigned size;
398 };
399
400 /*
401 * GEM objects.
402 */
403 struct radeon_gem {
404 struct mutex mutex;
405 struct list_head objects;
406 };
407
408 int radeon_gem_init(struct radeon_device *rdev);
409 void radeon_gem_fini(struct radeon_device *rdev);
410 int radeon_gem_object_create(struct radeon_device *rdev, int size,
411 int alignment, int initial_domain,
412 bool discardable, bool kernel,
413 struct drm_gem_object **obj);
414 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
415 uint64_t *gpu_addr);
416 void radeon_gem_object_unpin(struct drm_gem_object *obj);
417
418 int radeon_mode_dumb_create(struct drm_file *file_priv,
419 struct drm_device *dev,
420 struct drm_mode_create_dumb *args);
421 int radeon_mode_dumb_mmap(struct drm_file *filp,
422 struct drm_device *dev,
423 uint32_t handle, uint64_t *offset_p);
424 int radeon_mode_dumb_destroy(struct drm_file *file_priv,
425 struct drm_device *dev,
426 uint32_t handle);
427
428 /*
429 * Semaphores.
430 */
431 struct radeon_ring;
432
433 #define RADEON_SEMAPHORE_BO_SIZE 256
434
435 struct radeon_semaphore_driver {
436 rwlock_t lock;
437 struct list_head bo;
438 };
439
440 struct radeon_semaphore_bo;
441
442 /* everything here is constant */
443 struct radeon_semaphore {
444 struct list_head list;
445 uint64_t gpu_addr;
446 uint32_t *cpu_ptr;
447 struct radeon_semaphore_bo *bo;
448 };
449
450 struct radeon_semaphore_bo {
451 struct list_head list;
452 struct radeon_ib *ib;
453 struct list_head free;
454 struct radeon_semaphore semaphores[RADEON_SEMAPHORE_BO_SIZE/8];
455 unsigned nused;
456 };
457
458 void radeon_semaphore_driver_fini(struct radeon_device *rdev);
459 int radeon_semaphore_create(struct radeon_device *rdev,
460 struct radeon_semaphore **semaphore);
461 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
462 struct radeon_semaphore *semaphore);
463 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
464 struct radeon_semaphore *semaphore);
465 void radeon_semaphore_free(struct radeon_device *rdev,
466 struct radeon_semaphore *semaphore);
467
468 /*
469 * GART structures, functions & helpers
470 */
471 struct radeon_mc;
472
473 #define RADEON_GPU_PAGE_SIZE 4096
474 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
475 #define RADEON_GPU_PAGE_SHIFT 12
476 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
477
478 struct radeon_gart {
479 dma_addr_t table_addr;
480 struct radeon_bo *robj;
481 void *ptr;
482 unsigned num_gpu_pages;
483 unsigned num_cpu_pages;
484 unsigned table_size;
485 struct page **pages;
486 dma_addr_t *pages_addr;
487 bool ready;
488 };
489
490 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
491 void radeon_gart_table_ram_free(struct radeon_device *rdev);
492 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
493 void radeon_gart_table_vram_free(struct radeon_device *rdev);
494 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
495 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
496 int radeon_gart_init(struct radeon_device *rdev);
497 void radeon_gart_fini(struct radeon_device *rdev);
498 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
499 int pages);
500 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
501 int pages, struct page **pagelist,
502 dma_addr_t *dma_addr);
503 void radeon_gart_restore(struct radeon_device *rdev);
504
505
506 /*
507 * GPU MC structures, functions & helpers
508 */
509 struct radeon_mc {
510 resource_size_t aper_size;
511 resource_size_t aper_base;
512 resource_size_t agp_base;
513 /* for some chips with <= 32MB we need to lie
514 * about vram size near mc fb location */
515 u64 mc_vram_size;
516 u64 visible_vram_size;
517 u64 gtt_size;
518 u64 gtt_start;
519 u64 gtt_end;
520 u64 vram_start;
521 u64 vram_end;
522 unsigned vram_width;
523 u64 real_vram_size;
524 int vram_mtrr;
525 bool vram_is_ddr;
526 bool igp_sideport_enabled;
527 u64 gtt_base_align;
528 };
529
530 bool radeon_combios_sideport_present(struct radeon_device *rdev);
531 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
532
533 /*
534 * GPU scratch registers structures, functions & helpers
535 */
536 struct radeon_scratch {
537 unsigned num_reg;
538 uint32_t reg_base;
539 bool free[32];
540 uint32_t reg[32];
541 };
542
543 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
544 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
545
546
547 /*
548 * IRQS.
549 */
550
551 struct radeon_unpin_work {
552 struct work_struct work;
553 struct radeon_device *rdev;
554 int crtc_id;
555 struct radeon_fence *fence;
556 struct drm_pending_vblank_event *event;
557 struct radeon_bo *old_rbo;
558 u64 new_crtc_base;
559 };
560
561 struct r500_irq_stat_regs {
562 u32 disp_int;
563 };
564
565 struct r600_irq_stat_regs {
566 u32 disp_int;
567 u32 disp_int_cont;
568 u32 disp_int_cont2;
569 u32 d1grph_int;
570 u32 d2grph_int;
571 };
572
573 struct evergreen_irq_stat_regs {
574 u32 disp_int;
575 u32 disp_int_cont;
576 u32 disp_int_cont2;
577 u32 disp_int_cont3;
578 u32 disp_int_cont4;
579 u32 disp_int_cont5;
580 u32 d1grph_int;
581 u32 d2grph_int;
582 u32 d3grph_int;
583 u32 d4grph_int;
584 u32 d5grph_int;
585 u32 d6grph_int;
586 };
587
588 union radeon_irq_stat_regs {
589 struct r500_irq_stat_regs r500;
590 struct r600_irq_stat_regs r600;
591 struct evergreen_irq_stat_regs evergreen;
592 };
593
594 #define RADEON_MAX_HPD_PINS 6
595 #define RADEON_MAX_CRTCS 6
596 #define RADEON_MAX_HDMI_BLOCKS 2
597
598 struct radeon_irq {
599 bool installed;
600 bool sw_int[RADEON_NUM_RINGS];
601 bool crtc_vblank_int[RADEON_MAX_CRTCS];
602 bool pflip[RADEON_MAX_CRTCS];
603 wait_queue_head_t vblank_queue;
604 bool hpd[RADEON_MAX_HPD_PINS];
605 bool gui_idle;
606 bool gui_idle_acked;
607 wait_queue_head_t idle_queue;
608 bool hdmi[RADEON_MAX_HDMI_BLOCKS];
609 spinlock_t sw_lock;
610 int sw_refcount[RADEON_NUM_RINGS];
611 union radeon_irq_stat_regs stat_regs;
612 spinlock_t pflip_lock[RADEON_MAX_CRTCS];
613 int pflip_refcount[RADEON_MAX_CRTCS];
614 };
615
616 int radeon_irq_kms_init(struct radeon_device *rdev);
617 void radeon_irq_kms_fini(struct radeon_device *rdev);
618 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
619 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
620 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
621 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
622
623 /*
624 * CP & rings.
625 */
626
627 struct radeon_ib {
628 struct radeon_sa_bo sa_bo;
629 unsigned idx;
630 uint32_t length_dw;
631 uint64_t gpu_addr;
632 uint32_t *ptr;
633 struct radeon_fence *fence;
634 unsigned vm_id;
635 };
636
637 /*
638 * locking -
639 * mutex protects scheduled_ibs, ready, alloc_bm
640 */
641 struct radeon_ib_pool {
642 struct radeon_mutex mutex;
643 struct radeon_sa_manager sa_manager;
644 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
645 bool ready;
646 unsigned head_id;
647 };
648
649 struct radeon_ring {
650 struct radeon_bo *ring_obj;
651 volatile uint32_t *ring;
652 unsigned rptr;
653 unsigned rptr_offs;
654 unsigned rptr_reg;
655 unsigned wptr;
656 unsigned wptr_old;
657 unsigned wptr_reg;
658 unsigned ring_size;
659 unsigned ring_free_dw;
660 int count_dw;
661 uint64_t gpu_addr;
662 uint32_t align_mask;
663 uint32_t ptr_mask;
664 struct mutex mutex;
665 bool ready;
666 u32 ptr_reg_shift;
667 u32 ptr_reg_mask;
668 u32 nop;
669 };
670
671 /*
672 * VM
673 */
674 struct radeon_vm {
675 struct list_head list;
676 struct list_head va;
677 int id;
678 unsigned last_pfn;
679 u64 pt_gpu_addr;
680 u64 *pt;
681 struct radeon_sa_bo sa_bo;
682 struct mutex mutex;
683 /* last fence for cs using this vm */
684 struct radeon_fence *fence;
685 };
686
687 struct radeon_vm_funcs {
688 int (*init)(struct radeon_device *rdev);
689 void (*fini)(struct radeon_device *rdev);
690 /* cs mutex must be lock for schedule_ib */
691 int (*bind)(struct radeon_device *rdev, struct radeon_vm *vm, int id);
692 void (*unbind)(struct radeon_device *rdev, struct radeon_vm *vm);
693 void (*tlb_flush)(struct radeon_device *rdev, struct radeon_vm *vm);
694 uint32_t (*page_flags)(struct radeon_device *rdev,
695 struct radeon_vm *vm,
696 uint32_t flags);
697 void (*set_page)(struct radeon_device *rdev, struct radeon_vm *vm,
698 unsigned pfn, uint64_t addr, uint32_t flags);
699 };
700
701 struct radeon_vm_manager {
702 struct list_head lru_vm;
703 uint32_t use_bitmap;
704 struct radeon_sa_manager sa_manager;
705 uint32_t max_pfn;
706 /* fields constant after init */
707 const struct radeon_vm_funcs *funcs;
708 /* number of VMIDs */
709 unsigned nvm;
710 /* vram base address for page table entry */
711 u64 vram_base_offset;
712 /* is vm enabled? */
713 bool enabled;
714 };
715
716 /*
717 * file private structure
718 */
719 struct radeon_fpriv {
720 struct radeon_vm vm;
721 };
722
723 /*
724 * R6xx+ IH ring
725 */
726 struct r600_ih {
727 struct radeon_bo *ring_obj;
728 volatile uint32_t *ring;
729 unsigned rptr;
730 unsigned rptr_offs;
731 unsigned wptr;
732 unsigned wptr_old;
733 unsigned ring_size;
734 uint64_t gpu_addr;
735 uint32_t ptr_mask;
736 spinlock_t lock;
737 bool enabled;
738 };
739
740 struct r600_blit_cp_primitives {
741 void (*set_render_target)(struct radeon_device *rdev, int format,
742 int w, int h, u64 gpu_addr);
743 void (*cp_set_surface_sync)(struct radeon_device *rdev,
744 u32 sync_type, u32 size,
745 u64 mc_addr);
746 void (*set_shaders)(struct radeon_device *rdev);
747 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
748 void (*set_tex_resource)(struct radeon_device *rdev,
749 int format, int w, int h, int pitch,
750 u64 gpu_addr, u32 size);
751 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
752 int x2, int y2);
753 void (*draw_auto)(struct radeon_device *rdev);
754 void (*set_default_state)(struct radeon_device *rdev);
755 };
756
757 struct r600_blit {
758 struct mutex mutex;
759 struct radeon_bo *shader_obj;
760 struct r600_blit_cp_primitives primitives;
761 int max_dim;
762 int ring_size_common;
763 int ring_size_per_loop;
764 u64 shader_gpu_addr;
765 u32 vs_offset, ps_offset;
766 u32 state_offset;
767 u32 state_len;
768 u32 vb_used, vb_total;
769 struct radeon_ib *vb_ib;
770 };
771
772 void r600_blit_suspend(struct radeon_device *rdev);
773
774 int radeon_ib_get(struct radeon_device *rdev, int ring,
775 struct radeon_ib **ib, unsigned size);
776 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
777 bool radeon_ib_try_free(struct radeon_device *rdev, struct radeon_ib *ib);
778 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
779 int radeon_ib_pool_init(struct radeon_device *rdev);
780 void radeon_ib_pool_fini(struct radeon_device *rdev);
781 int radeon_ib_pool_start(struct radeon_device *rdev);
782 int radeon_ib_pool_suspend(struct radeon_device *rdev);
783 int radeon_ib_test(struct radeon_device *rdev);
784 /* Ring access between begin & end cannot sleep */
785 int radeon_ring_index(struct radeon_device *rdev, struct radeon_ring *cp);
786 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
787 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
788 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
789 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
790 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
791 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
792 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
793 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
794 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
795 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
796 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
797
798
799 /*
800 * CS.
801 */
802 struct radeon_cs_reloc {
803 struct drm_gem_object *gobj;
804 struct radeon_bo *robj;
805 struct radeon_bo_list lobj;
806 uint32_t handle;
807 uint32_t flags;
808 };
809
810 struct radeon_cs_chunk {
811 uint32_t chunk_id;
812 uint32_t length_dw;
813 int kpage_idx[2];
814 uint32_t *kpage[2];
815 uint32_t *kdata;
816 void __user *user_ptr;
817 int last_copied_page;
818 int last_page_index;
819 };
820
821 struct radeon_cs_parser {
822 struct device *dev;
823 struct radeon_device *rdev;
824 struct drm_file *filp;
825 /* chunks */
826 unsigned nchunks;
827 struct radeon_cs_chunk *chunks;
828 uint64_t *chunks_array;
829 /* IB */
830 unsigned idx;
831 /* relocations */
832 unsigned nrelocs;
833 struct radeon_cs_reloc *relocs;
834 struct radeon_cs_reloc **relocs_ptr;
835 struct list_head validated;
836 bool sync_to_ring[RADEON_NUM_RINGS];
837 /* indices of various chunks */
838 int chunk_ib_idx;
839 int chunk_relocs_idx;
840 int chunk_flags_idx;
841 struct radeon_ib *ib;
842 void *track;
843 unsigned family;
844 int parser_error;
845 u32 cs_flags;
846 u32 ring;
847 s32 priority;
848 };
849
850 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
851 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
852 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
853
854 struct radeon_cs_packet {
855 unsigned idx;
856 unsigned type;
857 unsigned reg;
858 unsigned opcode;
859 int count;
860 unsigned one_reg_wr;
861 };
862
863 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
864 struct radeon_cs_packet *pkt,
865 unsigned idx, unsigned reg);
866 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
867 struct radeon_cs_packet *pkt);
868
869
870 /*
871 * AGP
872 */
873 int radeon_agp_init(struct radeon_device *rdev);
874 void radeon_agp_resume(struct radeon_device *rdev);
875 void radeon_agp_suspend(struct radeon_device *rdev);
876 void radeon_agp_fini(struct radeon_device *rdev);
877
878
879 /*
880 * Writeback
881 */
882 struct radeon_wb {
883 struct radeon_bo *wb_obj;
884 volatile uint32_t *wb;
885 uint64_t gpu_addr;
886 bool enabled;
887 bool use_event;
888 };
889
890 #define RADEON_WB_SCRATCH_OFFSET 0
891 #define RADEON_WB_CP_RPTR_OFFSET 1024
892 #define RADEON_WB_CP1_RPTR_OFFSET 1280
893 #define RADEON_WB_CP2_RPTR_OFFSET 1536
894 #define R600_WB_IH_WPTR_OFFSET 2048
895 #define R600_WB_EVENT_OFFSET 3072
896
897 /**
898 * struct radeon_pm - power management datas
899 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
900 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
901 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
902 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
903 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
904 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
905 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
906 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
907 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
908 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
909 * @needed_bandwidth: current bandwidth needs
910 *
911 * It keeps track of various data needed to take powermanagement decision.
912 * Bandwidth need is used to determine minimun clock of the GPU and memory.
913 * Equation between gpu/memory clock and available bandwidth is hw dependent
914 * (type of memory, bus size, efficiency, ...)
915 */
916
917 enum radeon_pm_method {
918 PM_METHOD_PROFILE,
919 PM_METHOD_DYNPM,
920 };
921
922 enum radeon_dynpm_state {
923 DYNPM_STATE_DISABLED,
924 DYNPM_STATE_MINIMUM,
925 DYNPM_STATE_PAUSED,
926 DYNPM_STATE_ACTIVE,
927 DYNPM_STATE_SUSPENDED,
928 };
929 enum radeon_dynpm_action {
930 DYNPM_ACTION_NONE,
931 DYNPM_ACTION_MINIMUM,
932 DYNPM_ACTION_DOWNCLOCK,
933 DYNPM_ACTION_UPCLOCK,
934 DYNPM_ACTION_DEFAULT
935 };
936
937 enum radeon_voltage_type {
938 VOLTAGE_NONE = 0,
939 VOLTAGE_GPIO,
940 VOLTAGE_VDDC,
941 VOLTAGE_SW
942 };
943
944 enum radeon_pm_state_type {
945 POWER_STATE_TYPE_DEFAULT,
946 POWER_STATE_TYPE_POWERSAVE,
947 POWER_STATE_TYPE_BATTERY,
948 POWER_STATE_TYPE_BALANCED,
949 POWER_STATE_TYPE_PERFORMANCE,
950 };
951
952 enum radeon_pm_profile_type {
953 PM_PROFILE_DEFAULT,
954 PM_PROFILE_AUTO,
955 PM_PROFILE_LOW,
956 PM_PROFILE_MID,
957 PM_PROFILE_HIGH,
958 };
959
960 #define PM_PROFILE_DEFAULT_IDX 0
961 #define PM_PROFILE_LOW_SH_IDX 1
962 #define PM_PROFILE_MID_SH_IDX 2
963 #define PM_PROFILE_HIGH_SH_IDX 3
964 #define PM_PROFILE_LOW_MH_IDX 4
965 #define PM_PROFILE_MID_MH_IDX 5
966 #define PM_PROFILE_HIGH_MH_IDX 6
967 #define PM_PROFILE_MAX 7
968
969 struct radeon_pm_profile {
970 int dpms_off_ps_idx;
971 int dpms_on_ps_idx;
972 int dpms_off_cm_idx;
973 int dpms_on_cm_idx;
974 };
975
976 enum radeon_int_thermal_type {
977 THERMAL_TYPE_NONE,
978 THERMAL_TYPE_RV6XX,
979 THERMAL_TYPE_RV770,
980 THERMAL_TYPE_EVERGREEN,
981 THERMAL_TYPE_SUMO,
982 THERMAL_TYPE_NI,
983 };
984
985 struct radeon_voltage {
986 enum radeon_voltage_type type;
987 /* gpio voltage */
988 struct radeon_gpio_rec gpio;
989 u32 delay; /* delay in usec from voltage drop to sclk change */
990 bool active_high; /* voltage drop is active when bit is high */
991 /* VDDC voltage */
992 u8 vddc_id; /* index into vddc voltage table */
993 u8 vddci_id; /* index into vddci voltage table */
994 bool vddci_enabled;
995 /* r6xx+ sw */
996 u16 voltage;
997 /* evergreen+ vddci */
998 u16 vddci;
999 };
1000
1001 /* clock mode flags */
1002 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1003
1004 struct radeon_pm_clock_info {
1005 /* memory clock */
1006 u32 mclk;
1007 /* engine clock */
1008 u32 sclk;
1009 /* voltage info */
1010 struct radeon_voltage voltage;
1011 /* standardized clock flags */
1012 u32 flags;
1013 };
1014
1015 /* state flags */
1016 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1017
1018 struct radeon_power_state {
1019 enum radeon_pm_state_type type;
1020 struct radeon_pm_clock_info *clock_info;
1021 /* number of valid clock modes in this power state */
1022 int num_clock_modes;
1023 struct radeon_pm_clock_info *default_clock_mode;
1024 /* standardized state flags */
1025 u32 flags;
1026 u32 misc; /* vbios specific flags */
1027 u32 misc2; /* vbios specific flags */
1028 int pcie_lanes; /* pcie lanes */
1029 };
1030
1031 /*
1032 * Some modes are overclocked by very low value, accept them
1033 */
1034 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1035
1036 struct radeon_pm {
1037 struct mutex mutex;
1038 u32 active_crtcs;
1039 int active_crtc_count;
1040 int req_vblank;
1041 bool vblank_sync;
1042 bool gui_idle;
1043 fixed20_12 max_bandwidth;
1044 fixed20_12 igp_sideport_mclk;
1045 fixed20_12 igp_system_mclk;
1046 fixed20_12 igp_ht_link_clk;
1047 fixed20_12 igp_ht_link_width;
1048 fixed20_12 k8_bandwidth;
1049 fixed20_12 sideport_bandwidth;
1050 fixed20_12 ht_bandwidth;
1051 fixed20_12 core_bandwidth;
1052 fixed20_12 sclk;
1053 fixed20_12 mclk;
1054 fixed20_12 needed_bandwidth;
1055 struct radeon_power_state *power_state;
1056 /* number of valid power states */
1057 int num_power_states;
1058 int current_power_state_index;
1059 int current_clock_mode_index;
1060 int requested_power_state_index;
1061 int requested_clock_mode_index;
1062 int default_power_state_index;
1063 u32 current_sclk;
1064 u32 current_mclk;
1065 u16 current_vddc;
1066 u16 current_vddci;
1067 u32 default_sclk;
1068 u32 default_mclk;
1069 u16 default_vddc;
1070 u16 default_vddci;
1071 struct radeon_i2c_chan *i2c_bus;
1072 /* selected pm method */
1073 enum radeon_pm_method pm_method;
1074 /* dynpm power management */
1075 struct delayed_work dynpm_idle_work;
1076 enum radeon_dynpm_state dynpm_state;
1077 enum radeon_dynpm_action dynpm_planned_action;
1078 unsigned long dynpm_action_timeout;
1079 bool dynpm_can_upclock;
1080 bool dynpm_can_downclock;
1081 /* profile-based power management */
1082 enum radeon_pm_profile_type profile;
1083 int profile_index;
1084 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1085 /* internal thermal controller on rv6xx+ */
1086 enum radeon_int_thermal_type int_thermal_type;
1087 struct device *int_hwmon_dev;
1088 };
1089
1090 int radeon_pm_get_type_index(struct radeon_device *rdev,
1091 enum radeon_pm_state_type ps_type,
1092 int instance);
1093
1094 /*
1095 * Benchmarking
1096 */
1097 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1098
1099
1100 /*
1101 * Testing
1102 */
1103 void radeon_test_moves(struct radeon_device *rdev);
1104 void radeon_test_ring_sync(struct radeon_device *rdev,
1105 struct radeon_ring *cpA,
1106 struct radeon_ring *cpB);
1107 void radeon_test_syncing(struct radeon_device *rdev);
1108
1109
1110 /*
1111 * Debugfs
1112 */
1113 struct radeon_debugfs {
1114 struct drm_info_list *files;
1115 unsigned num_files;
1116 };
1117
1118 int radeon_debugfs_add_files(struct radeon_device *rdev,
1119 struct drm_info_list *files,
1120 unsigned nfiles);
1121 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1122
1123
1124 /*
1125 * ASIC specific functions.
1126 */
1127 struct radeon_asic {
1128 int (*init)(struct radeon_device *rdev);
1129 void (*fini)(struct radeon_device *rdev);
1130 int (*resume)(struct radeon_device *rdev);
1131 int (*suspend)(struct radeon_device *rdev);
1132 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1133 bool (*gpu_is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1134 int (*asic_reset)(struct radeon_device *rdev);
1135 void (*gart_tlb_flush)(struct radeon_device *rdev);
1136 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1137 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
1138 void (*cp_fini)(struct radeon_device *rdev);
1139 void (*cp_disable)(struct radeon_device *rdev);
1140 void (*ring_start)(struct radeon_device *rdev);
1141
1142 struct {
1143 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1144 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1145 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1146 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1147 struct radeon_semaphore *semaphore, bool emit_wait);
1148 } ring[RADEON_NUM_RINGS];
1149
1150 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1151 int (*irq_set)(struct radeon_device *rdev);
1152 int (*irq_process)(struct radeon_device *rdev);
1153 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1154 int (*cs_parse)(struct radeon_cs_parser *p);
1155 int (*copy_blit)(struct radeon_device *rdev,
1156 uint64_t src_offset,
1157 uint64_t dst_offset,
1158 unsigned num_gpu_pages,
1159 struct radeon_fence *fence);
1160 int (*copy_dma)(struct radeon_device *rdev,
1161 uint64_t src_offset,
1162 uint64_t dst_offset,
1163 unsigned num_gpu_pages,
1164 struct radeon_fence *fence);
1165 int (*copy)(struct radeon_device *rdev,
1166 uint64_t src_offset,
1167 uint64_t dst_offset,
1168 unsigned num_gpu_pages,
1169 struct radeon_fence *fence);
1170 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1171 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1172 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1173 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1174 int (*get_pcie_lanes)(struct radeon_device *rdev);
1175 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1176 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1177 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
1178 uint32_t tiling_flags, uint32_t pitch,
1179 uint32_t offset, uint32_t obj_size);
1180 void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
1181 void (*bandwidth_update)(struct radeon_device *rdev);
1182 void (*hpd_init)(struct radeon_device *rdev);
1183 void (*hpd_fini)(struct radeon_device *rdev);
1184 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1185 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1186 /* ioctl hw specific callback. Some hw might want to perform special
1187 * operation on specific ioctl. For instance on wait idle some hw
1188 * might want to perform and HDP flush through MMIO as it seems that
1189 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1190 * through ring.
1191 */
1192 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1193 bool (*gui_idle)(struct radeon_device *rdev);
1194 /* power management */
1195 void (*pm_misc)(struct radeon_device *rdev);
1196 void (*pm_prepare)(struct radeon_device *rdev);
1197 void (*pm_finish)(struct radeon_device *rdev);
1198 void (*pm_init_profile)(struct radeon_device *rdev);
1199 void (*pm_get_dynpm_state)(struct radeon_device *rdev);
1200 /* pageflipping */
1201 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1202 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1203 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1204 };
1205
1206 /*
1207 * Asic structures
1208 */
1209 struct r100_gpu_lockup {
1210 unsigned long last_jiffies;
1211 u32 last_cp_rptr;
1212 };
1213
1214 struct r100_asic {
1215 const unsigned *reg_safe_bm;
1216 unsigned reg_safe_bm_size;
1217 u32 hdp_cntl;
1218 struct r100_gpu_lockup lockup;
1219 };
1220
1221 struct r300_asic {
1222 const unsigned *reg_safe_bm;
1223 unsigned reg_safe_bm_size;
1224 u32 resync_scratch;
1225 u32 hdp_cntl;
1226 struct r100_gpu_lockup lockup;
1227 };
1228
1229 struct r600_asic {
1230 unsigned max_pipes;
1231 unsigned max_tile_pipes;
1232 unsigned max_simds;
1233 unsigned max_backends;
1234 unsigned max_gprs;
1235 unsigned max_threads;
1236 unsigned max_stack_entries;
1237 unsigned max_hw_contexts;
1238 unsigned max_gs_threads;
1239 unsigned sx_max_export_size;
1240 unsigned sx_max_export_pos_size;
1241 unsigned sx_max_export_smx_size;
1242 unsigned sq_num_cf_insts;
1243 unsigned tiling_nbanks;
1244 unsigned tiling_npipes;
1245 unsigned tiling_group_size;
1246 unsigned tile_config;
1247 unsigned backend_map;
1248 struct r100_gpu_lockup lockup;
1249 };
1250
1251 struct rv770_asic {
1252 unsigned max_pipes;
1253 unsigned max_tile_pipes;
1254 unsigned max_simds;
1255 unsigned max_backends;
1256 unsigned max_gprs;
1257 unsigned max_threads;
1258 unsigned max_stack_entries;
1259 unsigned max_hw_contexts;
1260 unsigned max_gs_threads;
1261 unsigned sx_max_export_size;
1262 unsigned sx_max_export_pos_size;
1263 unsigned sx_max_export_smx_size;
1264 unsigned sq_num_cf_insts;
1265 unsigned sx_num_of_sets;
1266 unsigned sc_prim_fifo_size;
1267 unsigned sc_hiz_tile_fifo_size;
1268 unsigned sc_earlyz_tile_fifo_fize;
1269 unsigned tiling_nbanks;
1270 unsigned tiling_npipes;
1271 unsigned tiling_group_size;
1272 unsigned tile_config;
1273 unsigned backend_map;
1274 struct r100_gpu_lockup lockup;
1275 };
1276
1277 struct evergreen_asic {
1278 unsigned num_ses;
1279 unsigned max_pipes;
1280 unsigned max_tile_pipes;
1281 unsigned max_simds;
1282 unsigned max_backends;
1283 unsigned max_gprs;
1284 unsigned max_threads;
1285 unsigned max_stack_entries;
1286 unsigned max_hw_contexts;
1287 unsigned max_gs_threads;
1288 unsigned sx_max_export_size;
1289 unsigned sx_max_export_pos_size;
1290 unsigned sx_max_export_smx_size;
1291 unsigned sq_num_cf_insts;
1292 unsigned sx_num_of_sets;
1293 unsigned sc_prim_fifo_size;
1294 unsigned sc_hiz_tile_fifo_size;
1295 unsigned sc_earlyz_tile_fifo_size;
1296 unsigned tiling_nbanks;
1297 unsigned tiling_npipes;
1298 unsigned tiling_group_size;
1299 unsigned tile_config;
1300 unsigned backend_map;
1301 struct r100_gpu_lockup lockup;
1302 };
1303
1304 struct cayman_asic {
1305 unsigned max_shader_engines;
1306 unsigned max_pipes_per_simd;
1307 unsigned max_tile_pipes;
1308 unsigned max_simds_per_se;
1309 unsigned max_backends_per_se;
1310 unsigned max_texture_channel_caches;
1311 unsigned max_gprs;
1312 unsigned max_threads;
1313 unsigned max_gs_threads;
1314 unsigned max_stack_entries;
1315 unsigned sx_num_of_sets;
1316 unsigned sx_max_export_size;
1317 unsigned sx_max_export_pos_size;
1318 unsigned sx_max_export_smx_size;
1319 unsigned max_hw_contexts;
1320 unsigned sq_num_cf_insts;
1321 unsigned sc_prim_fifo_size;
1322 unsigned sc_hiz_tile_fifo_size;
1323 unsigned sc_earlyz_tile_fifo_size;
1324
1325 unsigned num_shader_engines;
1326 unsigned num_shader_pipes_per_simd;
1327 unsigned num_tile_pipes;
1328 unsigned num_simds_per_se;
1329 unsigned num_backends_per_se;
1330 unsigned backend_disable_mask_per_asic;
1331 unsigned backend_map;
1332 unsigned num_texture_channel_caches;
1333 unsigned mem_max_burst_length_bytes;
1334 unsigned mem_row_size_in_kb;
1335 unsigned shader_engine_tile_size;
1336 unsigned num_gpus;
1337 unsigned multi_gpu_tile_size;
1338
1339 unsigned tile_config;
1340 struct r100_gpu_lockup lockup;
1341 };
1342
1343 union radeon_asic_config {
1344 struct r300_asic r300;
1345 struct r100_asic r100;
1346 struct r600_asic r600;
1347 struct rv770_asic rv770;
1348 struct evergreen_asic evergreen;
1349 struct cayman_asic cayman;
1350 };
1351
1352 /*
1353 * asic initizalization from radeon_asic.c
1354 */
1355 void radeon_agp_disable(struct radeon_device *rdev);
1356 int radeon_asic_init(struct radeon_device *rdev);
1357
1358
1359 /*
1360 * IOCTL.
1361 */
1362 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1363 struct drm_file *filp);
1364 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1365 struct drm_file *filp);
1366 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1367 struct drm_file *file_priv);
1368 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1369 struct drm_file *file_priv);
1370 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1371 struct drm_file *file_priv);
1372 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1373 struct drm_file *file_priv);
1374 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1375 struct drm_file *filp);
1376 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1377 struct drm_file *filp);
1378 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1379 struct drm_file *filp);
1380 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1381 struct drm_file *filp);
1382 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1383 struct drm_file *filp);
1384 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1385 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1386 struct drm_file *filp);
1387 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1388 struct drm_file *filp);
1389
1390 /* VRAM scratch page for HDP bug, default vram page */
1391 struct r600_vram_scratch {
1392 struct radeon_bo *robj;
1393 volatile uint32_t *ptr;
1394 u64 gpu_addr;
1395 };
1396
1397
1398 /*
1399 * Core structure, functions and helpers.
1400 */
1401 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1402 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1403
1404 struct radeon_device {
1405 struct device *dev;
1406 struct drm_device *ddev;
1407 struct pci_dev *pdev;
1408 /* ASIC */
1409 union radeon_asic_config config;
1410 enum radeon_family family;
1411 unsigned long flags;
1412 int usec_timeout;
1413 enum radeon_pll_errata pll_errata;
1414 int num_gb_pipes;
1415 int num_z_pipes;
1416 int disp_priority;
1417 /* BIOS */
1418 uint8_t *bios;
1419 bool is_atom_bios;
1420 uint16_t bios_header_start;
1421 struct radeon_bo *stollen_vga_memory;
1422 /* Register mmio */
1423 resource_size_t rmmio_base;
1424 resource_size_t rmmio_size;
1425 void __iomem *rmmio;
1426 radeon_rreg_t mc_rreg;
1427 radeon_wreg_t mc_wreg;
1428 radeon_rreg_t pll_rreg;
1429 radeon_wreg_t pll_wreg;
1430 uint32_t pcie_reg_mask;
1431 radeon_rreg_t pciep_rreg;
1432 radeon_wreg_t pciep_wreg;
1433 /* io port */
1434 void __iomem *rio_mem;
1435 resource_size_t rio_mem_size;
1436 struct radeon_clock clock;
1437 struct radeon_mc mc;
1438 struct radeon_gart gart;
1439 struct radeon_mode_info mode_info;
1440 struct radeon_scratch scratch;
1441 struct radeon_mman mman;
1442 rwlock_t fence_lock;
1443 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
1444 struct radeon_semaphore_driver semaphore_drv;
1445 struct radeon_ring ring[RADEON_NUM_RINGS];
1446 struct radeon_ib_pool ib_pool;
1447 struct radeon_irq irq;
1448 struct radeon_asic *asic;
1449 struct radeon_gem gem;
1450 struct radeon_pm pm;
1451 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1452 struct radeon_mutex cs_mutex;
1453 struct radeon_wb wb;
1454 struct radeon_dummy_page dummy_page;
1455 bool gpu_lockup;
1456 bool shutdown;
1457 bool suspend;
1458 bool need_dma32;
1459 bool accel_working;
1460 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1461 const struct firmware *me_fw; /* all family ME firmware */
1462 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1463 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1464 const struct firmware *mc_fw; /* NI MC firmware */
1465 struct r600_blit r600_blit;
1466 struct r600_vram_scratch vram_scratch;
1467 int msi_enabled; /* msi enabled */
1468 struct r600_ih ih; /* r6/700 interrupt ring */
1469 struct work_struct hotplug_work;
1470 int num_crtc; /* number of crtcs */
1471 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1472 struct mutex vram_mutex;
1473
1474 /* audio stuff */
1475 bool audio_enabled;
1476 struct timer_list audio_timer;
1477 int audio_channels;
1478 int audio_rate;
1479 int audio_bits_per_sample;
1480 uint8_t audio_status_bits;
1481 uint8_t audio_category_code;
1482
1483 struct notifier_block acpi_nb;
1484 /* only one userspace can use Hyperz features or CMASK at a time */
1485 struct drm_file *hyperz_filp;
1486 struct drm_file *cmask_filp;
1487 /* i2c buses */
1488 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1489 /* debugfs */
1490 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
1491 unsigned debugfs_count;
1492 /* virtual memory */
1493 struct radeon_vm_manager vm_manager;
1494 /* ring used for bo copies */
1495 u32 copy_ring;
1496 };
1497
1498 int radeon_device_init(struct radeon_device *rdev,
1499 struct drm_device *ddev,
1500 struct pci_dev *pdev,
1501 uint32_t flags);
1502 void radeon_device_fini(struct radeon_device *rdev);
1503 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1504
1505 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
1506 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
1507 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
1508 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1509
1510 /*
1511 * Cast helper
1512 */
1513 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1514
1515 /*
1516 * Registers read & write functions.
1517 */
1518 #define RREG8(reg) readb((rdev->rmmio) + (reg))
1519 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1520 #define RREG16(reg) readw((rdev->rmmio) + (reg))
1521 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
1522 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1523 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1524 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1525 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1526 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1527 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1528 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1529 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1530 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1531 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1532 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1533 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1534 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1535 #define WREG32_P(reg, val, mask) \
1536 do { \
1537 uint32_t tmp_ = RREG32(reg); \
1538 tmp_ &= (mask); \
1539 tmp_ |= ((val) & ~(mask)); \
1540 WREG32(reg, tmp_); \
1541 } while (0)
1542 #define WREG32_PLL_P(reg, val, mask) \
1543 do { \
1544 uint32_t tmp_ = RREG32_PLL(reg); \
1545 tmp_ &= (mask); \
1546 tmp_ |= ((val) & ~(mask)); \
1547 WREG32_PLL(reg, tmp_); \
1548 } while (0)
1549 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1550 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1551 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1552
1553 /*
1554 * Indirect registers accessor
1555 */
rv370_pcie_rreg(struct radeon_device * rdev,uint32_t reg)1556 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1557 {
1558 uint32_t r;
1559
1560 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1561 r = RREG32(RADEON_PCIE_DATA);
1562 return r;
1563 }
1564
rv370_pcie_wreg(struct radeon_device * rdev,uint32_t reg,uint32_t v)1565 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1566 {
1567 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1568 WREG32(RADEON_PCIE_DATA, (v));
1569 }
1570
1571 void r100_pll_errata_after_index(struct radeon_device *rdev);
1572
1573
1574 /*
1575 * ASICs helpers.
1576 */
1577 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1578 (rdev->pdev->device == 0x5969))
1579 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1580 (rdev->family == CHIP_RV200) || \
1581 (rdev->family == CHIP_RS100) || \
1582 (rdev->family == CHIP_RS200) || \
1583 (rdev->family == CHIP_RV250) || \
1584 (rdev->family == CHIP_RV280) || \
1585 (rdev->family == CHIP_RS300))
1586 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1587 (rdev->family == CHIP_RV350) || \
1588 (rdev->family == CHIP_R350) || \
1589 (rdev->family == CHIP_RV380) || \
1590 (rdev->family == CHIP_R420) || \
1591 (rdev->family == CHIP_R423) || \
1592 (rdev->family == CHIP_RV410) || \
1593 (rdev->family == CHIP_RS400) || \
1594 (rdev->family == CHIP_RS480))
1595 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1596 (rdev->ddev->pdev->device == 0x9443) || \
1597 (rdev->ddev->pdev->device == 0x944B) || \
1598 (rdev->ddev->pdev->device == 0x9506) || \
1599 (rdev->ddev->pdev->device == 0x9509) || \
1600 (rdev->ddev->pdev->device == 0x950F) || \
1601 (rdev->ddev->pdev->device == 0x689C) || \
1602 (rdev->ddev->pdev->device == 0x689D))
1603 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1604 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1605 (rdev->family == CHIP_RS690) || \
1606 (rdev->family == CHIP_RS740) || \
1607 (rdev->family >= CHIP_R600))
1608 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1609 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1610 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1611 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1612 (rdev->flags & RADEON_IS_IGP))
1613 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1614
1615 /*
1616 * BIOS helpers.
1617 */
1618 #define RBIOS8(i) (rdev->bios[i])
1619 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1620 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1621
1622 int radeon_combios_init(struct radeon_device *rdev);
1623 void radeon_combios_fini(struct radeon_device *rdev);
1624 int radeon_atombios_init(struct radeon_device *rdev);
1625 void radeon_atombios_fini(struct radeon_device *rdev);
1626
1627
1628 /*
1629 * RING helpers.
1630 */
1631 #if DRM_DEBUG_CODE == 0
radeon_ring_write(struct radeon_ring * ring,uint32_t v)1632 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
1633 {
1634 ring->ring[ring->wptr++] = v;
1635 ring->wptr &= ring->ptr_mask;
1636 ring->count_dw--;
1637 ring->ring_free_dw--;
1638 }
1639 #else
1640 /* With debugging this is just too big to inline */
1641 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
1642 #endif
1643
1644 /*
1645 * ASICs macro.
1646 */
1647 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1648 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1649 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1650 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1651 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
1652 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1653 #define radeon_gpu_is_lockup(rdev, cp) (rdev)->asic->gpu_is_lockup((rdev), (cp))
1654 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1655 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1656 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1657 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1658 #define radeon_ring_test(rdev, cp) (rdev)->asic->ring_test((rdev), (cp))
1659 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
1660 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
1661 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1662 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1663 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1664 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
1665 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
1666 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1667 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1668 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1669 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1670 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1671 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1672 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1673 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
1674 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1675 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1676 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1677 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1678 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1679 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1680 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1681 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1682 #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1683 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1684 #define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev))
1685 #define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev))
1686 #define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev))
1687 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev))
1688 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev))
1689 #define radeon_pre_page_flip(rdev, crtc) rdev->asic->pre_page_flip((rdev), (crtc))
1690 #define radeon_page_flip(rdev, crtc, base) rdev->asic->page_flip((rdev), (crtc), (base))
1691 #define radeon_post_page_flip(rdev, crtc) rdev->asic->post_page_flip((rdev), (crtc))
1692
1693 /* Common functions */
1694 /* AGP */
1695 extern int radeon_gpu_reset(struct radeon_device *rdev);
1696 extern void radeon_agp_disable(struct radeon_device *rdev);
1697 extern int radeon_modeset_init(struct radeon_device *rdev);
1698 extern void radeon_modeset_fini(struct radeon_device *rdev);
1699 extern bool radeon_card_posted(struct radeon_device *rdev);
1700 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1701 extern void radeon_update_display_priority(struct radeon_device *rdev);
1702 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1703 extern void radeon_scratch_init(struct radeon_device *rdev);
1704 extern void radeon_wb_fini(struct radeon_device *rdev);
1705 extern int radeon_wb_init(struct radeon_device *rdev);
1706 extern void radeon_wb_disable(struct radeon_device *rdev);
1707 extern void radeon_surface_init(struct radeon_device *rdev);
1708 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1709 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1710 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1711 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1712 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1713 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1714 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1715 extern int radeon_resume_kms(struct drm_device *dev);
1716 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1717 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1718
1719 /*
1720 * vm
1721 */
1722 int radeon_vm_manager_init(struct radeon_device *rdev);
1723 void radeon_vm_manager_fini(struct radeon_device *rdev);
1724 int radeon_vm_manager_start(struct radeon_device *rdev);
1725 int radeon_vm_manager_suspend(struct radeon_device *rdev);
1726 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
1727 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
1728 int radeon_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm);
1729 void radeon_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm);
1730 int radeon_vm_bo_update_pte(struct radeon_device *rdev,
1731 struct radeon_vm *vm,
1732 struct radeon_bo *bo,
1733 struct ttm_mem_reg *mem);
1734 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
1735 struct radeon_bo *bo);
1736 int radeon_vm_bo_add(struct radeon_device *rdev,
1737 struct radeon_vm *vm,
1738 struct radeon_bo *bo,
1739 uint64_t offset,
1740 uint32_t flags);
1741 int radeon_vm_bo_rmv(struct radeon_device *rdev,
1742 struct radeon_vm *vm,
1743 struct radeon_bo *bo);
1744
1745
1746 /*
1747 * R600 vram scratch functions
1748 */
1749 int r600_vram_scratch_init(struct radeon_device *rdev);
1750 void r600_vram_scratch_fini(struct radeon_device *rdev);
1751
1752 /*
1753 * r600 functions used by radeon_encoder.c
1754 */
1755 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1756 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1757 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1758
1759 extern int ni_init_microcode(struct radeon_device *rdev);
1760 extern int ni_mc_load_microcode(struct radeon_device *rdev);
1761
1762 /* radeon_acpi.c */
1763 #if defined(CONFIG_ACPI)
1764 extern int radeon_acpi_init(struct radeon_device *rdev);
1765 #else
radeon_acpi_init(struct radeon_device * rdev)1766 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1767 #endif
1768
1769 #include "radeon_object.h"
1770
1771 #endif
1772