1 #ifndef _ASMARM_PTRACE_H_
2 #define _ASMARM_PTRACE_H_
3 /*
4 * Adapted from Linux kernel headers
5 * arch/arm/include/asm/ptrace.h
6 * arch/arm/include/uapi/asm/ptrace.h
7 *
8 * Copyright (C) 2017, Red Hat Inc, Andrew Jones <drjones@redhat.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2.
11 */
12
13 /*
14 * PSR bits
15 */
16 #define USR_MODE 0x00000010
17 #define SVC_MODE 0x00000013
18 #define FIQ_MODE 0x00000011
19 #define IRQ_MODE 0x00000012
20 #define ABT_MODE 0x00000017
21 #define HYP_MODE 0x0000001a
22 #define UND_MODE 0x0000001b
23 #define SYSTEM_MODE 0x0000001f
24 #define MODE32_BIT 0x00000010
25 #define MODE_MASK 0x0000001f
26
27 #define PSR_T_BIT 0x00000020 /* >= V4T, but not V7M */
28 #define PSR_F_BIT 0x00000040 /* >= V4, but not V7M */
29 #define PSR_I_BIT 0x00000080 /* >= V4, but not V7M */
30 #define PSR_A_BIT 0x00000100 /* >= V6, but not V7M */
31 #define PSR_E_BIT 0x00000200 /* >= V6, but not V7M */
32 #define PSR_J_BIT 0x01000000 /* >= V5J, but not V7M */
33 #define PSR_Q_BIT 0x08000000 /* >= V5E, including V7M */
34 #define PSR_V_BIT 0x10000000
35 #define PSR_C_BIT 0x20000000
36 #define PSR_Z_BIT 0x40000000
37 #define PSR_N_BIT 0x80000000
38
39 /*
40 * Groups of PSR bits
41 */
42 #define PSR_f 0xff000000 /* Flags */
43 #define PSR_s 0x00ff0000 /* Status */
44 #define PSR_x 0x0000ff00 /* Extension */
45 #define PSR_c 0x000000ff /* Control */
46
47 /*
48 * ARMv7 groups of PSR bits
49 */
50 #define APSR_MASK 0xf80f0000 /* N, Z, C, V, Q and GE flags */
51 #define PSR_ISET_MASK 0x01000010 /* ISA state (J, T) mask */
52 #define PSR_IT_MASK 0x0600fc00 /* If-Then execution state mask */
53 #define PSR_ENDIAN_MASK 0x00000200 /* Endianness state mask */
54
55 #ifndef __ASSEMBLER__
56 #include <libcflat.h>
57
58 struct pt_regs {
59 unsigned long uregs[18];
60 };
61
62 #define ARM_cpsr uregs[16]
63 #define ARM_pc uregs[15]
64 #define ARM_lr uregs[14]
65 #define ARM_sp uregs[13]
66 #define ARM_ip uregs[12]
67 #define ARM_fp uregs[11]
68 #define ARM_r10 uregs[10]
69 #define ARM_r9 uregs[9]
70 #define ARM_r8 uregs[8]
71 #define ARM_r7 uregs[7]
72 #define ARM_r6 uregs[6]
73 #define ARM_r5 uregs[5]
74 #define ARM_r4 uregs[4]
75 #define ARM_r3 uregs[3]
76 #define ARM_r2 uregs[2]
77 #define ARM_r1 uregs[1]
78 #define ARM_r0 uregs[0]
79 #define ARM_ORIG_r0 uregs[17]
80
81 #define user_mode(regs) \
82 (((regs)->ARM_cpsr & 0xf) == 0)
83
84 #define processor_mode(regs) \
85 ((regs)->ARM_cpsr & MODE_MASK)
86
87 #define interrupts_enabled(regs) \
88 (!((regs)->ARM_cpsr & PSR_I_BIT))
89
90 #define fast_interrupts_enabled(regs) \
91 (!((regs)->ARM_cpsr & PSR_F_BIT))
92
93 #define MAX_REG_OFFSET (offsetof(struct pt_regs, ARM_ORIG_r0))
94
regs_get_register(struct pt_regs * regs,unsigned int offset)95 static inline unsigned long regs_get_register(struct pt_regs *regs,
96 unsigned int offset)
97 {
98 if (offset > MAX_REG_OFFSET)
99 return 0;
100 return *(unsigned long *)((unsigned long)regs + offset);
101 }
102
103 #endif /* !__ASSEMBLER__ */
104 #endif /* _ASMARM_PTRACE_H_ */
105