1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_APMT if ACPI 5 select ACPI_CCA_REQUIRED if ACPI 6 select ACPI_GENERIC_GSI if ACPI 7 select ACPI_GTDT if ACPI 8 select ACPI_HOTPLUG_CPU if ACPI_PROCESSOR && HOTPLUG_CPU 9 select ACPI_IORT if ACPI 10 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 11 select ACPI_MCFG if (ACPI && PCI) 12 select ACPI_SPCR_TABLE if ACPI 13 select ACPI_PPTT if ACPI 14 select ARCH_HAS_DEBUG_WX 15 select ARCH_BINFMT_ELF_EXTRA_PHDRS 16 select ARCH_BINFMT_ELF_STATE 17 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION 18 select ARCH_ENABLE_MEMORY_HOTPLUG 19 select ARCH_ENABLE_MEMORY_HOTREMOVE 20 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 21 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE 22 select ARCH_HAS_CACHE_LINE_SIZE 23 select ARCH_HAS_CC_PLATFORM 24 select ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION 25 select ARCH_HAS_CURRENT_STACK_POINTER 26 select ARCH_HAS_DEBUG_VIRTUAL 27 select ARCH_HAS_DEBUG_VM_PGTABLE 28 select ARCH_HAS_DMA_OPS if XEN 29 select ARCH_HAS_DMA_PREP_COHERENT 30 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 31 select ARCH_HAS_FAST_MULTIPLIER 32 select ARCH_HAS_FORTIFY_SOURCE 33 select ARCH_HAS_GCOV_PROFILE_ALL 34 select ARCH_HAS_GIGANTIC_PAGE 35 select ARCH_HAS_KCOV 36 select ARCH_HAS_KERNEL_FPU_SUPPORT if KERNEL_MODE_NEON 37 select ARCH_HAS_KEEPINITRD 38 select ARCH_HAS_LAZY_MMU_MODE 39 select ARCH_HAS_MEMBARRIER_SYNC_CORE 40 select ARCH_HAS_MEM_ENCRYPT 41 select ARCH_SUPPORTS_MSEAL_SYSTEM_MAPPINGS 42 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS 43 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 44 select ARCH_HAS_NONLEAF_PMD_YOUNG if ARM64_HAFT 45 select ARCH_HAS_PREEMPT_LAZY 46 select ARCH_HAS_PTDUMP 47 select ARCH_HAS_PTE_SPECIAL 48 select ARCH_HAS_HW_PTE_YOUNG 49 select ARCH_HAS_SETUP_DMA_OPS 50 select ARCH_HAS_SET_DIRECT_MAP 51 select ARCH_HAS_SET_MEMORY 52 select ARCH_HAS_FORCE_DMA_UNENCRYPTED 53 select ARCH_STACKWALK 54 select ARCH_HAS_STRICT_KERNEL_RWX 55 select ARCH_HAS_STRICT_MODULE_RWX 56 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 57 select ARCH_HAS_SYNC_DMA_FOR_CPU 58 select ARCH_HAS_SYSCALL_WRAPPER 59 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 60 select ARCH_HAS_ZONE_DMA_SET if EXPERT 61 select ARCH_HAVE_ELF_PROT 62 select ARCH_HAVE_NMI_SAFE_CMPXCHG 63 select ARCH_HAVE_TRACE_MMIO_ACCESS 64 select ARCH_INLINE_READ_LOCK if !PREEMPTION 65 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION 66 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION 67 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION 68 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION 69 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION 70 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION 71 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION 72 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION 73 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION 74 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION 75 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION 76 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION 77 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION 78 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION 79 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION 80 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION 81 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION 82 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION 83 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION 84 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION 85 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION 86 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION 87 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION 88 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION 89 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION 90 select ARCH_KEEP_MEMBLOCK 91 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE 92 select ARCH_USE_CMPXCHG_LOCKREF 93 select ARCH_USE_GNU_PROPERTY 94 select ARCH_USE_MEMTEST 95 select ARCH_USE_QUEUED_RWLOCKS 96 select ARCH_USE_QUEUED_SPINLOCKS 97 select ARCH_USE_SYM_ANNOTATIONS 98 select ARCH_SUPPORTS_DEBUG_PAGEALLOC 99 select ARCH_SUPPORTS_HUGETLBFS 100 select ARCH_SUPPORTS_MEMORY_FAILURE 101 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK 102 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN 103 select ARCH_SUPPORTS_LTO_CLANG_THIN 104 select ARCH_SUPPORTS_CFI 105 select ARCH_SUPPORTS_ATOMIC_RMW 106 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 107 select ARCH_SUPPORTS_NUMA_BALANCING 108 select ARCH_SUPPORTS_PAGE_TABLE_CHECK 109 select ARCH_SUPPORTS_PER_VMA_LOCK 110 select ARCH_SUPPORTS_HUGE_PFNMAP if TRANSPARENT_HUGEPAGE 111 select ARCH_SUPPORTS_RT 112 select ARCH_SUPPORTS_SCHED_SMT 113 select ARCH_SUPPORTS_SCHED_CLUSTER 114 select ARCH_SUPPORTS_SCHED_MC 115 select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH 116 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 117 select ARCH_WANT_DEFAULT_BPF_JIT 118 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 119 select ARCH_WANT_FRAME_POINTERS 120 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 121 select ARCH_WANT_LD_ORPHAN_WARN 122 select ARCH_WANTS_EXECMEM_LATE 123 select ARCH_WANTS_NO_INSTR 124 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES 125 select ARCH_HAS_UBSAN 126 select ARM_AMBA 127 select ARM_ARCH_TIMER 128 select ARM_GIC 129 select AUDIT_ARCH_COMPAT_GENERIC 130 select ARM_GIC_V2M if PCI 131 select ARM_GIC_V3 132 select ARM_GIC_V3_ITS if PCI 133 select ARM_GIC_V5 134 select ARM_PSCI_FW 135 select BUILDTIME_TABLE_SORT 136 select CLONE_BACKWARDS 137 select COMMON_CLK 138 select CPU_PM if (SUSPEND || CPU_IDLE) 139 select CPUMASK_OFFSTACK if NR_CPUS > 256 140 select DCACHE_WORD_ACCESS 141 select HAVE_EXTRA_IPI_TRACEPOINTS 142 select DYNAMIC_FTRACE if FUNCTION_TRACER 143 select DMA_BOUNCE_UNALIGNED_KMALLOC 144 select DMA_DIRECT_REMAP 145 select EDAC_SUPPORT 146 select FRAME_POINTER 147 select FUNCTION_ALIGNMENT_4B 148 select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS 149 select GENERIC_ALLOCATOR 150 select GENERIC_ARCH_TOPOLOGY 151 select GENERIC_CLOCKEVENTS_BROADCAST 152 select GENERIC_CPU_AUTOPROBE 153 select GENERIC_CPU_CACHE_MAINTENANCE 154 select GENERIC_CPU_DEVICES 155 select GENERIC_CPU_VULNERABILITIES 156 select GENERIC_EARLY_IOREMAP 157 select GENERIC_IDLE_POLL_SETUP 158 select GENERIC_IOREMAP 159 select GENERIC_IRQ_ENTRY 160 select GENERIC_IRQ_IPI 161 select GENERIC_IRQ_KEXEC_CLEAR_VM_FORWARD 162 select GENERIC_IRQ_PROBE 163 select GENERIC_IRQ_SHOW 164 select GENERIC_IRQ_SHOW_LEVEL 165 select GENERIC_LIB_DEVMEM_IS_ALLOWED 166 select GENERIC_PCI_IOMAP 167 select GENERIC_SCHED_CLOCK 168 select GENERIC_SMP_IDLE_THREAD 169 select GENERIC_TIME_VSYSCALL 170 select GENERIC_GETTIMEOFDAY 171 select HARDIRQS_SW_RESEND 172 select HAS_IOPORT 173 select HAVE_MOVE_PMD 174 select HAVE_MOVE_PUD 175 select HAVE_PCI 176 select HAVE_ACPI_APEI if (ACPI && EFI) 177 select HAVE_ALIGNED_STRUCT_PAGE 178 select HAVE_ARCH_AUDITSYSCALL 179 select HAVE_ARCH_BITREVERSE 180 select HAVE_ARCH_COMPILER_H 181 select HAVE_ARCH_HUGE_VMALLOC 182 select HAVE_ARCH_HUGE_VMAP 183 select HAVE_ARCH_JUMP_LABEL 184 select HAVE_ARCH_JUMP_LABEL_RELATIVE 185 select HAVE_ARCH_KASAN 186 select HAVE_ARCH_KASAN_VMALLOC 187 select HAVE_ARCH_KASAN_SW_TAGS 188 select HAVE_ARCH_KASAN_HW_TAGS if ARM64_MTE 189 # Some instrumentation may be unsound, hence EXPERT 190 select HAVE_ARCH_KCSAN if EXPERT 191 select HAVE_ARCH_KFENCE 192 select HAVE_ARCH_KGDB 193 select HAVE_ARCH_KSTACK_ERASE 194 select HAVE_ARCH_MMAP_RND_BITS 195 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 196 select HAVE_ARCH_PREL32_RELOCATIONS 197 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET 198 select HAVE_ARCH_SECCOMP_FILTER 199 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 200 select HAVE_ARCH_TRACEHOOK 201 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 202 select HAVE_ARCH_VMAP_STACK 203 select HAVE_ARM_SMCCC 204 select HAVE_ASM_MODVERSIONS 205 select HAVE_EBPF_JIT 206 select HAVE_C_RECORDMCOUNT 207 select HAVE_CMPXCHG_DOUBLE 208 select HAVE_CMPXCHG_LOCAL 209 select HAVE_CONTEXT_TRACKING_USER 210 select HAVE_DEBUG_KMEMLEAK 211 select HAVE_DMA_CONTIGUOUS 212 select HAVE_DYNAMIC_FTRACE 213 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ 214 if (GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS || \ 215 CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS) 216 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \ 217 if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS 218 select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \ 219 if (DYNAMIC_FTRACE_WITH_ARGS && !CFI && \ 220 (CC_IS_CLANG || !CC_OPTIMIZE_FOR_SIZE)) 221 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ 222 if DYNAMIC_FTRACE_WITH_ARGS 223 select HAVE_SAMPLE_FTRACE_DIRECT 224 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI 225 select HAVE_BUILDTIME_MCOUNT_SORT 226 select HAVE_EFFICIENT_UNALIGNED_ACCESS 227 select HAVE_GUP_FAST 228 select HAVE_FTRACE_GRAPH_FUNC 229 select HAVE_FUNCTION_TRACER 230 select HAVE_FUNCTION_ERROR_INJECTION 231 select HAVE_FUNCTION_GRAPH_FREGS 232 select HAVE_FUNCTION_GRAPH_TRACER 233 select HAVE_GCC_PLUGINS 234 select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && \ 235 HW_PERF_EVENTS && HAVE_PERF_EVENTS_NMI 236 select HAVE_HW_BREAKPOINT if PERF_EVENTS 237 select HAVE_IOREMAP_PROT 238 select HAVE_IRQ_TIME_ACCOUNTING 239 select HAVE_LIVEPATCH 240 select HAVE_MOD_ARCH_SPECIFIC 241 select HAVE_NMI 242 select HAVE_PERF_EVENTS 243 select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI 244 select HAVE_PERF_REGS 245 select HAVE_PERF_USER_STACK_DUMP 246 select HAVE_PREEMPT_DYNAMIC_KEY 247 select HAVE_REGS_AND_STACK_ACCESS_API 248 select HAVE_RELIABLE_STACKTRACE 249 select HAVE_POSIX_CPU_TIMERS_TASK_WORK 250 select HAVE_FUNCTION_ARG_ACCESS_API 251 select MMU_GATHER_RCU_TABLE_FREE 252 select HAVE_RSEQ 253 select HAVE_RUST if RUSTC_SUPPORTS_ARM64 254 select HAVE_STACKPROTECTOR 255 select HAVE_STATIC_CALL if CFI 256 select HAVE_SYSCALL_TRACEPOINTS 257 select HAVE_KPROBES 258 select HAVE_KRETPROBES 259 select HAVE_GENERIC_VDSO 260 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 261 select HOTPLUG_SMT if HOTPLUG_CPU 262 select IRQ_DOMAIN 263 select IRQ_FORCED_THREADING 264 select JUMP_LABEL 265 select KASAN_VMALLOC if KASAN 266 select LOCK_MM_AND_FIND_VMA 267 select MODULES_USE_ELF_RELA 268 select NEED_DMA_MAP_STATE 269 select NEED_SG_DMA_LENGTH 270 select OF 271 select OF_EARLY_FLATTREE 272 select PCI_DOMAINS_GENERIC if PCI 273 select PCI_ECAM if (ACPI && PCI) 274 select PCI_SYSCALL if PCI 275 select POWER_RESET 276 select POWER_SUPPLY 277 select SPARSE_IRQ 278 select SWIOTLB 279 select SYSCTL_EXCEPTION_TRACE 280 select THREAD_INFO_IN_TASK 281 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD 282 select HAVE_ARCH_USERFAULTFD_WP if USERFAULTFD 283 select TRACE_IRQFLAGS_SUPPORT 284 select TRACE_IRQFLAGS_NMI_SUPPORT 285 select HAVE_SOFTIRQ_ON_OWN_STACK 286 select USER_STACKTRACE_SUPPORT 287 select VDSO_GETRANDOM 288 select VMAP_STACK 289 help 290 ARM 64-bit (AArch64) Linux support. 291 292config RUSTC_SUPPORTS_ARM64 293 def_bool y 294 depends on CPU_LITTLE_ENDIAN 295 296config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 297 def_bool CC_IS_CLANG 298 # https://github.com/ClangBuiltLinux/linux/issues/1507 299 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600)) 300 301config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 302 def_bool CC_IS_GCC 303 depends on $(cc-option,-fpatchable-function-entry=2) 304 305config 64BIT 306 def_bool y 307 308config MMU 309 def_bool y 310 311config ARM64_CONT_PTE_SHIFT 312 int 313 default 5 if PAGE_SIZE_64KB 314 default 7 if PAGE_SIZE_16KB 315 default 4 316 317config ARM64_CONT_PMD_SHIFT 318 int 319 default 5 if PAGE_SIZE_64KB 320 default 5 if PAGE_SIZE_16KB 321 default 4 322 323config ARCH_MMAP_RND_BITS_MIN 324 default 14 if PAGE_SIZE_64KB 325 default 16 if PAGE_SIZE_16KB 326 default 18 327 328# max bits determined by the following formula: 329# VA_BITS - PTDESC_TABLE_SHIFT 330config ARCH_MMAP_RND_BITS_MAX 331 default 19 if ARM64_VA_BITS=36 332 default 24 if ARM64_VA_BITS=39 333 default 27 if ARM64_VA_BITS=42 334 default 30 if ARM64_VA_BITS=47 335 default 29 if (ARM64_VA_BITS=48 || ARM64_VA_BITS=52) && ARM64_64K_PAGES 336 default 31 if (ARM64_VA_BITS=48 || ARM64_VA_BITS=52) && ARM64_16K_PAGES 337 default 33 if (ARM64_VA_BITS=48 || ARM64_VA_BITS=52) 338 default 14 if ARM64_64K_PAGES 339 default 16 if ARM64_16K_PAGES 340 default 18 341 342config ARCH_MMAP_RND_COMPAT_BITS_MIN 343 default 7 if ARM64_64K_PAGES 344 default 9 if ARM64_16K_PAGES 345 default 11 346 347config ARCH_MMAP_RND_COMPAT_BITS_MAX 348 default 16 349 350config NO_IOPORT_MAP 351 def_bool y if !PCI 352 353config STACKTRACE_SUPPORT 354 def_bool y 355 356config ILLEGAL_POINTER_VALUE 357 hex 358 default 0xdead000000000000 359 360config LOCKDEP_SUPPORT 361 def_bool y 362 363config GENERIC_BUG 364 def_bool y 365 depends on BUG 366 367config GENERIC_BUG_RELATIVE_POINTERS 368 def_bool y 369 depends on GENERIC_BUG 370 371config GENERIC_HWEIGHT 372 def_bool y 373 374config GENERIC_CSUM 375 def_bool y 376 377config GENERIC_CALIBRATE_DELAY 378 def_bool y 379 380config SMP 381 def_bool y 382 383config KERNEL_MODE_NEON 384 def_bool y 385 386config FIX_EARLYCON_MEM 387 def_bool y 388 389config PGTABLE_LEVELS 390 int 391 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 392 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 393 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 394 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 395 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 396 default 4 if ARM64_16K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 397 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 398 default 5 if ARM64_4K_PAGES && ARM64_VA_BITS_52 399 400config ARCH_SUPPORTS_UPROBES 401 def_bool y 402 403config ARCH_PROC_KCORE_TEXT 404 def_bool y 405 406config BROKEN_GAS_INST 407 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 408 409config BUILTIN_RETURN_ADDRESS_STRIPS_PAC 410 bool 411 # Clang's __builtin_return_address() strips the PAC since 12.0.0 412 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2 413 default y if CC_IS_CLANG 414 # GCC's __builtin_return_address() strips the PAC since 11.1.0, 415 # and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier 416 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891 417 default y if CC_IS_GCC && (GCC_VERSION >= 110100) 418 default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000) 419 default y if CC_IS_GCC && (GCC_VERSION >= 90400) && (GCC_VERSION < 100000) 420 default y if CC_IS_GCC && (GCC_VERSION >= 80500) && (GCC_VERSION < 90000) 421 default n 422 423config KASAN_SHADOW_OFFSET 424 hex 425 depends on KASAN_GENERIC || KASAN_SW_TAGS 426 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && !KASAN_SW_TAGS 427 default 0xdfffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && !KASAN_SW_TAGS 428 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 429 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 430 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 431 default 0xefff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && KASAN_SW_TAGS 432 default 0xefffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && KASAN_SW_TAGS 433 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 434 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 435 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 436 default 0xffffffffffffffff 437 438config UNWIND_TABLES 439 bool 440 441source "arch/arm64/Kconfig.platforms" 442 443menu "Kernel Features" 444 445menu "ARM errata workarounds via the alternatives framework" 446 447config AMPERE_ERRATUM_AC03_CPU_38 448 bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and Translation Control Registers do not follow RES0 semantics" 449 default y 450 help 451 This option adds an alternative code sequence to work around Ampere 452 errata AC03_CPU_38 and AC04_CPU_10 on AmpereOne. 453 454 The affected design reports FEAT_HAFDBS as not implemented in 455 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0 456 as required by the architecture. The unadvertised HAFDBS 457 implementation suffers from an additional erratum where hardware 458 A/D updates can occur after a PTE has been marked invalid. 459 460 The workaround forces KVM to explicitly set VTCR_EL2.HA to 0, 461 which avoids enabling unadvertised hardware Access Flag management 462 at stage-2. 463 464 If unsure, say Y. 465 466config AMPERE_ERRATUM_AC04_CPU_23 467 bool "AmpereOne: AC04_CPU_23: Failure to synchronize writes to HCR_EL2 may corrupt address translations." 468 default y 469 help 470 This option adds an alternative code sequence to work around Ampere 471 errata AC04_CPU_23 on AmpereOne. 472 473 Updates to HCR_EL2 can rarely corrupt simultaneous translations for 474 data addresses initiated by load/store instructions. Only 475 instruction initiated translations are vulnerable, not translations 476 from prefetches for example. A DSB before the store to HCR_EL2 is 477 sufficient to prevent older instructions from hitting the window 478 for corruption, and an ISB after is sufficient to prevent younger 479 instructions from hitting the window for corruption. 480 481 If unsure, say Y. 482 483config ARM64_WORKAROUND_CLEAN_CACHE 484 bool 485 486config ARM64_ERRATUM_826319 487 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 488 default y 489 select ARM64_WORKAROUND_CLEAN_CACHE 490 help 491 This option adds an alternative code sequence to work around ARM 492 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 493 AXI master interface and an L2 cache. 494 495 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 496 and is unable to accept a certain write via this interface, it will 497 not progress on read data presented on the read data channel and the 498 system can deadlock. 499 500 The workaround promotes data cache clean instructions to 501 data cache clean-and-invalidate. 502 Please note that this does not necessarily enable the workaround, 503 as it depends on the alternative framework, which will only patch 504 the kernel if an affected CPU is detected. 505 506 If unsure, say Y. 507 508config ARM64_ERRATUM_827319 509 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 510 default y 511 select ARM64_WORKAROUND_CLEAN_CACHE 512 help 513 This option adds an alternative code sequence to work around ARM 514 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 515 master interface and an L2 cache. 516 517 Under certain conditions this erratum can cause a clean line eviction 518 to occur at the same time as another transaction to the same address 519 on the AMBA 5 CHI interface, which can cause data corruption if the 520 interconnect reorders the two transactions. 521 522 The workaround promotes data cache clean instructions to 523 data cache clean-and-invalidate. 524 Please note that this does not necessarily enable the workaround, 525 as it depends on the alternative framework, which will only patch 526 the kernel if an affected CPU is detected. 527 528 If unsure, say Y. 529 530config ARM64_ERRATUM_824069 531 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 532 default y 533 select ARM64_WORKAROUND_CLEAN_CACHE 534 help 535 This option adds an alternative code sequence to work around ARM 536 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 537 to a coherent interconnect. 538 539 If a Cortex-A53 processor is executing a store or prefetch for 540 write instruction at the same time as a processor in another 541 cluster is executing a cache maintenance operation to the same 542 address, then this erratum might cause a clean cache line to be 543 incorrectly marked as dirty. 544 545 The workaround promotes data cache clean instructions to 546 data cache clean-and-invalidate. 547 Please note that this option does not necessarily enable the 548 workaround, as it depends on the alternative framework, which will 549 only patch the kernel if an affected CPU is detected. 550 551 If unsure, say Y. 552 553config ARM64_ERRATUM_819472 554 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 555 default y 556 select ARM64_WORKAROUND_CLEAN_CACHE 557 help 558 This option adds an alternative code sequence to work around ARM 559 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 560 present when it is connected to a coherent interconnect. 561 562 If the processor is executing a load and store exclusive sequence at 563 the same time as a processor in another cluster is executing a cache 564 maintenance operation to the same address, then this erratum might 565 cause data corruption. 566 567 The workaround promotes data cache clean instructions to 568 data cache clean-and-invalidate. 569 Please note that this does not necessarily enable the workaround, 570 as it depends on the alternative framework, which will only patch 571 the kernel if an affected CPU is detected. 572 573 If unsure, say Y. 574 575config ARM64_ERRATUM_832075 576 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 577 default y 578 help 579 This option adds an alternative code sequence to work around ARM 580 erratum 832075 on Cortex-A57 parts up to r1p2. 581 582 Affected Cortex-A57 parts might deadlock when exclusive load/store 583 instructions to Write-Back memory are mixed with Device loads. 584 585 The workaround is to promote device loads to use Load-Acquire 586 semantics. 587 Please note that this does not necessarily enable the workaround, 588 as it depends on the alternative framework, which will only patch 589 the kernel if an affected CPU is detected. 590 591 If unsure, say Y. 592 593config ARM64_ERRATUM_834220 594 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault (rare)" 595 depends on KVM 596 help 597 This option adds an alternative code sequence to work around ARM 598 erratum 834220 on Cortex-A57 parts up to r1p2. 599 600 Affected Cortex-A57 parts might report a Stage 2 translation 601 fault as the result of a Stage 1 fault for load crossing a 602 page boundary when there is a permission or device memory 603 alignment fault at Stage 1 and a translation fault at Stage 2. 604 605 The workaround is to verify that the Stage 1 translation 606 doesn't generate a fault before handling the Stage 2 fault. 607 Please note that this does not necessarily enable the workaround, 608 as it depends on the alternative framework, which will only patch 609 the kernel if an affected CPU is detected. 610 611 If unsure, say N. 612 613config ARM64_ERRATUM_1742098 614 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence" 615 depends on COMPAT 616 default y 617 help 618 This option removes the AES hwcap for aarch32 user-space to 619 workaround erratum 1742098 on Cortex-A57 and Cortex-A72. 620 621 Affected parts may corrupt the AES state if an interrupt is 622 taken between a pair of AES instructions. These instructions 623 are only present if the cryptography extensions are present. 624 All software should have a fallback implementation for CPUs 625 that don't implement the cryptography extensions. 626 627 If unsure, say Y. 628 629config ARM64_ERRATUM_845719 630 bool "Cortex-A53: 845719: a load might read incorrect data" 631 depends on COMPAT 632 default y 633 help 634 This option adds an alternative code sequence to work around ARM 635 erratum 845719 on Cortex-A53 parts up to r0p4. 636 637 When running a compat (AArch32) userspace on an affected Cortex-A53 638 part, a load at EL0 from a virtual address that matches the bottom 32 639 bits of the virtual address used by a recent load at (AArch64) EL1 640 might return incorrect data. 641 642 The workaround is to write the contextidr_el1 register on exception 643 return to a 32-bit task. 644 Please note that this does not necessarily enable the workaround, 645 as it depends on the alternative framework, which will only patch 646 the kernel if an affected CPU is detected. 647 648 If unsure, say Y. 649 650config ARM64_ERRATUM_843419 651 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 652 default y 653 help 654 This option links the kernel with '--fix-cortex-a53-843419' and 655 enables PLT support to replace certain ADRP instructions, which can 656 cause subsequent memory accesses to use an incorrect address on 657 Cortex-A53 parts up to r0p4. 658 659 If unsure, say Y. 660 661config ARM64_ERRATUM_1024718 662 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 663 default y 664 help 665 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 666 667 Affected Cortex-A55 cores (all revisions) could cause incorrect 668 update of the hardware dirty bit when the DBM/AP bits are updated 669 without a break-before-make. The workaround is to disable the usage 670 of hardware DBM locally on the affected cores. CPUs not affected by 671 this erratum will continue to use the feature. 672 673 If unsure, say Y. 674 675config ARM64_ERRATUM_1418040 676 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 677 default y 678 depends on COMPAT 679 help 680 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 681 errata 1188873 and 1418040. 682 683 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 684 cause register corruption when accessing the timer registers 685 from AArch32 userspace. 686 687 If unsure, say Y. 688 689config ARM64_WORKAROUND_SPECULATIVE_AT 690 bool 691 692config ARM64_ERRATUM_1165522 693 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 694 default y 695 select ARM64_WORKAROUND_SPECULATIVE_AT 696 help 697 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 698 699 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 700 corrupted TLBs by speculating an AT instruction during a guest 701 context switch. 702 703 If unsure, say Y. 704 705config ARM64_ERRATUM_1319367 706 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 707 default y 708 select ARM64_WORKAROUND_SPECULATIVE_AT 709 help 710 This option adds work arounds for ARM Cortex-A57 erratum 1319537 711 and A72 erratum 1319367 712 713 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 714 speculating an AT instruction during a guest context switch. 715 716 If unsure, say Y. 717 718config ARM64_ERRATUM_1530923 719 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 720 default y 721 select ARM64_WORKAROUND_SPECULATIVE_AT 722 help 723 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 724 725 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 726 corrupted TLBs by speculating an AT instruction during a guest 727 context switch. 728 729 If unsure, say Y. 730 731config ARM64_WORKAROUND_REPEAT_TLBI 732 bool 733 734config ARM64_ERRATUM_2441007 735 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 736 select ARM64_WORKAROUND_REPEAT_TLBI 737 help 738 This option adds a workaround for ARM Cortex-A55 erratum #2441007. 739 740 Under very rare circumstances, affected Cortex-A55 CPUs 741 may not handle a race between a break-before-make sequence on one 742 CPU, and another CPU accessing the same page. This could allow a 743 store to a page that has been unmapped. 744 745 Work around this by adding the affected CPUs to the list that needs 746 TLB sequences to be done twice. 747 748 If unsure, say N. 749 750config ARM64_ERRATUM_1286807 751 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation (rare)" 752 select ARM64_WORKAROUND_REPEAT_TLBI 753 help 754 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 755 756 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 757 address for a cacheable mapping of a location is being 758 accessed by a core while another core is remapping the virtual 759 address to a new physical page using the recommended 760 break-before-make sequence, then under very rare circumstances 761 TLBI+DSB completes before a read using the translation being 762 invalidated has been observed by other observers. The 763 workaround repeats the TLBI+DSB operation. 764 765 If unsure, say N. 766 767config ARM64_ERRATUM_1463225 768 bool "Cortex-A76: Software Step might prevent interrupt recognition" 769 default y 770 help 771 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 772 773 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 774 of a system call instruction (SVC) can prevent recognition of 775 subsequent interrupts when software stepping is disabled in the 776 exception handler of the system call and either kernel debugging 777 is enabled or VHE is in use. 778 779 Work around the erratum by triggering a dummy step exception 780 when handling a system call from a task that is being stepped 781 in a VHE configuration of the kernel. 782 783 If unsure, say Y. 784 785config ARM64_ERRATUM_1542419 786 bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)" 787 help 788 This option adds a workaround for ARM Neoverse-N1 erratum 789 1542419. 790 791 Affected Neoverse-N1 cores could execute a stale instruction when 792 modified by another CPU. The workaround depends on a firmware 793 counterpart. 794 795 Workaround the issue by hiding the DIC feature from EL0. This 796 forces user-space to perform cache maintenance. 797 798 If unsure, say N. 799 800config ARM64_ERRATUM_1508412 801 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" 802 default y 803 help 804 This option adds a workaround for Arm Cortex-A77 erratum 1508412. 805 806 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence 807 of a store-exclusive or read of PAR_EL1 and a load with device or 808 non-cacheable memory attributes. The workaround depends on a firmware 809 counterpart. 810 811 KVM guests must also have the workaround implemented or they can 812 deadlock the system. 813 814 Work around the issue by inserting DMB SY barriers around PAR_EL1 815 register reads and warning KVM users. The DMB barrier is sufficient 816 to prevent a speculative PAR_EL1 read. 817 818 If unsure, say Y. 819 820config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 821 bool 822 823config ARM64_ERRATUM_2051678 824 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit" 825 default y 826 help 827 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678. 828 Affected Cortex-A510 might not respect the ordering rules for 829 hardware update of the page table's dirty bit. The workaround 830 is to not enable the feature on affected CPUs. 831 832 If unsure, say Y. 833 834config ARM64_ERRATUM_2077057 835 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2" 836 default y 837 help 838 This option adds the workaround for ARM Cortex-A510 erratum 2077057. 839 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is 840 expected, but a Pointer Authentication trap is taken instead. The 841 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow 842 EL1 to cause a return to EL2 with a guest controlled ELR_EL2. 843 844 This can only happen when EL2 is stepping EL1. 845 846 When these conditions occur, the SPSR_EL2 value is unchanged from the 847 previous guest entry, and can be restored from the in-memory copy. 848 849 If unsure, say Y. 850 851config ARM64_ERRATUM_2658417 852 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result" 853 default y 854 help 855 This option adds the workaround for ARM Cortex-A510 erratum 2658417. 856 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for 857 BFMMLA or VMMLA instructions in rare circumstances when a pair of 858 A510 CPUs are using shared neon hardware. As the sharing is not 859 discoverable by the kernel, hide the BF16 HWCAP to indicate that 860 user-space should not be using these instructions. 861 862 If unsure, say Y. 863 864config ARM64_ERRATUM_2119858 865 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode" 866 default y 867 depends on CORESIGHT_TRBE 868 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 869 help 870 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858. 871 872 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace 873 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 874 the event of a WRAP event. 875 876 Work around the issue by always making sure we move the TRBPTR_EL1 by 877 256 bytes before enabling the buffer and filling the first 256 bytes of 878 the buffer with ETM ignore packets upon disabling. 879 880 If unsure, say Y. 881 882config ARM64_ERRATUM_2139208 883 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" 884 default y 885 depends on CORESIGHT_TRBE 886 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 887 help 888 This option adds the workaround for ARM Neoverse-N2 erratum 2139208. 889 890 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace 891 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 892 the event of a WRAP event. 893 894 Work around the issue by always making sure we move the TRBPTR_EL1 by 895 256 bytes before enabling the buffer and filling the first 256 bytes of 896 the buffer with ETM ignore packets upon disabling. 897 898 If unsure, say Y. 899 900config ARM64_WORKAROUND_TSB_FLUSH_FAILURE 901 bool 902 903config ARM64_ERRATUM_2054223 904 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" 905 default y 906 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 907 help 908 Enable workaround for ARM Cortex-A710 erratum 2054223 909 910 Affected cores may fail to flush the trace data on a TSB instruction, when 911 the PE is in trace prohibited state. This will cause losing a few bytes 912 of the trace cached. 913 914 Workaround is to issue two TSB consecutively on affected cores. 915 916 If unsure, say Y. 917 918config ARM64_ERRATUM_2067961 919 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" 920 default y 921 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 922 help 923 Enable workaround for ARM Neoverse-N2 erratum 2067961 924 925 Affected cores may fail to flush the trace data on a TSB instruction, when 926 the PE is in trace prohibited state. This will cause losing a few bytes 927 of the trace cached. 928 929 Workaround is to issue two TSB consecutively on affected cores. 930 931 If unsure, say Y. 932 933config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 934 bool 935 936config ARM64_ERRATUM_2253138 937 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" 938 depends on CORESIGHT_TRBE 939 default y 940 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 941 help 942 This option adds the workaround for ARM Neoverse-N2 erratum 2253138. 943 944 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved 945 for TRBE. Under some conditions, the TRBE might generate a write to the next 946 virtually addressed page following the last page of the TRBE address space 947 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 948 949 Work around this in the driver by always making sure that there is a 950 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 951 952 If unsure, say Y. 953 954config ARM64_ERRATUM_2224489 955 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range" 956 depends on CORESIGHT_TRBE 957 default y 958 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 959 help 960 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489. 961 962 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved 963 for TRBE. Under some conditions, the TRBE might generate a write to the next 964 virtually addressed page following the last page of the TRBE address space 965 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 966 967 Work around this in the driver by always making sure that there is a 968 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 969 970 If unsure, say Y. 971 972config ARM64_ERRATUM_2441009 973 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 974 select ARM64_WORKAROUND_REPEAT_TLBI 975 help 976 This option adds a workaround for ARM Cortex-A510 erratum #2441009. 977 978 Under very rare circumstances, affected Cortex-A510 CPUs 979 may not handle a race between a break-before-make sequence on one 980 CPU, and another CPU accessing the same page. This could allow a 981 store to a page that has been unmapped. 982 983 Work around this by adding the affected CPUs to the list that needs 984 TLB sequences to be done twice. 985 986 If unsure, say N. 987 988config ARM64_ERRATUM_2064142 989 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" 990 depends on CORESIGHT_TRBE 991 default y 992 help 993 This option adds the workaround for ARM Cortex-A510 erratum 2064142. 994 995 Affected Cortex-A510 core might fail to write into system registers after the 996 TRBE has been disabled. Under some conditions after the TRBE has been disabled 997 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, 998 and TRBTRG_EL1 will be ignored and will not be effected. 999 1000 Work around this in the driver by executing TSB CSYNC and DSB after collection 1001 is stopped and before performing a system register write to one of the affected 1002 registers. 1003 1004 If unsure, say Y. 1005 1006config ARM64_ERRATUM_2038923 1007 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" 1008 depends on CORESIGHT_TRBE 1009 default y 1010 help 1011 This option adds the workaround for ARM Cortex-A510 erratum 2038923. 1012 1013 Affected Cortex-A510 core might cause an inconsistent view on whether trace is 1014 prohibited within the CPU. As a result, the trace buffer or trace buffer state 1015 might be corrupted. This happens after TRBE buffer has been enabled by setting 1016 TRBLIMITR_EL1.E, followed by just a single context synchronization event before 1017 execution changes from a context, in which trace is prohibited to one where it 1018 isn't, or vice versa. In these mentioned conditions, the view of whether trace 1019 is prohibited is inconsistent between parts of the CPU, and the trace buffer or 1020 the trace buffer state might be corrupted. 1021 1022 Work around this in the driver by preventing an inconsistent view of whether the 1023 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a 1024 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or 1025 two ISB instructions if no ERET is to take place. 1026 1027 If unsure, say Y. 1028 1029config ARM64_ERRATUM_1902691 1030 bool "Cortex-A510: 1902691: workaround TRBE trace corruption" 1031 depends on CORESIGHT_TRBE 1032 default y 1033 help 1034 This option adds the workaround for ARM Cortex-A510 erratum 1902691. 1035 1036 Affected Cortex-A510 core might cause trace data corruption, when being written 1037 into the memory. Effectively TRBE is broken and hence cannot be used to capture 1038 trace data. 1039 1040 Work around this problem in the driver by just preventing TRBE initialization on 1041 affected cpus. The firmware must have disabled the access to TRBE for the kernel 1042 on such implementations. This will cover the kernel for any firmware that doesn't 1043 do this already. 1044 1045 If unsure, say Y. 1046 1047config ARM64_ERRATUM_2457168 1048 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" 1049 depends on ARM64_AMU_EXTN 1050 default y 1051 help 1052 This option adds the workaround for ARM Cortex-A510 erratum 2457168. 1053 1054 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate 1055 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments 1056 incorrectly giving a significantly higher output value. 1057 1058 Work around this problem by returning 0 when reading the affected counter in 1059 key locations that results in disabling all users of this counter. This effect 1060 is the same to firmware disabling affected counters. 1061 1062 If unsure, say Y. 1063 1064config ARM64_ERRATUM_2645198 1065 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption" 1066 default y 1067 help 1068 This option adds the workaround for ARM Cortex-A715 erratum 2645198. 1069 1070 If a Cortex-A715 cpu sees a page mapping permissions change from executable 1071 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the 1072 next instruction abort caused by permission fault. 1073 1074 Only user-space does executable to non-executable permission transition via 1075 mprotect() system call. Workaround the problem by doing a break-before-make 1076 TLB invalidation, for all changes to executable user space mappings. 1077 1078 If unsure, say Y. 1079 1080config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1081 bool 1082 1083config ARM64_ERRATUM_2966298 1084 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load" 1085 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1086 default y 1087 help 1088 This option adds the workaround for ARM Cortex-A520 erratum 2966298. 1089 1090 On an affected Cortex-A520 core, a speculatively executed unprivileged 1091 load might leak data from a privileged level via a cache side channel. 1092 1093 Work around this problem by executing a TLBI before returning to EL0. 1094 1095 If unsure, say Y. 1096 1097config ARM64_ERRATUM_3117295 1098 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load" 1099 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1100 default y 1101 help 1102 This option adds the workaround for ARM Cortex-A510 erratum 3117295. 1103 1104 On an affected Cortex-A510 core, a speculatively executed unprivileged 1105 load might leak data from a privileged level via a cache side channel. 1106 1107 Work around this problem by executing a TLBI before returning to EL0. 1108 1109 If unsure, say Y. 1110 1111config ARM64_ERRATUM_3194386 1112 bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing" 1113 default y 1114 help 1115 This option adds the workaround for the following errata: 1116 1117 * ARM Cortex-A76 erratum 3324349 1118 * ARM Cortex-A77 erratum 3324348 1119 * ARM Cortex-A78 erratum 3324344 1120 * ARM Cortex-A78C erratum 3324346 1121 * ARM Cortex-A78C erratum 3324347 1122 * ARM Cortex-A710 erratam 3324338 1123 * ARM Cortex-A715 errartum 3456084 1124 * ARM Cortex-A720 erratum 3456091 1125 * ARM Cortex-A725 erratum 3456106 1126 * ARM Cortex-X1 erratum 3324344 1127 * ARM Cortex-X1C erratum 3324346 1128 * ARM Cortex-X2 erratum 3324338 1129 * ARM Cortex-X3 erratum 3324335 1130 * ARM Cortex-X4 erratum 3194386 1131 * ARM Cortex-X925 erratum 3324334 1132 * ARM Neoverse-N1 erratum 3324349 1133 * ARM Neoverse N2 erratum 3324339 1134 * ARM Neoverse-N3 erratum 3456111 1135 * ARM Neoverse-V1 erratum 3324341 1136 * ARM Neoverse V2 erratum 3324336 1137 * ARM Neoverse-V3 erratum 3312417 1138 * ARM Neoverse-V3AE erratum 3312417 1139 1140 On affected cores "MSR SSBS, #0" instructions may not affect 1141 subsequent speculative instructions, which may permit unexepected 1142 speculative store bypassing. 1143 1144 Work around this problem by placing a Speculation Barrier (SB) or 1145 Instruction Synchronization Barrier (ISB) after kernel changes to 1146 SSBS. The presence of the SSBS special-purpose register is hidden 1147 from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace 1148 will use the PR_SPEC_STORE_BYPASS prctl to change SSBS. 1149 1150 If unsure, say Y. 1151 1152config ARM64_ERRATUM_4311569 1153 bool "SI L1: 4311569: workaround for premature CMO completion erratum" 1154 default y 1155 help 1156 This option adds the workaround for ARM SI L1 erratum 4311569. 1157 1158 The erratum of SI L1 can cause an early response to a combined write 1159 and cache maintenance operation (WR+CMO) before the operation is fully 1160 completed to the Point of Serialization (POS). 1161 This can result in a non-I/O coherent agent observing stale data, 1162 potentially leading to system instability or incorrect behavior. 1163 1164 Enabling this option implements a software workaround by inserting a 1165 second loop of Cache Maintenance Operation (CMO) immediately following the 1166 end of function to do CMOs. This ensures that the data is correctly serialized 1167 before the buffer is handed off to a non-coherent agent. 1168 1169 If unsure, say Y. 1170 1171config CAVIUM_ERRATUM_22375 1172 bool "Cavium erratum 22375, 24313" 1173 default y 1174 help 1175 Enable workaround for errata 22375 and 24313. 1176 1177 This implements two gicv3-its errata workarounds for ThunderX. Both 1178 with a small impact affecting only ITS table allocation. 1179 1180 erratum 22375: only alloc 8MB table size 1181 erratum 24313: ignore memory access type 1182 1183 The fixes are in ITS initialization and basically ignore memory access 1184 type and table size provided by the TYPER and BASER registers. 1185 1186 If unsure, say Y. 1187 1188config CAVIUM_ERRATUM_23144 1189 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 1190 depends on NUMA 1191 default y 1192 help 1193 ITS SYNC command hang for cross node io and collections/cpu mapping. 1194 1195 If unsure, say Y. 1196 1197config CAVIUM_ERRATUM_23154 1198 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation" 1199 default y 1200 help 1201 The ThunderX GICv3 implementation requires a modified version for 1202 reading the IAR status to ensure data synchronization 1203 (access to icc_iar1_el1 is not sync'ed before and after). 1204 1205 It also suffers from erratum 38545 (also present on Marvell's 1206 OcteonTX and OcteonTX2), resulting in deactivated interrupts being 1207 spuriously presented to the CPU interface. 1208 1209 If unsure, say Y. 1210 1211config CAVIUM_ERRATUM_27456 1212 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 1213 default y 1214 help 1215 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 1216 instructions may cause the icache to become corrupted if it 1217 contains data for a non-current ASID. The fix is to 1218 invalidate the icache when changing the mm context. 1219 1220 If unsure, say Y. 1221 1222config CAVIUM_ERRATUM_30115 1223 bool "Cavium erratum 30115: Guest may disable interrupts in host" 1224 default y 1225 help 1226 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 1227 1.2, and T83 Pass 1.0, KVM guest execution may disable 1228 interrupts in host. Trapping both GICv3 group-0 and group-1 1229 accesses sidesteps the issue. 1230 1231 If unsure, say Y. 1232 1233config CAVIUM_TX2_ERRATUM_219 1234 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 1235 default y 1236 help 1237 On Cavium ThunderX2, a load, store or prefetch instruction between a 1238 TTBR update and the corresponding context synchronizing operation can 1239 cause a spurious Data Abort to be delivered to any hardware thread in 1240 the CPU core. 1241 1242 Work around the issue by avoiding the problematic code sequence and 1243 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 1244 trap handler performs the corresponding register access, skips the 1245 instruction and ensures context synchronization by virtue of the 1246 exception return. 1247 1248 If unsure, say Y. 1249 1250config FUJITSU_ERRATUM_010001 1251 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 1252 default y 1253 help 1254 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 1255 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 1256 accesses may cause undefined fault (Data abort, DFSC=0b111111). 1257 This fault occurs under a specific hardware condition when a 1258 load/store instruction performs an address translation using: 1259 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 1260 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 1261 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 1262 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 1263 1264 The workaround is to ensure these bits are clear in TCR_ELx. 1265 The workaround only affects the Fujitsu-A64FX. 1266 1267 If unsure, say Y. 1268 1269config HISILICON_ERRATUM_161600802 1270 bool "Hip07 161600802: Erroneous redistributor VLPI base" 1271 default y 1272 help 1273 The HiSilicon Hip07 SoC uses the wrong redistributor base 1274 when issued ITS commands such as VMOVP and VMAPP, and requires 1275 a 128kB offset to be applied to the target address in this commands. 1276 1277 If unsure, say Y. 1278 1279config HISILICON_ERRATUM_162100801 1280 bool "Hip09 162100801 erratum support" 1281 default y 1282 help 1283 When enabling GICv4.1 in hip09, VMAPP will fail to clear some caches 1284 during unmapping operation, which will cause some vSGIs lost. 1285 To fix the issue, invalidate related vPE cache through GICR_INVALLR 1286 after VMOVP. 1287 1288 If unsure, say Y. 1289 1290config QCOM_FALKOR_ERRATUM_1003 1291 bool "Falkor E1003: Incorrect translation due to ASID change" 1292 default y 1293 help 1294 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 1295 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 1296 in TTBR1_EL1, this situation only occurs in the entry trampoline and 1297 then only for entries in the walk cache, since the leaf translation 1298 is unchanged. Work around the erratum by invalidating the walk cache 1299 entries for the trampoline before entering the kernel proper. 1300 1301config QCOM_FALKOR_ERRATUM_1009 1302 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 1303 default y 1304 select ARM64_WORKAROUND_REPEAT_TLBI 1305 help 1306 On Falkor v1, the CPU may prematurely complete a DSB following a 1307 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 1308 one more time to fix the issue. 1309 1310 If unsure, say Y. 1311 1312config QCOM_QDF2400_ERRATUM_0065 1313 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 1314 default y 1315 help 1316 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 1317 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 1318 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 1319 1320 If unsure, say Y. 1321 1322config QCOM_FALKOR_ERRATUM_E1041 1323 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 1324 default y 1325 help 1326 Falkor CPU may speculatively fetch instructions from an improper 1327 memory location when MMU translation is changed from SCTLR_ELn[M]=1 1328 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 1329 1330 If unsure, say Y. 1331 1332config NVIDIA_CARMEL_CNP_ERRATUM 1333 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" 1334 default y 1335 help 1336 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not 1337 invalidate shared TLB entries installed by a different core, as it would 1338 on standard ARM cores. 1339 1340 If unsure, say Y. 1341 1342config ROCKCHIP_ERRATUM_3568002 1343 bool "Rockchip 3568002: GIC600 can not access physical addresses higher than 4GB" 1344 default y 1345 help 1346 The Rockchip RK3566 and RK3568 GIC600 SoC integrations have AXI 1347 addressing limited to the first 32bit of physical address space. 1348 1349 If unsure, say Y. 1350 1351config ROCKCHIP_ERRATUM_3588001 1352 bool "Rockchip 3588001: GIC600 can not support shareability attributes" 1353 default y 1354 help 1355 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite. 1356 This means, that its sharability feature may not be used, even though it 1357 is supported by the IP itself. 1358 1359 If unsure, say Y. 1360 1361config SOCIONEXT_SYNQUACER_PREITS 1362 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 1363 default y 1364 help 1365 Socionext Synquacer SoCs implement a separate h/w block to generate 1366 MSI doorbell writes with non-zero values for the device ID. 1367 1368 If unsure, say Y. 1369 1370endmenu # "ARM errata workarounds via the alternatives framework" 1371 1372choice 1373 prompt "Page size" 1374 default ARM64_4K_PAGES 1375 help 1376 Page size (translation granule) configuration. 1377 1378config ARM64_4K_PAGES 1379 bool "4KB" 1380 select HAVE_PAGE_SIZE_4KB 1381 help 1382 This feature enables 4KB pages support. 1383 1384config ARM64_16K_PAGES 1385 bool "16KB" 1386 select HAVE_PAGE_SIZE_16KB 1387 help 1388 The system will use 16KB pages support. AArch32 emulation 1389 requires applications compiled with 16K (or a multiple of 16K) 1390 aligned segments. 1391 1392config ARM64_64K_PAGES 1393 bool "64KB" 1394 select HAVE_PAGE_SIZE_64KB 1395 help 1396 This feature enables 64KB pages support (4KB by default) 1397 allowing only two levels of page tables and faster TLB 1398 look-up. AArch32 emulation requires applications compiled 1399 with 64K aligned segments. 1400 1401endchoice 1402 1403choice 1404 prompt "Virtual address space size" 1405 default ARM64_VA_BITS_52 1406 help 1407 Allows choosing one of multiple possible virtual address 1408 space sizes. The level of translation table is determined by 1409 a combination of page size and virtual address space size. 1410 1411config ARM64_VA_BITS_36 1412 bool "36-bit" if EXPERT 1413 depends on PAGE_SIZE_16KB 1414 1415config ARM64_VA_BITS_39 1416 bool "39-bit" 1417 depends on PAGE_SIZE_4KB 1418 1419config ARM64_VA_BITS_42 1420 bool "42-bit" 1421 depends on PAGE_SIZE_64KB 1422 1423config ARM64_VA_BITS_47 1424 bool "47-bit" 1425 depends on PAGE_SIZE_16KB 1426 1427config ARM64_VA_BITS_48 1428 bool "48-bit" 1429 1430config ARM64_VA_BITS_52 1431 bool "52-bit" 1432 help 1433 Enable 52-bit virtual addressing for userspace when explicitly 1434 requested via a hint to mmap(). The kernel will also use 52-bit 1435 virtual addresses for its own mappings (provided HW support for 1436 this feature is available, otherwise it reverts to 48-bit). 1437 1438 NOTE: Enabling 52-bit virtual addressing in conjunction with 1439 ARMv8.3 Pointer Authentication will result in the PAC being 1440 reduced from 7 bits to 3 bits, which may have a significant 1441 impact on its susceptibility to brute-force attacks. 1442 1443 If unsure, select 48-bit virtual addressing instead. 1444 1445endchoice 1446 1447config ARM64_FORCE_52BIT 1448 bool "Force 52-bit virtual addresses for userspace" 1449 depends on ARM64_VA_BITS_52 && EXPERT 1450 help 1451 For systems with 52-bit userspace VAs enabled, the kernel will attempt 1452 to maintain compatibility with older software by providing 48-bit VAs 1453 unless a hint is supplied to mmap. 1454 1455 This configuration option disables the 48-bit compatibility logic, and 1456 forces all userspace addresses to be 52-bit on HW that supports it. One 1457 should only enable this configuration option for stress testing userspace 1458 memory management code. If unsure say N here. 1459 1460config ARM64_VA_BITS 1461 int 1462 default 36 if ARM64_VA_BITS_36 1463 default 39 if ARM64_VA_BITS_39 1464 default 42 if ARM64_VA_BITS_42 1465 default 47 if ARM64_VA_BITS_47 1466 default 48 if ARM64_VA_BITS_48 1467 default 52 if ARM64_VA_BITS_52 1468 1469choice 1470 prompt "Physical address space size" 1471 default ARM64_PA_BITS_48 1472 help 1473 Choose the maximum physical address range that the kernel will 1474 support. 1475 1476config ARM64_PA_BITS_48 1477 bool "48-bit" 1478 depends on ARM64_64K_PAGES || !ARM64_VA_BITS_52 1479 1480config ARM64_PA_BITS_52 1481 bool "52-bit" 1482 depends on ARM64_64K_PAGES || ARM64_VA_BITS_52 1483 help 1484 Enable support for a 52-bit physical address space, introduced as 1485 part of the ARMv8.2-LPA extension. 1486 1487 With this enabled, the kernel will also continue to work on CPUs that 1488 do not support ARMv8.2-LPA, but with some added memory overhead (and 1489 minor performance overhead). 1490 1491endchoice 1492 1493config ARM64_PA_BITS 1494 int 1495 default 48 if ARM64_PA_BITS_48 1496 default 52 if ARM64_PA_BITS_52 1497 1498config ARM64_LPA2 1499 def_bool y 1500 depends on ARM64_PA_BITS_52 && !ARM64_64K_PAGES 1501 1502choice 1503 prompt "Endianness" 1504 default CPU_LITTLE_ENDIAN 1505 help 1506 Select the endianness of data accesses performed by the CPU. Userspace 1507 applications will need to be compiled and linked for the endianness 1508 that is selected here. 1509 1510config CPU_BIG_ENDIAN 1511 bool "Build big-endian kernel" 1512 depends on BROKEN 1513 help 1514 Say Y if you plan on running a kernel with a big-endian userspace. 1515 1516config CPU_LITTLE_ENDIAN 1517 bool "Build little-endian kernel" 1518 help 1519 Say Y if you plan on running a kernel with a little-endian userspace. 1520 This is usually the case for distributions targeting arm64. 1521 1522endchoice 1523 1524config NR_CPUS 1525 int "Maximum number of CPUs (2-4096)" 1526 range 2 4096 1527 default "512" 1528 1529config HOTPLUG_CPU 1530 bool "Support for hot-pluggable CPUs" 1531 select GENERIC_IRQ_MIGRATION 1532 help 1533 Say Y here to experiment with turning CPUs off and on. CPUs 1534 can be controlled through /sys/devices/system/cpu. 1535 1536# Common NUMA Features 1537config NUMA 1538 bool "NUMA Memory Allocation and Scheduler Support" 1539 select GENERIC_ARCH_NUMA 1540 select OF_NUMA 1541 select HAVE_SETUP_PER_CPU_AREA 1542 select NEED_PER_CPU_EMBED_FIRST_CHUNK 1543 select NEED_PER_CPU_PAGE_FIRST_CHUNK 1544 select USE_PERCPU_NUMA_NODE_ID 1545 help 1546 Enable NUMA (Non-Uniform Memory Access) support. 1547 1548 The kernel will try to allocate memory used by a CPU on the 1549 local memory of the CPU and add some more 1550 NUMA awareness to the kernel. 1551 1552config NODES_SHIFT 1553 int "Maximum NUMA Nodes (as a power of 2)" 1554 range 1 10 1555 default "4" 1556 depends on NUMA 1557 help 1558 Specify the maximum number of NUMA Nodes available on the target 1559 system. Increases memory reserved to accommodate various tables. 1560 1561source "kernel/Kconfig.hz" 1562 1563config ARCH_SPARSEMEM_ENABLE 1564 def_bool y 1565 select SPARSEMEM_VMEMMAP_ENABLE 1566 1567config HW_PERF_EVENTS 1568 def_bool y 1569 depends on ARM_PMU 1570 1571# Supported by clang >= 7.0 or GCC >= 12.0.0 1572config CC_HAVE_SHADOW_CALL_STACK 1573 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) 1574 1575config PARAVIRT 1576 bool "Enable paravirtualization code" 1577 select HAVE_PV_STEAL_CLOCK_GEN 1578 help 1579 This changes the kernel so it can modify itself when it is run 1580 under a hypervisor, potentially improving performance significantly 1581 over full virtualization. 1582 1583config PARAVIRT_TIME_ACCOUNTING 1584 bool "Paravirtual steal time accounting" 1585 select PARAVIRT 1586 help 1587 Select this option to enable fine granularity task steal time 1588 accounting. Time spent executing other tasks in parallel with 1589 the current vCPU is discounted from the vCPU power. To account for 1590 that, there can be a small performance impact. 1591 1592 If in doubt, say N here. 1593 1594config ARCH_SUPPORTS_KEXEC 1595 def_bool PM_SLEEP_SMP 1596 1597config ARCH_SUPPORTS_KEXEC_FILE 1598 def_bool y 1599 1600config ARCH_SELECTS_KEXEC_FILE 1601 def_bool y 1602 depends on KEXEC_FILE 1603 select HAVE_IMA_KEXEC if IMA 1604 1605config ARCH_SUPPORTS_KEXEC_SIG 1606 def_bool y 1607 1608config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG 1609 def_bool y 1610 1611config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG 1612 def_bool y 1613 1614config ARCH_SUPPORTS_KEXEC_HANDOVER 1615 def_bool y 1616 1617config ARCH_SUPPORTS_CRASH_DUMP 1618 def_bool y 1619 1620config ARCH_DEFAULT_CRASH_DUMP 1621 def_bool y 1622 1623config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION 1624 def_bool CRASH_RESERVE 1625 1626config TRANS_TABLE 1627 def_bool y 1628 depends on HIBERNATION || KEXEC_CORE 1629 1630config XEN_DOM0 1631 def_bool y 1632 depends on XEN 1633 1634config XEN 1635 bool "Xen guest support on ARM64" 1636 depends on ARM64 && OF 1637 select SWIOTLB_XEN 1638 select PARAVIRT 1639 help 1640 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1641 1642# include/linux/mmzone.h requires the following to be true: 1643# 1644# MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1645# 1646# so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT: 1647# 1648# | SECTION_SIZE_BITS | PAGE_SHIFT | max MAX_PAGE_ORDER | default MAX_PAGE_ORDER | 1649# ----+-------------------+--------------+----------------------+-------------------------+ 1650# 4K | 27 | 12 | 15 | 10 | 1651# 16K | 27 | 14 | 13 | 11 | 1652# 64K | 29 | 16 | 13 | 13 | 1653config ARCH_FORCE_MAX_ORDER 1654 int 1655 default "13" if ARM64_64K_PAGES 1656 default "11" if ARM64_16K_PAGES 1657 default "10" 1658 help 1659 The kernel page allocator limits the size of maximal physically 1660 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1661 defines the maximal power of two of number of pages that can be 1662 allocated as a single contiguous block. This option allows 1663 overriding the default setting when ability to allocate very 1664 large blocks of physically contiguous memory is required. 1665 1666 The maximal size of allocation cannot exceed the size of the 1667 section, so the value of MAX_PAGE_ORDER should satisfy 1668 1669 MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1670 1671 Don't change if unsure. 1672 1673config UNMAP_KERNEL_AT_EL0 1674 bool "Unmap kernel when running in userspace (KPTI)" if EXPERT 1675 default y 1676 help 1677 Speculation attacks against some high-performance processors can 1678 be used to bypass MMU permission checks and leak kernel data to 1679 userspace. This can be defended against by unmapping the kernel 1680 when running in userspace, mapping it back in on exception entry 1681 via a trampoline page in the vector table. 1682 1683 If unsure, say Y. 1684 1685config MITIGATE_SPECTRE_BRANCH_HISTORY 1686 bool "Mitigate Spectre style attacks against branch history" if EXPERT 1687 default y 1688 help 1689 Speculation attacks against some high-performance processors can 1690 make use of branch history to influence future speculation. 1691 When taking an exception from user-space, a sequence of branches 1692 or a firmware call overwrites the branch history. 1693 1694config ARM64_SW_TTBR0_PAN 1695 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1696 depends on !KCSAN 1697 help 1698 Enabling this option prevents the kernel from accessing 1699 user-space memory directly by pointing TTBR0_EL1 to a reserved 1700 zeroed area and reserved ASID. The user access routines 1701 restore the valid TTBR0_EL1 temporarily. 1702 1703config ARM64_TAGGED_ADDR_ABI 1704 bool "Enable the tagged user addresses syscall ABI" 1705 default y 1706 help 1707 When this option is enabled, user applications can opt in to a 1708 relaxed ABI via prctl() allowing tagged addresses to be passed 1709 to system calls as pointer arguments. For details, see 1710 Documentation/arch/arm64/tagged-address-abi.rst. 1711 1712menuconfig COMPAT 1713 bool "Kernel support for 32-bit EL0" 1714 depends on ARM64_4K_PAGES || EXPERT 1715 select HAVE_UID16 1716 select OLD_SIGSUSPEND3 1717 select COMPAT_OLD_SIGACTION 1718 help 1719 This option enables support for a 32-bit EL0 running under a 64-bit 1720 kernel at EL1. AArch32-specific components such as system calls, 1721 the user helper functions, VFP support and the ptrace interface are 1722 handled appropriately by the kernel. 1723 1724 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1725 that you will only be able to execute AArch32 binaries that were compiled 1726 with page size aligned segments. 1727 1728 If you want to execute 32-bit userspace applications, say Y. 1729 1730if COMPAT 1731 1732config KUSER_HELPERS 1733 bool "Enable kuser helpers page for 32-bit applications" 1734 default y 1735 help 1736 Warning: disabling this option may break 32-bit user programs. 1737 1738 Provide kuser helpers to compat tasks. The kernel provides 1739 helper code to userspace in read only form at a fixed location 1740 to allow userspace to be independent of the CPU type fitted to 1741 the system. This permits binaries to be run on ARMv4 through 1742 to ARMv8 without modification. 1743 1744 See Documentation/arch/arm/kernel_user_helpers.rst for details. 1745 1746 However, the fixed address nature of these helpers can be used 1747 by ROP (return orientated programming) authors when creating 1748 exploits. 1749 1750 If all of the binaries and libraries which run on your platform 1751 are built specifically for your platform, and make no use of 1752 these helpers, then you can turn this option off to hinder 1753 such exploits. However, in that case, if a binary or library 1754 relying on those helpers is run, it will not function correctly. 1755 1756 Say N here only if you are absolutely certain that you do not 1757 need these helpers; otherwise, the safe option is to say Y. 1758 1759config COMPAT_VDSO 1760 bool "Enable vDSO for 32-bit applications" 1761 depends on !CPU_BIG_ENDIAN 1762 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" 1763 default y 1764 help 1765 Place in the process address space of 32-bit applications an 1766 ELF shared object providing fast implementations of gettimeofday 1767 and clock_gettime. 1768 1769 You must have a 32-bit build of glibc 2.22 or later for programs 1770 to seamlessly take advantage of this. 1771 1772config THUMB2_COMPAT_VDSO 1773 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT 1774 depends on COMPAT_VDSO 1775 default y 1776 help 1777 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, 1778 otherwise with '-marm'. 1779 1780config COMPAT_ALIGNMENT_FIXUPS 1781 bool "Fix up misaligned multi-word loads and stores in user space" 1782 1783menuconfig ARMV8_DEPRECATED 1784 bool "Emulate deprecated/obsolete ARMv8 instructions" 1785 depends on SYSCTL 1786 help 1787 Legacy software support may require certain instructions 1788 that have been deprecated or obsoleted in the architecture. 1789 1790 Enable this config to enable selective emulation of these 1791 features. 1792 1793 If unsure, say Y 1794 1795if ARMV8_DEPRECATED 1796 1797config SWP_EMULATION 1798 bool "Emulate SWP/SWPB instructions" 1799 help 1800 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1801 they are always undefined. Say Y here to enable software 1802 emulation of these instructions for userspace using LDXR/STXR. 1803 This feature can be controlled at runtime with the abi.swp 1804 sysctl which is disabled by default. 1805 1806 In some older versions of glibc [<=2.8] SWP is used during futex 1807 trylock() operations with the assumption that the code will not 1808 be preempted. This invalid assumption may be more likely to fail 1809 with SWP emulation enabled, leading to deadlock of the user 1810 application. 1811 1812 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1813 on an external transaction monitoring block called a global 1814 monitor to maintain update atomicity. If your system does not 1815 implement a global monitor, this option can cause programs that 1816 perform SWP operations to uncached memory to deadlock. 1817 1818 If unsure, say Y 1819 1820config CP15_BARRIER_EMULATION 1821 bool "Emulate CP15 Barrier instructions" 1822 help 1823 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1824 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1825 strongly recommended to use the ISB, DSB, and DMB 1826 instructions instead. 1827 1828 Say Y here to enable software emulation of these 1829 instructions for AArch32 userspace code. When this option is 1830 enabled, CP15 barrier usage is traced which can help 1831 identify software that needs updating. This feature can be 1832 controlled at runtime with the abi.cp15_barrier sysctl. 1833 1834 If unsure, say Y 1835 1836config SETEND_EMULATION 1837 bool "Emulate SETEND instruction" 1838 help 1839 The SETEND instruction alters the data-endianness of the 1840 AArch32 EL0, and is deprecated in ARMv8. 1841 1842 Say Y here to enable software emulation of the instruction 1843 for AArch32 userspace code. This feature can be controlled 1844 at runtime with the abi.setend sysctl. 1845 1846 Note: All the cpus on the system must have mixed endian support at EL0 1847 for this feature to be enabled. If a new CPU - which doesn't support mixed 1848 endian - is hotplugged in after this feature has been enabled, there could 1849 be unexpected results in the applications. 1850 1851 If unsure, say Y 1852endif # ARMV8_DEPRECATED 1853 1854endif # COMPAT 1855 1856menu "ARMv8.1 architectural features" 1857 1858config ARM64_HW_AFDBM 1859 bool "Support for hardware updates of the Access and Dirty page flags" 1860 default y 1861 help 1862 The ARMv8.1 architecture extensions introduce support for 1863 hardware updates of the access and dirty information in page 1864 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1865 capable processors, accesses to pages with PTE_AF cleared will 1866 set this bit instead of raising an access flag fault. 1867 Similarly, writes to read-only pages with the DBM bit set will 1868 clear the read-only bit (AP[2]) instead of raising a 1869 permission fault. 1870 1871 Kernels built with this configuration option enabled continue 1872 to work on pre-ARMv8.1 hardware and the performance impact is 1873 minimal. If unsure, say Y. 1874 1875endmenu # "ARMv8.1 architectural features" 1876 1877menu "ARMv8.2 architectural features" 1878 1879config ARM64_PMEM 1880 bool "Enable support for persistent memory" 1881 select ARCH_HAS_PMEM_API 1882 select ARCH_HAS_UACCESS_FLUSHCACHE 1883 help 1884 Say Y to enable support for the persistent memory API based on the 1885 ARMv8.2 DCPoP feature. 1886 1887 The feature is detected at runtime, and the kernel will use DC CVAC 1888 operations if DC CVAP is not supported (following the behaviour of 1889 DC CVAP itself if the system does not define a point of persistence). 1890 1891config ARM64_RAS_EXTN 1892 bool "Enable support for RAS CPU Extensions" 1893 default y 1894 help 1895 CPUs that support the Reliability, Availability and Serviceability 1896 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1897 errors, classify them and report them to software. 1898 1899 On CPUs with these extensions system software can use additional 1900 barriers to determine if faults are pending and read the 1901 classification from a new set of registers. 1902 1903 Selecting this feature will allow the kernel to use these barriers 1904 and access the new registers if the system supports the extension. 1905 Platform RAS features may additionally depend on firmware support. 1906 1907config ARM64_CNP 1908 bool "Enable support for Common Not Private (CNP) translations" 1909 default y 1910 help 1911 Common Not Private (CNP) allows translation table entries to 1912 be shared between different PEs in the same inner shareable 1913 domain, so the hardware can use this fact to optimise the 1914 caching of such entries in the TLB. 1915 1916 Selecting this option allows the CNP feature to be detected 1917 at runtime, and does not affect PEs that do not implement 1918 this feature. 1919 1920endmenu # "ARMv8.2 architectural features" 1921 1922menu "ARMv8.3 architectural features" 1923 1924config ARM64_PTR_AUTH 1925 bool "Enable support for pointer authentication" 1926 default y 1927 help 1928 Pointer authentication (part of the ARMv8.3 Extensions) provides 1929 instructions for signing and authenticating pointers against secret 1930 keys, which can be used to mitigate Return Oriented Programming (ROP) 1931 and other attacks. 1932 1933 This option enables these instructions at EL0 (i.e. for userspace). 1934 Choosing this option will cause the kernel to initialise secret keys 1935 for each process at exec() time, with these keys being 1936 context-switched along with the process. 1937 1938 The feature is detected at runtime. If the feature is not present in 1939 hardware it will not be advertised to userspace/KVM guest nor will it 1940 be enabled. 1941 1942 If the feature is present on the boot CPU but not on a late CPU, then 1943 the late CPU will be parked. Also, if the boot CPU does not have 1944 address auth and the late CPU has then the late CPU will still boot 1945 but with the feature disabled. On such a system, this option should 1946 not be selected. 1947 1948config ARM64_PTR_AUTH_KERNEL 1949 bool "Use pointer authentication for kernel" 1950 default y 1951 depends on ARM64_PTR_AUTH 1952 # Modern compilers insert a .note.gnu.property section note for PAC 1953 # which is only understood by binutils starting with version 2.33.1. 1954 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) 1955 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE 1956 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 1957 help 1958 If the compiler supports the -mbranch-protection or 1959 -msign-return-address flag (e.g. GCC 7 or later), then this option 1960 will cause the kernel itself to be compiled with return address 1961 protection. In this case, and if the target hardware is known to 1962 support pointer authentication, then CONFIG_STACKPROTECTOR can be 1963 disabled with minimal loss of protection. 1964 1965 This feature works with FUNCTION_GRAPH_TRACER option only if 1966 DYNAMIC_FTRACE_WITH_ARGS is enabled. 1967 1968config CC_HAS_BRANCH_PROT_PAC_RET 1969 # GCC 9 or later, clang 8 or later 1970 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) 1971 1972config AS_HAS_CFI_NEGATE_RA_STATE 1973 # binutils 2.34+ 1974 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) 1975 1976endmenu # "ARMv8.3 architectural features" 1977 1978menu "ARMv8.4 architectural features" 1979 1980config ARM64_AMU_EXTN 1981 bool "Enable support for the Activity Monitors Unit CPU extension" 1982 default y 1983 help 1984 The activity monitors extension is an optional extension introduced 1985 by the ARMv8.4 CPU architecture. This enables support for version 1 1986 of the activity monitors architecture, AMUv1. 1987 1988 To enable the use of this extension on CPUs that implement it, say Y. 1989 1990 Note that for architectural reasons, firmware _must_ implement AMU 1991 support when running on CPUs that present the activity monitors 1992 extension. The required support is present in: 1993 * Version 1.5 and later of the ARM Trusted Firmware 1994 1995 For kernels that have this configuration enabled but boot with broken 1996 firmware, you may need to say N here until the firmware is fixed. 1997 Otherwise you may experience firmware panics or lockups when 1998 accessing the counter registers. Even if you are not observing these 1999 symptoms, the values returned by the register reads might not 2000 correctly reflect reality. Most commonly, the value read will be 0, 2001 indicating that the counter is not enabled. 2002 2003config ARM64_TLB_RANGE 2004 bool "Enable support for tlbi range feature" 2005 default y 2006 help 2007 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a 2008 range of input addresses. 2009 2010config ARM64_MPAM 2011 bool "Enable support for MPAM" 2012 select ARM64_MPAM_DRIVER if EXPERT # does nothing yet 2013 select ACPI_MPAM if ACPI 2014 help 2015 Memory System Resource Partitioning and Monitoring (MPAM) is an 2016 optional extension to the Arm architecture that allows each 2017 transaction issued to the memory system to be labelled with a 2018 Partition identifier (PARTID) and Performance Monitoring Group 2019 identifier (PMG). 2020 2021 Memory system components, such as the caches, can be configured with 2022 policies to control how much of various physical resources (such as 2023 memory bandwidth or cache memory) the transactions labelled with each 2024 PARTID can consume. Depending on the capabilities of the hardware, 2025 the PARTID and PMG can also be used as filtering criteria to measure 2026 the memory system resource consumption of different parts of a 2027 workload. 2028 2029 Use of this extension requires CPU support, support in the 2030 Memory System Components (MSC), and a description from firmware 2031 of where the MSCs are in the address space. 2032 2033 MPAM is exposed to user-space via the resctrl pseudo filesystem. 2034 2035endmenu # "ARMv8.4 architectural features" 2036 2037menu "ARMv8.5 architectural features" 2038 2039config AS_HAS_ARMV8_5 2040 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) 2041 2042config ARM64_BTI 2043 bool "Branch Target Identification support" 2044 default y 2045 help 2046 Branch Target Identification (part of the ARMv8.5 Extensions) 2047 provides a mechanism to limit the set of locations to which computed 2048 branch instructions such as BR or BLR can jump. 2049 2050 To make use of BTI on CPUs that support it, say Y. 2051 2052 BTI is intended to provide complementary protection to other control 2053 flow integrity protection mechanisms, such as the Pointer 2054 authentication mechanism provided as part of the ARMv8.3 Extensions. 2055 For this reason, it does not make sense to enable this option without 2056 also enabling support for pointer authentication. Thus, when 2057 enabling this option you should also select ARM64_PTR_AUTH=y. 2058 2059 Userspace binaries must also be specifically compiled to make use of 2060 this mechanism. If you say N here or the hardware does not support 2061 BTI, such binaries can still run, but you get no additional 2062 enforcement of branch destinations. 2063 2064config ARM64_BTI_KERNEL 2065 bool "Use Branch Target Identification for kernel" 2066 default y 2067 depends on ARM64_BTI 2068 depends on ARM64_PTR_AUTH_KERNEL 2069 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI 2070 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 2071 depends on !CC_IS_GCC || GCC_VERSION >= 100100 2072 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671 2073 depends on !CC_IS_GCC 2074 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 2075 help 2076 Build the kernel with Branch Target Identification annotations 2077 and enable enforcement of this for kernel code. When this option 2078 is enabled and the system supports BTI all kernel code including 2079 modular code must have BTI enabled. 2080 2081config CC_HAS_BRANCH_PROT_PAC_RET_BTI 2082 # GCC 9 or later, clang 8 or later 2083 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) 2084 2085config ARM64_E0PD 2086 bool "Enable support for E0PD" 2087 default y 2088 help 2089 E0PD (part of the ARMv8.5 extensions) allows us to ensure 2090 that EL0 accesses made via TTBR1 always fault in constant time, 2091 providing similar benefits to KASLR as those provided by KPTI, but 2092 with lower overhead and without disrupting legitimate access to 2093 kernel memory such as SPE. 2094 2095 This option enables E0PD for TTBR1 where available. 2096 2097config ARM64_AS_HAS_MTE 2098 # Initial support for MTE went in binutils 2.32.0, checked with 2099 # ".arch armv8.5-a+memtag" below. However, this was incomplete 2100 # as a late addition to the final architecture spec (LDGM/STGM) 2101 # is only supported in the newer 2.32.x and 2.33 binutils 2102 # versions, hence the extra "stgm" instruction check below. 2103 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) 2104 2105config ARM64_MTE 2106 bool "Memory Tagging Extension support" 2107 default y 2108 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 2109 depends on AS_HAS_ARMV8_5 2110 # Required for tag checking in the uaccess routines 2111 select ARCH_HAS_SUBPAGE_FAULTS 2112 select ARCH_USES_HIGH_VMA_FLAGS 2113 select ARCH_USES_PG_ARCH_2 2114 select ARCH_USES_PG_ARCH_3 2115 help 2116 Memory Tagging (part of the ARMv8.5 Extensions) provides 2117 architectural support for run-time, always-on detection of 2118 various classes of memory error to aid with software debugging 2119 to eliminate vulnerabilities arising from memory-unsafe 2120 languages. 2121 2122 This option enables the support for the Memory Tagging 2123 Extension at EL0 (i.e. for userspace). 2124 2125 Selecting this option allows the feature to be detected at 2126 runtime. Any secondary CPU not implementing this feature will 2127 not be allowed a late bring-up. 2128 2129 Userspace binaries that want to use this feature must 2130 explicitly opt in. The mechanism for the userspace is 2131 described in: 2132 2133 Documentation/arch/arm64/memory-tagging-extension.rst. 2134 2135endmenu # "ARMv8.5 architectural features" 2136 2137menu "ARMv8.7 architectural features" 2138 2139config ARM64_EPAN 2140 bool "Enable support for Enhanced Privileged Access Never (EPAN)" 2141 default y 2142 help 2143 Enhanced Privileged Access Never (EPAN) allows Privileged 2144 Access Never to be used with Execute-only mappings. 2145 2146 The feature is detected at runtime, and will remain disabled 2147 if the cpu does not implement the feature. 2148endmenu # "ARMv8.7 architectural features" 2149 2150config AS_HAS_MOPS 2151 def_bool $(as-instr,.arch_extension mops) 2152 2153menu "ARMv8.9 architectural features" 2154 2155config ARM64_POE 2156 prompt "Permission Overlay Extension" 2157 def_bool y 2158 select ARCH_USES_HIGH_VMA_FLAGS 2159 select ARCH_HAS_PKEYS 2160 help 2161 The Permission Overlay Extension is used to implement Memory 2162 Protection Keys. Memory Protection Keys provides a mechanism for 2163 enforcing page-based protections, but without requiring modification 2164 of the page tables when an application changes protection domains. 2165 2166 For details, see Documentation/core-api/protection-keys.rst 2167 2168 If unsure, say y. 2169 2170config ARCH_PKEY_BITS 2171 int 2172 default 3 2173 2174config ARM64_HAFT 2175 bool "Support for Hardware managed Access Flag for Table Descriptors" 2176 depends on ARM64_HW_AFDBM 2177 default y 2178 help 2179 The ARMv8.9/ARMv9.5 introduces the feature Hardware managed Access 2180 Flag for Table descriptors. When enabled an architectural executed 2181 memory access will update the Access Flag in each Table descriptor 2182 which is accessed during the translation table walk and for which 2183 the Access Flag is 0. The Access Flag of the Table descriptor use 2184 the same bit of PTE_AF. 2185 2186 The feature will only be enabled if all the CPUs in the system 2187 support this feature. If unsure, say Y. 2188 2189endmenu # "ARMv8.9 architectural features" 2190 2191menu "ARMv9.4 architectural features" 2192 2193config ARM64_GCS 2194 bool "Enable support for Guarded Control Stack (GCS)" 2195 default y 2196 select ARCH_HAS_USER_SHADOW_STACK 2197 select ARCH_USES_HIGH_VMA_FLAGS 2198 help 2199 Guarded Control Stack (GCS) provides support for a separate 2200 stack with restricted access which contains only return 2201 addresses. This can be used to harden against some attacks 2202 by comparing return address used by the program with what is 2203 stored in the GCS, and may also be used to efficiently obtain 2204 the call stack for applications such as profiling. 2205 2206 The feature is detected at runtime, and will remain disabled 2207 if the system does not implement the feature. 2208 2209endmenu # "ARMv9.4 architectural features" 2210 2211config ARM64_SVE 2212 bool "ARM Scalable Vector Extension support" 2213 default y 2214 help 2215 The Scalable Vector Extension (SVE) is an extension to the AArch64 2216 execution state which complements and extends the SIMD functionality 2217 of the base architecture to support much larger vectors and to enable 2218 additional vectorisation opportunities. 2219 2220 To enable use of this extension on CPUs that implement it, say Y. 2221 2222 On CPUs that support the SVE2 extensions, this option will enable 2223 those too. 2224 2225 Note that for architectural reasons, firmware _must_ implement SVE 2226 support when running on SVE capable hardware. The required support 2227 is present in: 2228 2229 * version 1.5 and later of the ARM Trusted Firmware 2230 * the AArch64 boot wrapper since commit 5e1261e08abf 2231 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 2232 2233 For other firmware implementations, consult the firmware documentation 2234 or vendor. 2235 2236 If you need the kernel to boot on SVE-capable hardware with broken 2237 firmware, you may need to say N here until you get your firmware 2238 fixed. Otherwise, you may experience firmware panics or lockups when 2239 booting the kernel. If unsure and you are not observing these 2240 symptoms, you should assume that it is safe to say Y. 2241 2242config ARM64_SME 2243 bool "ARM Scalable Matrix Extension support" 2244 default y 2245 depends on ARM64_SVE 2246 help 2247 The Scalable Matrix Extension (SME) is an extension to the AArch64 2248 execution state which utilises a substantial subset of the SVE 2249 instruction set, together with the addition of new architectural 2250 register state capable of holding two dimensional matrix tiles to 2251 enable various matrix operations. 2252 2253config ARM64_PSEUDO_NMI 2254 bool "Support for NMI-like interrupts" 2255 select ARM_GIC_V3 2256 help 2257 Adds support for mimicking Non-Maskable Interrupts through the use of 2258 GIC interrupt priority. This support requires version 3 or later of 2259 ARM GIC. 2260 2261 This high priority configuration for interrupts needs to be 2262 explicitly enabled by setting the kernel parameter 2263 "irqchip.gicv3_pseudo_nmi" to 1. 2264 2265 If unsure, say N 2266 2267if ARM64_PSEUDO_NMI 2268config ARM64_DEBUG_PRIORITY_MASKING 2269 bool "Debug interrupt priority masking" 2270 help 2271 This adds runtime checks to functions enabling/disabling 2272 interrupts when using priority masking. The additional checks verify 2273 the validity of ICC_PMR_EL1 when calling concerned functions. 2274 2275 If unsure, say N 2276endif # ARM64_PSEUDO_NMI 2277 2278config RELOCATABLE 2279 bool "Build a relocatable kernel image" if EXPERT 2280 select ARCH_HAS_RELR 2281 default y 2282 help 2283 This builds the kernel as a Position Independent Executable (PIE), 2284 which retains all relocation metadata required to relocate the 2285 kernel binary at runtime to a different virtual address than the 2286 address it was linked at. 2287 Since AArch64 uses the RELA relocation format, this requires a 2288 relocation pass at runtime even if the kernel is loaded at the 2289 same address it was linked at. 2290 2291config RANDOMIZE_BASE 2292 bool "Randomize the address of the kernel image" 2293 select RELOCATABLE 2294 help 2295 Randomizes the virtual address at which the kernel image is 2296 loaded, as a security feature that deters exploit attempts 2297 relying on knowledge of the location of kernel internals. 2298 2299 It is the bootloader's job to provide entropy, by passing a 2300 random u64 value in /chosen/kaslr-seed at kernel entry. 2301 2302 When booting via the UEFI stub, it will invoke the firmware's 2303 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 2304 to the kernel proper. In addition, it will randomise the physical 2305 location of the kernel Image as well. 2306 2307 If unsure, say N. 2308 2309config RANDOMIZE_MODULE_REGION_FULL 2310 bool "Randomize the module region over a 2 GB range" 2311 depends on RANDOMIZE_BASE 2312 default y 2313 help 2314 Randomizes the location of the module region inside a 2 GB window 2315 covering the core kernel. This way, it is less likely for modules 2316 to leak information about the location of core kernel data structures 2317 but it does imply that function calls between modules and the core 2318 kernel will need to be resolved via veneers in the module PLT. 2319 2320 When this option is not set, the module region will be randomized over 2321 a limited range that contains the [_stext, _etext] interval of the 2322 core kernel, so branch relocations are almost always in range unless 2323 the region is exhausted. In this particular case of region 2324 exhaustion, modules might be able to fall back to a larger 2GB area. 2325 2326config CC_HAVE_STACKPROTECTOR_SYSREG 2327 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 2328 2329config STACKPROTECTOR_PER_TASK 2330 def_bool y 2331 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 2332 2333config UNWIND_PATCH_PAC_INTO_SCS 2334 bool "Enable shadow call stack dynamically using code patching" 2335 depends on CC_IS_CLANG 2336 depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET 2337 depends on SHADOW_CALL_STACK 2338 select UNWIND_TABLES 2339 select DYNAMIC_SCS 2340 2341config ARM64_CONTPTE 2342 bool "Contiguous PTE mappings for user memory" if EXPERT 2343 depends on TRANSPARENT_HUGEPAGE 2344 default y 2345 help 2346 When enabled, user mappings are configured using the PTE contiguous 2347 bit, for any mappings that meet the size and alignment requirements. 2348 This reduces TLB pressure and improves performance. 2349 2350endmenu # "Kernel Features" 2351 2352menu "Boot options" 2353 2354config ARM64_ACPI_PARKING_PROTOCOL 2355 bool "Enable support for the ARM64 ACPI parking protocol" 2356 depends on ACPI 2357 help 2358 Enable support for the ARM64 ACPI parking protocol. If disabled 2359 the kernel will not allow booting through the ARM64 ACPI parking 2360 protocol even if the corresponding data is present in the ACPI 2361 MADT table. 2362 2363config CMDLINE 2364 string "Default kernel command string" 2365 default "" 2366 help 2367 Provide a set of default command-line options at build time by 2368 entering them here. As a minimum, you should specify the the 2369 root device (e.g. root=/dev/nfs). 2370 2371choice 2372 prompt "Kernel command line type" 2373 depends on CMDLINE != "" 2374 default CMDLINE_FROM_BOOTLOADER 2375 help 2376 Choose how the kernel will handle the provided default kernel 2377 command line string. 2378 2379config CMDLINE_FROM_BOOTLOADER 2380 bool "Use bootloader kernel arguments if available" 2381 help 2382 Uses the command-line options passed by the boot loader. If 2383 the boot loader doesn't provide any, the default kernel command 2384 string provided in CMDLINE will be used. 2385 2386config CMDLINE_FORCE 2387 bool "Always use the default kernel command string" 2388 help 2389 Always use the default kernel command string, even if the boot 2390 loader passes other arguments to the kernel. 2391 This is useful if you cannot or don't want to change the 2392 command-line options your boot loader passes to the kernel. 2393 2394endchoice 2395 2396config EFI_STUB 2397 bool 2398 2399config EFI 2400 bool "UEFI runtime support" 2401 depends on OF && !CPU_BIG_ENDIAN 2402 depends on KERNEL_MODE_NEON 2403 select ARCH_SUPPORTS_ACPI 2404 select LIBFDT 2405 select UCS2_STRING 2406 select EFI_PARAMS_FROM_FDT 2407 select EFI_RUNTIME_WRAPPERS 2408 select EFI_STUB 2409 select EFI_GENERIC_STUB 2410 imply IMA_SECURE_AND_OR_TRUSTED_BOOT 2411 default y 2412 help 2413 This option provides support for runtime services provided 2414 by UEFI firmware (such as non-volatile variables, realtime 2415 clock, and platform reset). A UEFI stub is also provided to 2416 allow the kernel to be booted as an EFI application. This 2417 is only useful on systems that have UEFI firmware. 2418 2419config COMPRESSED_INSTALL 2420 bool "Install compressed image by default" 2421 help 2422 This makes the regular "make install" install the compressed 2423 image we built, not the legacy uncompressed one. 2424 2425 You can check that a compressed image works for you by doing 2426 "make zinstall" first, and verifying that everything is fine 2427 in your environment before making "make install" do this for 2428 you. 2429 2430config DMI 2431 bool "Enable support for SMBIOS (DMI) tables" 2432 depends on EFI 2433 default y 2434 help 2435 This enables SMBIOS/DMI feature for systems. 2436 2437 This option is only useful on systems that have UEFI firmware. 2438 However, even with this option, the resultant kernel should 2439 continue to boot on existing non-UEFI platforms. 2440 2441endmenu # "Boot options" 2442 2443menu "Power management options" 2444 2445source "kernel/power/Kconfig" 2446 2447config ARCH_HIBERNATION_POSSIBLE 2448 def_bool y 2449 depends on CPU_PM 2450 2451config ARCH_HIBERNATION_HEADER 2452 def_bool y 2453 depends on HIBERNATION 2454 2455config ARCH_SUSPEND_POSSIBLE 2456 def_bool y 2457 2458endmenu # "Power management options" 2459 2460menu "CPU Power Management" 2461 2462source "drivers/cpuidle/Kconfig" 2463 2464source "drivers/cpufreq/Kconfig" 2465 2466endmenu # "CPU Power Management" 2467 2468source "drivers/acpi/Kconfig" 2469 2470source "arch/arm64/kvm/Kconfig" 2471 2472source "kernel/livepatch/Kconfig" 2473