1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Xilinx Zynq MPSoC Firmware layer
4 *
5 * Copyright (C) 2014-2021 Xilinx
6 *
7 * Michal Simek <michal.simek@amd.com>
8 * Davorin Mista <davorin.mista@aggios.com>
9 * Jolly Shah <jollys@xilinx.com>
10 * Rajan Vaja <rajanv@xilinx.com>
11 */
12
13 #ifndef __FIRMWARE_ZYNQMP_H__
14 #define __FIRMWARE_ZYNQMP_H__
15 #include <linux/types.h>
16
17 #include <linux/err.h>
18
19 #define ZYNQMP_PM_VERSION_MAJOR 1
20 #define ZYNQMP_PM_VERSION_MINOR 0
21
22 #define ZYNQMP_PM_VERSION ((ZYNQMP_PM_VERSION_MAJOR << 16) | \
23 ZYNQMP_PM_VERSION_MINOR)
24
25 #define ZYNQMP_TZ_VERSION_MAJOR 1
26 #define ZYNQMP_TZ_VERSION_MINOR 0
27
28 #define ZYNQMP_TZ_VERSION ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
29 ZYNQMP_TZ_VERSION_MINOR)
30
31 /* SMC SIP service Call Function Identifier Prefix */
32 #define PM_SIP_SVC 0xC2000000
33
34 /* PM API versions */
35 #define PM_API_VERSION_1 1
36 #define PM_API_VERSION_2 2
37
38 #define PM_PINCTRL_PARAM_SET_VERSION 2
39
40 #define ZYNQMP_FAMILY_CODE 0x23
41 #define VERSAL_FAMILY_CODE 0x26
42
43 /* When all subfamily of platform need to support */
44 #define ALL_SUB_FAMILY_CODE 0x00
45 #define VERSAL_SUB_FAMILY_CODE 0x01
46 #define VERSALNET_SUB_FAMILY_CODE 0x03
47
48 #define FAMILY_CODE_MASK GENMASK(27, 21)
49 #define SUB_FAMILY_CODE_MASK GENMASK(20, 19)
50
51 #define API_ID_MASK GENMASK(7, 0)
52 #define MODULE_ID_MASK GENMASK(11, 8)
53
54 /* ATF only commands */
55 #define TF_A_PM_REGISTER_SGI 0xa04
56 #define PM_GET_TRUSTZONE_VERSION 0xa03
57 #define PM_SET_SUSPEND_MODE 0xa02
58 #define GET_CALLBACK_DATA 0xa01
59
60 /* Number of 32bits values in payload */
61 #define PAYLOAD_ARG_CNT 4U
62
63 /* Number of arguments for a callback */
64 #define CB_ARG_CNT 4
65
66 /* Payload size (consists of callback API ID + arguments) */
67 #define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1)
68
69 #define ZYNQMP_PM_MAX_QOS 100U
70
71 #define GSS_NUM_REGS (4)
72
73 /* Node capabilities */
74 #define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U
75 #define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U
76 #define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
77 #define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U
78
79 /* Loader commands */
80 #define PM_LOAD_PDI 0x701
81 #define PDI_SRC_DDR 0xF
82
83 /*
84 * Firmware FPGA Manager flags
85 * XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration
86 * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration
87 */
88 #define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U
89 #define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0)
90
91 /* FPGA Status Reg */
92 #define XILINX_ZYNQMP_PM_FPGA_CONFIG_STAT_OFFSET 7U
93 #define XILINX_ZYNQMP_PM_FPGA_READ_CONFIG_REG 0U
94
95 /*
96 * Node IDs for the Error Events.
97 */
98 #define VERSAL_EVENT_ERROR_PMC_ERR1 (0x28100000U)
99 #define VERSAL_EVENT_ERROR_PMC_ERR2 (0x28104000U)
100 #define VERSAL_EVENT_ERROR_PSM_ERR1 (0x28108000U)
101 #define VERSAL_EVENT_ERROR_PSM_ERR2 (0x2810C000U)
102
103 #define VERSAL_NET_EVENT_ERROR_PMC_ERR1 (0x28100000U)
104 #define VERSAL_NET_EVENT_ERROR_PMC_ERR2 (0x28104000U)
105 #define VERSAL_NET_EVENT_ERROR_PMC_ERR3 (0x28108000U)
106 #define VERSAL_NET_EVENT_ERROR_PSM_ERR1 (0x2810C000U)
107 #define VERSAL_NET_EVENT_ERROR_PSM_ERR2 (0x28110000U)
108 #define VERSAL_NET_EVENT_ERROR_PSM_ERR3 (0x28114000U)
109 #define VERSAL_NET_EVENT_ERROR_PSM_ERR4 (0x28118000U)
110
111 /* ZynqMP SD tap delay tuning */
112 #define SD_ITAPDLY 0xFF180314
113 #define SD_OTAPDLYSEL 0xFF180318
114
115 /**
116 * XPM_EVENT_ERROR_MASK_DDRMC_CR: Error event mask for DDRMC MC Correctable ECC Error.
117 */
118 #define XPM_EVENT_ERROR_MASK_DDRMC_CR BIT(18)
119
120 /**
121 * XPM_EVENT_ERROR_MASK_DDRMC_NCR: Error event mask for DDRMC MC Non-Correctable ECC Error.
122 */
123 #define XPM_EVENT_ERROR_MASK_DDRMC_NCR BIT(19)
124 #define XPM_EVENT_ERROR_MASK_NOC_NCR BIT(13)
125 #define XPM_EVENT_ERROR_MASK_NOC_CR BIT(12)
126
127 enum pm_module_id {
128 PM_MODULE_ID = 0x0,
129 XSEM_MODULE_ID = 0x3,
130 TF_A_MODULE_ID = 0xa,
131 };
132
133 enum pm_api_cb_id {
134 PM_INIT_SUSPEND_CB = 30,
135 PM_ACKNOWLEDGE_CB = 31,
136 PM_NOTIFY_CB = 32,
137 };
138
139 enum pm_api_id {
140 PM_API_FEATURES = 0,
141 PM_GET_API_VERSION = 1,
142 PM_REGISTER_NOTIFIER = 5,
143 PM_FORCE_POWERDOWN = 8,
144 PM_REQUEST_WAKEUP = 10,
145 PM_SYSTEM_SHUTDOWN = 12,
146 PM_REQUEST_NODE = 13,
147 PM_RELEASE_NODE = 14,
148 PM_SET_REQUIREMENT = 15,
149 PM_RESET_ASSERT = 17,
150 PM_RESET_GET_STATUS = 18,
151 PM_MMIO_WRITE = 19,
152 PM_MMIO_READ = 20,
153 PM_PM_INIT_FINALIZE = 21,
154 PM_FPGA_LOAD = 22,
155 PM_FPGA_GET_STATUS = 23,
156 PM_GET_CHIPID = 24,
157 PM_SECURE_SHA = 26,
158 PM_PINCTRL_REQUEST = 28,
159 PM_PINCTRL_RELEASE = 29,
160 PM_PINCTRL_SET_FUNCTION = 31,
161 PM_PINCTRL_CONFIG_PARAM_GET = 32,
162 PM_PINCTRL_CONFIG_PARAM_SET = 33,
163 PM_IOCTL = 34,
164 PM_QUERY_DATA = 35,
165 PM_CLOCK_ENABLE = 36,
166 PM_CLOCK_DISABLE = 37,
167 PM_CLOCK_GETSTATE = 38,
168 PM_CLOCK_SETDIVIDER = 39,
169 PM_CLOCK_GETDIVIDER = 40,
170 PM_CLOCK_SETPARENT = 43,
171 PM_CLOCK_GETPARENT = 44,
172 PM_FPGA_READ = 46,
173 PM_SECURE_AES = 47,
174 PM_FEATURE_CHECK = 63,
175 };
176
177 /* PMU-FW return status codes */
178 enum pm_ret_status {
179 XST_PM_SUCCESS = 0,
180 XST_PM_INVALID_VERSION = 4,
181 XST_PM_NO_FEATURE = 19,
182 XST_PM_INVALID_CRC = 301,
183 XST_PM_INTERNAL = 2000,
184 XST_PM_CONFLICT = 2001,
185 XST_PM_NO_ACCESS = 2002,
186 XST_PM_INVALID_NODE = 2003,
187 XST_PM_DOUBLE_REQ = 2004,
188 XST_PM_ABORT_SUSPEND = 2005,
189 XST_PM_MULT_USER = 2008,
190 };
191
192 enum pm_ioctl_id {
193 IOCTL_GET_RPU_OPER_MODE = 0,
194 IOCTL_SET_RPU_OPER_MODE = 1,
195 IOCTL_RPU_BOOT_ADDR_CONFIG = 2,
196 IOCTL_TCM_COMB_CONFIG = 3,
197 IOCTL_SET_TAPDELAY_BYPASS = 4,
198 IOCTL_SD_DLL_RESET = 6,
199 IOCTL_SET_SD_TAPDELAY = 7,
200 IOCTL_SET_PLL_FRAC_MODE = 8,
201 IOCTL_GET_PLL_FRAC_MODE = 9,
202 IOCTL_SET_PLL_FRAC_DATA = 10,
203 IOCTL_GET_PLL_FRAC_DATA = 11,
204 IOCTL_WRITE_GGS = 12,
205 IOCTL_READ_GGS = 13,
206 IOCTL_WRITE_PGGS = 14,
207 IOCTL_READ_PGGS = 15,
208 /* Set healthy bit value */
209 IOCTL_SET_BOOT_HEALTH_STATUS = 17,
210 IOCTL_OSPI_MUX_SELECT = 21,
211 /* Register SGI to ATF */
212 IOCTL_REGISTER_SGI = 25,
213 /* Runtime feature configuration */
214 IOCTL_SET_FEATURE_CONFIG = 26,
215 IOCTL_GET_FEATURE_CONFIG = 27,
216 /* Dynamic SD/GEM configuration */
217 IOCTL_SET_SD_CONFIG = 30,
218 IOCTL_SET_GEM_CONFIG = 31,
219 };
220
221 enum pm_query_id {
222 PM_QID_INVALID = 0,
223 PM_QID_CLOCK_GET_NAME = 1,
224 PM_QID_CLOCK_GET_TOPOLOGY = 2,
225 PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3,
226 PM_QID_CLOCK_GET_PARENTS = 4,
227 PM_QID_CLOCK_GET_ATTRIBUTES = 5,
228 PM_QID_PINCTRL_GET_NUM_PINS = 6,
229 PM_QID_PINCTRL_GET_NUM_FUNCTIONS = 7,
230 PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS = 8,
231 PM_QID_PINCTRL_GET_FUNCTION_NAME = 9,
232 PM_QID_PINCTRL_GET_FUNCTION_GROUPS = 10,
233 PM_QID_PINCTRL_GET_PIN_GROUPS = 11,
234 PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
235 PM_QID_CLOCK_GET_MAX_DIVISOR = 13,
236 };
237
238 enum rpu_oper_mode {
239 PM_RPU_MODE_LOCKSTEP = 0,
240 PM_RPU_MODE_SPLIT = 1,
241 };
242
243 enum rpu_boot_mem {
244 PM_RPU_BOOTMEM_LOVEC = 0,
245 PM_RPU_BOOTMEM_HIVEC = 1,
246 };
247
248 enum rpu_tcm_comb {
249 PM_RPU_TCM_SPLIT = 0,
250 PM_RPU_TCM_COMB = 1,
251 };
252
253 enum zynqmp_pm_reset_action {
254 PM_RESET_ACTION_RELEASE = 0,
255 PM_RESET_ACTION_ASSERT = 1,
256 PM_RESET_ACTION_PULSE = 2,
257 };
258
259 enum zynqmp_pm_reset {
260 ZYNQMP_PM_RESET_START = 1000,
261 ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
262 ZYNQMP_PM_RESET_PCIE_BRIDGE = 1001,
263 ZYNQMP_PM_RESET_PCIE_CTRL = 1002,
264 ZYNQMP_PM_RESET_DP = 1003,
265 ZYNQMP_PM_RESET_SWDT_CRF = 1004,
266 ZYNQMP_PM_RESET_AFI_FM5 = 1005,
267 ZYNQMP_PM_RESET_AFI_FM4 = 1006,
268 ZYNQMP_PM_RESET_AFI_FM3 = 1007,
269 ZYNQMP_PM_RESET_AFI_FM2 = 1008,
270 ZYNQMP_PM_RESET_AFI_FM1 = 1009,
271 ZYNQMP_PM_RESET_AFI_FM0 = 1010,
272 ZYNQMP_PM_RESET_GDMA = 1011,
273 ZYNQMP_PM_RESET_GPU_PP1 = 1012,
274 ZYNQMP_PM_RESET_GPU_PP0 = 1013,
275 ZYNQMP_PM_RESET_GPU = 1014,
276 ZYNQMP_PM_RESET_GT = 1015,
277 ZYNQMP_PM_RESET_SATA = 1016,
278 ZYNQMP_PM_RESET_ACPU3_PWRON = 1017,
279 ZYNQMP_PM_RESET_ACPU2_PWRON = 1018,
280 ZYNQMP_PM_RESET_ACPU1_PWRON = 1019,
281 ZYNQMP_PM_RESET_ACPU0_PWRON = 1020,
282 ZYNQMP_PM_RESET_APU_L2 = 1021,
283 ZYNQMP_PM_RESET_ACPU3 = 1022,
284 ZYNQMP_PM_RESET_ACPU2 = 1023,
285 ZYNQMP_PM_RESET_ACPU1 = 1024,
286 ZYNQMP_PM_RESET_ACPU0 = 1025,
287 ZYNQMP_PM_RESET_DDR = 1026,
288 ZYNQMP_PM_RESET_APM_FPD = 1027,
289 ZYNQMP_PM_RESET_SOFT = 1028,
290 ZYNQMP_PM_RESET_GEM0 = 1029,
291 ZYNQMP_PM_RESET_GEM1 = 1030,
292 ZYNQMP_PM_RESET_GEM2 = 1031,
293 ZYNQMP_PM_RESET_GEM3 = 1032,
294 ZYNQMP_PM_RESET_QSPI = 1033,
295 ZYNQMP_PM_RESET_UART0 = 1034,
296 ZYNQMP_PM_RESET_UART1 = 1035,
297 ZYNQMP_PM_RESET_SPI0 = 1036,
298 ZYNQMP_PM_RESET_SPI1 = 1037,
299 ZYNQMP_PM_RESET_SDIO0 = 1038,
300 ZYNQMP_PM_RESET_SDIO1 = 1039,
301 ZYNQMP_PM_RESET_CAN0 = 1040,
302 ZYNQMP_PM_RESET_CAN1 = 1041,
303 ZYNQMP_PM_RESET_I2C0 = 1042,
304 ZYNQMP_PM_RESET_I2C1 = 1043,
305 ZYNQMP_PM_RESET_TTC0 = 1044,
306 ZYNQMP_PM_RESET_TTC1 = 1045,
307 ZYNQMP_PM_RESET_TTC2 = 1046,
308 ZYNQMP_PM_RESET_TTC3 = 1047,
309 ZYNQMP_PM_RESET_SWDT_CRL = 1048,
310 ZYNQMP_PM_RESET_NAND = 1049,
311 ZYNQMP_PM_RESET_ADMA = 1050,
312 ZYNQMP_PM_RESET_GPIO = 1051,
313 ZYNQMP_PM_RESET_IOU_CC = 1052,
314 ZYNQMP_PM_RESET_TIMESTAMP = 1053,
315 ZYNQMP_PM_RESET_RPU_R50 = 1054,
316 ZYNQMP_PM_RESET_RPU_R51 = 1055,
317 ZYNQMP_PM_RESET_RPU_AMBA = 1056,
318 ZYNQMP_PM_RESET_OCM = 1057,
319 ZYNQMP_PM_RESET_RPU_PGE = 1058,
320 ZYNQMP_PM_RESET_USB0_CORERESET = 1059,
321 ZYNQMP_PM_RESET_USB1_CORERESET = 1060,
322 ZYNQMP_PM_RESET_USB0_HIBERRESET = 1061,
323 ZYNQMP_PM_RESET_USB1_HIBERRESET = 1062,
324 ZYNQMP_PM_RESET_USB0_APB = 1063,
325 ZYNQMP_PM_RESET_USB1_APB = 1064,
326 ZYNQMP_PM_RESET_IPI = 1065,
327 ZYNQMP_PM_RESET_APM_LPD = 1066,
328 ZYNQMP_PM_RESET_RTC = 1067,
329 ZYNQMP_PM_RESET_SYSMON = 1068,
330 ZYNQMP_PM_RESET_AFI_FM6 = 1069,
331 ZYNQMP_PM_RESET_LPD_SWDT = 1070,
332 ZYNQMP_PM_RESET_FPD = 1071,
333 ZYNQMP_PM_RESET_RPU_DBG1 = 1072,
334 ZYNQMP_PM_RESET_RPU_DBG0 = 1073,
335 ZYNQMP_PM_RESET_DBG_LPD = 1074,
336 ZYNQMP_PM_RESET_DBG_FPD = 1075,
337 ZYNQMP_PM_RESET_APLL = 1076,
338 ZYNQMP_PM_RESET_DPLL = 1077,
339 ZYNQMP_PM_RESET_VPLL = 1078,
340 ZYNQMP_PM_RESET_IOPLL = 1079,
341 ZYNQMP_PM_RESET_RPLL = 1080,
342 ZYNQMP_PM_RESET_GPO3_PL_0 = 1081,
343 ZYNQMP_PM_RESET_GPO3_PL_1 = 1082,
344 ZYNQMP_PM_RESET_GPO3_PL_2 = 1083,
345 ZYNQMP_PM_RESET_GPO3_PL_3 = 1084,
346 ZYNQMP_PM_RESET_GPO3_PL_4 = 1085,
347 ZYNQMP_PM_RESET_GPO3_PL_5 = 1086,
348 ZYNQMP_PM_RESET_GPO3_PL_6 = 1087,
349 ZYNQMP_PM_RESET_GPO3_PL_7 = 1088,
350 ZYNQMP_PM_RESET_GPO3_PL_8 = 1089,
351 ZYNQMP_PM_RESET_GPO3_PL_9 = 1090,
352 ZYNQMP_PM_RESET_GPO3_PL_10 = 1091,
353 ZYNQMP_PM_RESET_GPO3_PL_11 = 1092,
354 ZYNQMP_PM_RESET_GPO3_PL_12 = 1093,
355 ZYNQMP_PM_RESET_GPO3_PL_13 = 1094,
356 ZYNQMP_PM_RESET_GPO3_PL_14 = 1095,
357 ZYNQMP_PM_RESET_GPO3_PL_15 = 1096,
358 ZYNQMP_PM_RESET_GPO3_PL_16 = 1097,
359 ZYNQMP_PM_RESET_GPO3_PL_17 = 1098,
360 ZYNQMP_PM_RESET_GPO3_PL_18 = 1099,
361 ZYNQMP_PM_RESET_GPO3_PL_19 = 1100,
362 ZYNQMP_PM_RESET_GPO3_PL_20 = 1101,
363 ZYNQMP_PM_RESET_GPO3_PL_21 = 1102,
364 ZYNQMP_PM_RESET_GPO3_PL_22 = 1103,
365 ZYNQMP_PM_RESET_GPO3_PL_23 = 1104,
366 ZYNQMP_PM_RESET_GPO3_PL_24 = 1105,
367 ZYNQMP_PM_RESET_GPO3_PL_25 = 1106,
368 ZYNQMP_PM_RESET_GPO3_PL_26 = 1107,
369 ZYNQMP_PM_RESET_GPO3_PL_27 = 1108,
370 ZYNQMP_PM_RESET_GPO3_PL_28 = 1109,
371 ZYNQMP_PM_RESET_GPO3_PL_29 = 1110,
372 ZYNQMP_PM_RESET_GPO3_PL_30 = 1111,
373 ZYNQMP_PM_RESET_GPO3_PL_31 = 1112,
374 ZYNQMP_PM_RESET_RPU_LS = 1113,
375 ZYNQMP_PM_RESET_PS_ONLY = 1114,
376 ZYNQMP_PM_RESET_PL = 1115,
377 ZYNQMP_PM_RESET_PS_PL0 = 1116,
378 ZYNQMP_PM_RESET_PS_PL1 = 1117,
379 ZYNQMP_PM_RESET_PS_PL2 = 1118,
380 ZYNQMP_PM_RESET_PS_PL3 = 1119,
381 ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
382 };
383
384 enum zynqmp_pm_suspend_reason {
385 SUSPEND_POWER_REQUEST = 201,
386 SUSPEND_ALERT = 202,
387 SUSPEND_SYSTEM_SHUTDOWN = 203,
388 };
389
390 enum zynqmp_pm_request_ack {
391 ZYNQMP_PM_REQUEST_ACK_NO = 1,
392 ZYNQMP_PM_REQUEST_ACK_BLOCKING = 2,
393 ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING = 3,
394 };
395
396 enum pm_node_id {
397 NODE_SD_0 = 39,
398 NODE_SD_1 = 40,
399 };
400
401 enum tap_delay_type {
402 PM_TAPDELAY_INPUT = 0,
403 PM_TAPDELAY_OUTPUT = 1,
404 };
405
406 enum dll_reset_type {
407 PM_DLL_RESET_ASSERT = 0,
408 PM_DLL_RESET_RELEASE = 1,
409 PM_DLL_RESET_PULSE = 2,
410 };
411
412 enum pm_pinctrl_config_param {
413 PM_PINCTRL_CONFIG_SLEW_RATE = 0,
414 PM_PINCTRL_CONFIG_BIAS_STATUS = 1,
415 PM_PINCTRL_CONFIG_PULL_CTRL = 2,
416 PM_PINCTRL_CONFIG_SCHMITT_CMOS = 3,
417 PM_PINCTRL_CONFIG_DRIVE_STRENGTH = 4,
418 PM_PINCTRL_CONFIG_VOLTAGE_STATUS = 5,
419 PM_PINCTRL_CONFIG_TRI_STATE = 6,
420 PM_PINCTRL_CONFIG_MAX = 7,
421 };
422
423 enum pm_pinctrl_slew_rate {
424 PM_PINCTRL_SLEW_RATE_FAST = 0,
425 PM_PINCTRL_SLEW_RATE_SLOW = 1,
426 };
427
428 enum pm_pinctrl_bias_status {
429 PM_PINCTRL_BIAS_DISABLE = 0,
430 PM_PINCTRL_BIAS_ENABLE = 1,
431 };
432
433 enum pm_pinctrl_pull_ctrl {
434 PM_PINCTRL_BIAS_PULL_DOWN = 0,
435 PM_PINCTRL_BIAS_PULL_UP = 1,
436 };
437
438 enum pm_pinctrl_schmitt_cmos {
439 PM_PINCTRL_INPUT_TYPE_CMOS = 0,
440 PM_PINCTRL_INPUT_TYPE_SCHMITT = 1,
441 };
442
443 enum pm_pinctrl_drive_strength {
444 PM_PINCTRL_DRIVE_STRENGTH_2MA = 0,
445 PM_PINCTRL_DRIVE_STRENGTH_4MA = 1,
446 PM_PINCTRL_DRIVE_STRENGTH_8MA = 2,
447 PM_PINCTRL_DRIVE_STRENGTH_12MA = 3,
448 };
449
450 enum pm_pinctrl_tri_state {
451 PM_PINCTRL_TRI_STATE_DISABLE = 0,
452 PM_PINCTRL_TRI_STATE_ENABLE = 1,
453 };
454
455 enum zynqmp_pm_shutdown_type {
456 ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN = 0,
457 ZYNQMP_PM_SHUTDOWN_TYPE_RESET = 1,
458 ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY = 2,
459 };
460
461 enum zynqmp_pm_shutdown_subtype {
462 ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM = 0,
463 ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY = 1,
464 ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM = 2,
465 };
466
467 enum tap_delay_signal_type {
468 PM_TAPDELAY_NAND_DQS_IN = 0,
469 PM_TAPDELAY_NAND_DQS_OUT = 1,
470 PM_TAPDELAY_QSPI = 2,
471 PM_TAPDELAY_MAX = 3,
472 };
473
474 enum tap_delay_bypass_ctrl {
475 PM_TAPDELAY_BYPASS_DISABLE = 0,
476 PM_TAPDELAY_BYPASS_ENABLE = 1,
477 };
478
479 enum ospi_mux_select_type {
480 PM_OSPI_MUX_SEL_DMA = 0,
481 PM_OSPI_MUX_SEL_LINEAR = 1,
482 };
483
484 enum pm_feature_config_id {
485 PM_FEATURE_INVALID = 0,
486 PM_FEATURE_OVERTEMP_STATUS = 1,
487 PM_FEATURE_OVERTEMP_VALUE = 2,
488 PM_FEATURE_EXTWDT_STATUS = 3,
489 PM_FEATURE_EXTWDT_VALUE = 4,
490 };
491
492 /**
493 * enum pm_sd_config_type - PM SD configuration.
494 * @SD_CONFIG_EMMC_SEL: To set SD_EMMC_SEL in CTRL_REG_SD and SD_SLOTTYPE
495 * @SD_CONFIG_BASECLK: To set SD_BASECLK in SD_CONFIG_REG1
496 * @SD_CONFIG_8BIT: To set SD_8BIT in SD_CONFIG_REG2
497 * @SD_CONFIG_FIXED: To set fixed config registers
498 */
499 enum pm_sd_config_type {
500 SD_CONFIG_EMMC_SEL = 1,
501 SD_CONFIG_BASECLK = 2,
502 SD_CONFIG_8BIT = 3,
503 SD_CONFIG_FIXED = 4,
504 };
505
506 /**
507 * enum pm_gem_config_type - PM GEM configuration.
508 * @GEM_CONFIG_SGMII_MODE: To set GEM_SGMII_MODE in GEM_CLK_CTRL register
509 * @GEM_CONFIG_FIXED: To set fixed config registers
510 */
511 enum pm_gem_config_type {
512 GEM_CONFIG_SGMII_MODE = 1,
513 GEM_CONFIG_FIXED = 2,
514 };
515
516 /**
517 * struct zynqmp_pm_query_data - PM query data
518 * @qid: query ID
519 * @arg1: Argument 1 of query data
520 * @arg2: Argument 2 of query data
521 * @arg3: Argument 3 of query data
522 */
523 struct zynqmp_pm_query_data {
524 u32 qid;
525 u32 arg1;
526 u32 arg2;
527 u32 arg3;
528 };
529
530 int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 *ret_payload, u32 num_args, ...);
531
532 #if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE)
533 int zynqmp_pm_get_api_version(u32 *version);
534 int zynqmp_pm_get_chipid(u32 *idcode, u32 *version);
535 int zynqmp_pm_get_family_info(u32 *family, u32 *subfamily);
536 int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out);
537 int zynqmp_pm_clock_enable(u32 clock_id);
538 int zynqmp_pm_clock_disable(u32 clock_id);
539 int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state);
540 int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider);
541 int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider);
542 int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id);
543 int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id);
544 int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode);
545 int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode);
546 int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data);
547 int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data);
548 int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value);
549 int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type);
550 int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select);
551 int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
552 const enum zynqmp_pm_reset_action assert_flag);
553 int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, u32 *status);
554 unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode);
555 int zynqmp_pm_bootmode_write(u32 ps_mode);
556 int zynqmp_pm_init_finalize(void);
557 int zynqmp_pm_set_suspend_mode(u32 mode);
558 int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
559 const u32 qos, const enum zynqmp_pm_request_ack ack);
560 int zynqmp_pm_release_node(const u32 node);
561 int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
562 const u32 qos,
563 const enum zynqmp_pm_request_ack ack);
564 int zynqmp_pm_aes_engine(const u64 address, u32 *out);
565 int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags);
566 int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags);
567 int zynqmp_pm_fpga_get_status(u32 *value);
568 int zynqmp_pm_fpga_get_config_status(u32 *value);
569 int zynqmp_pm_write_ggs(u32 index, u32 value);
570 int zynqmp_pm_read_ggs(u32 index, u32 *value);
571 int zynqmp_pm_write_pggs(u32 index, u32 value);
572 int zynqmp_pm_read_pggs(u32 index, u32 *value);
573 int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value);
574 int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
575 int zynqmp_pm_set_boot_health_status(u32 value);
576 int zynqmp_pm_pinctrl_request(const u32 pin);
577 int zynqmp_pm_pinctrl_release(const u32 pin);
578 int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id);
579 int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
580 u32 *value);
581 int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
582 u32 value);
583 int zynqmp_pm_load_pdi(const u32 src, const u64 address);
584 int zynqmp_pm_register_notifier(const u32 node, const u32 event,
585 const u32 wake, const u32 enable);
586 int zynqmp_pm_feature(const u32 api_id);
587 int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id);
588 int zynqmp_pm_set_feature_config(enum pm_feature_config_id id, u32 value);
589 int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, u32 *payload);
590 int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset);
591 int zynqmp_pm_force_pwrdwn(const u32 target,
592 const enum zynqmp_pm_request_ack ack);
593 int zynqmp_pm_request_wake(const u32 node,
594 const bool set_addr,
595 const u64 address,
596 const enum zynqmp_pm_request_ack ack);
597 int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode);
598 int zynqmp_pm_set_rpu_mode(u32 node_id, enum rpu_oper_mode rpu_mode);
599 int zynqmp_pm_set_tcm_config(u32 node_id, enum rpu_tcm_comb tcm_mode);
600 int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value);
601 int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config,
602 u32 value);
603 #else
zynqmp_pm_get_api_version(u32 * version)604 static inline int zynqmp_pm_get_api_version(u32 *version)
605 {
606 return -ENODEV;
607 }
608
zynqmp_pm_get_chipid(u32 * idcode,u32 * version)609 static inline int zynqmp_pm_get_chipid(u32 *idcode, u32 *version)
610 {
611 return -ENODEV;
612 }
613
zynqmp_pm_get_family_info(u32 * family,u32 * subfamily)614 static inline int zynqmp_pm_get_family_info(u32 *family, u32 *subfamily)
615 {
616 return -ENODEV;
617 }
618
zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata,u32 * out)619 static inline int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata,
620 u32 *out)
621 {
622 return -ENODEV;
623 }
624
zynqmp_pm_clock_enable(u32 clock_id)625 static inline int zynqmp_pm_clock_enable(u32 clock_id)
626 {
627 return -ENODEV;
628 }
629
zynqmp_pm_clock_disable(u32 clock_id)630 static inline int zynqmp_pm_clock_disable(u32 clock_id)
631 {
632 return -ENODEV;
633 }
634
zynqmp_pm_clock_getstate(u32 clock_id,u32 * state)635 static inline int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state)
636 {
637 return -ENODEV;
638 }
639
zynqmp_pm_clock_setdivider(u32 clock_id,u32 divider)640 static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider)
641 {
642 return -ENODEV;
643 }
644
zynqmp_pm_clock_getdivider(u32 clock_id,u32 * divider)645 static inline int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider)
646 {
647 return -ENODEV;
648 }
649
zynqmp_pm_clock_setparent(u32 clock_id,u32 parent_id)650 static inline int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id)
651 {
652 return -ENODEV;
653 }
654
zynqmp_pm_clock_getparent(u32 clock_id,u32 * parent_id)655 static inline int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id)
656 {
657 return -ENODEV;
658 }
659
zynqmp_pm_set_pll_frac_mode(u32 clk_id,u32 mode)660 static inline int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode)
661 {
662 return -ENODEV;
663 }
664
zynqmp_pm_get_pll_frac_mode(u32 clk_id,u32 * mode)665 static inline int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode)
666 {
667 return -ENODEV;
668 }
669
zynqmp_pm_set_pll_frac_data(u32 clk_id,u32 data)670 static inline int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data)
671 {
672 return -ENODEV;
673 }
674
zynqmp_pm_get_pll_frac_data(u32 clk_id,u32 * data)675 static inline int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data)
676 {
677 return -ENODEV;
678 }
679
zynqmp_pm_set_sd_tapdelay(u32 node_id,u32 type,u32 value)680 static inline int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value)
681 {
682 return -ENODEV;
683 }
684
zynqmp_pm_sd_dll_reset(u32 node_id,u32 type)685 static inline int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type)
686 {
687 return -ENODEV;
688 }
689
zynqmp_pm_ospi_mux_select(u32 dev_id,u32 select)690 static inline int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select)
691 {
692 return -ENODEV;
693 }
694
zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,const enum zynqmp_pm_reset_action assert_flag)695 static inline int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
696 const enum zynqmp_pm_reset_action assert_flag)
697 {
698 return -ENODEV;
699 }
700
zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset,u32 * status)701 static inline int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset,
702 u32 *status)
703 {
704 return -ENODEV;
705 }
706
zynqmp_pm_bootmode_read(u32 * ps_mode)707 static inline unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode)
708 {
709 return -ENODEV;
710 }
711
zynqmp_pm_bootmode_write(u32 ps_mode)712 static inline int zynqmp_pm_bootmode_write(u32 ps_mode)
713 {
714 return -ENODEV;
715 }
716
zynqmp_pm_init_finalize(void)717 static inline int zynqmp_pm_init_finalize(void)
718 {
719 return -ENODEV;
720 }
721
zynqmp_pm_set_suspend_mode(u32 mode)722 static inline int zynqmp_pm_set_suspend_mode(u32 mode)
723 {
724 return -ENODEV;
725 }
726
zynqmp_pm_request_node(const u32 node,const u32 capabilities,const u32 qos,const enum zynqmp_pm_request_ack ack)727 static inline int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
728 const u32 qos,
729 const enum zynqmp_pm_request_ack ack)
730 {
731 return -ENODEV;
732 }
733
zynqmp_pm_release_node(const u32 node)734 static inline int zynqmp_pm_release_node(const u32 node)
735 {
736 return -ENODEV;
737 }
738
zynqmp_pm_set_requirement(const u32 node,const u32 capabilities,const u32 qos,const enum zynqmp_pm_request_ack ack)739 static inline int zynqmp_pm_set_requirement(const u32 node,
740 const u32 capabilities,
741 const u32 qos,
742 const enum zynqmp_pm_request_ack ack)
743 {
744 return -ENODEV;
745 }
746
zynqmp_pm_aes_engine(const u64 address,u32 * out)747 static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out)
748 {
749 return -ENODEV;
750 }
751
zynqmp_pm_sha_hash(const u64 address,const u32 size,const u32 flags)752 static inline int zynqmp_pm_sha_hash(const u64 address, const u32 size,
753 const u32 flags)
754 {
755 return -ENODEV;
756 }
757
zynqmp_pm_fpga_load(const u64 address,const u32 size,const u32 flags)758 static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size,
759 const u32 flags)
760 {
761 return -ENODEV;
762 }
763
zynqmp_pm_fpga_get_status(u32 * value)764 static inline int zynqmp_pm_fpga_get_status(u32 *value)
765 {
766 return -ENODEV;
767 }
768
zynqmp_pm_fpga_get_config_status(u32 * value)769 static inline int zynqmp_pm_fpga_get_config_status(u32 *value)
770 {
771 return -ENODEV;
772 }
773
zynqmp_pm_write_ggs(u32 index,u32 value)774 static inline int zynqmp_pm_write_ggs(u32 index, u32 value)
775 {
776 return -ENODEV;
777 }
778
zynqmp_pm_read_ggs(u32 index,u32 * value)779 static inline int zynqmp_pm_read_ggs(u32 index, u32 *value)
780 {
781 return -ENODEV;
782 }
783
zynqmp_pm_write_pggs(u32 index,u32 value)784 static inline int zynqmp_pm_write_pggs(u32 index, u32 value)
785 {
786 return -ENODEV;
787 }
788
zynqmp_pm_read_pggs(u32 index,u32 * value)789 static inline int zynqmp_pm_read_pggs(u32 index, u32 *value)
790 {
791 return -ENODEV;
792 }
793
zynqmp_pm_set_tapdelay_bypass(u32 index,u32 value)794 static inline int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value)
795 {
796 return -ENODEV;
797 }
798
zynqmp_pm_system_shutdown(const u32 type,const u32 subtype)799 static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype)
800 {
801 return -ENODEV;
802 }
803
zynqmp_pm_set_boot_health_status(u32 value)804 static inline int zynqmp_pm_set_boot_health_status(u32 value)
805 {
806 return -ENODEV;
807 }
808
zynqmp_pm_pinctrl_request(const u32 pin)809 static inline int zynqmp_pm_pinctrl_request(const u32 pin)
810 {
811 return -ENODEV;
812 }
813
zynqmp_pm_pinctrl_release(const u32 pin)814 static inline int zynqmp_pm_pinctrl_release(const u32 pin)
815 {
816 return -ENODEV;
817 }
818
zynqmp_pm_is_function_supported(const u32 api_id,const u32 id)819 static inline int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id)
820 {
821 return -ENODEV;
822 }
823
zynqmp_pm_pinctrl_set_function(const u32 pin,const u32 id)824 static inline int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id)
825 {
826 return -ENODEV;
827 }
828
zynqmp_pm_pinctrl_get_config(const u32 pin,const u32 param,u32 * value)829 static inline int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
830 u32 *value)
831 {
832 return -ENODEV;
833 }
834
zynqmp_pm_pinctrl_set_config(const u32 pin,const u32 param,u32 value)835 static inline int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
836 u32 value)
837 {
838 return -ENODEV;
839 }
840
zynqmp_pm_load_pdi(const u32 src,const u64 address)841 static inline int zynqmp_pm_load_pdi(const u32 src, const u64 address)
842 {
843 return -ENODEV;
844 }
845
zynqmp_pm_register_notifier(const u32 node,const u32 event,const u32 wake,const u32 enable)846 static inline int zynqmp_pm_register_notifier(const u32 node, const u32 event,
847 const u32 wake, const u32 enable)
848 {
849 return -ENODEV;
850 }
851
zynqmp_pm_feature(const u32 api_id)852 static inline int zynqmp_pm_feature(const u32 api_id)
853 {
854 return -ENODEV;
855 }
856
zynqmp_pm_set_feature_config(enum pm_feature_config_id id,u32 value)857 static inline int zynqmp_pm_set_feature_config(enum pm_feature_config_id id,
858 u32 value)
859 {
860 return -ENODEV;
861 }
862
zynqmp_pm_get_feature_config(enum pm_feature_config_id id,u32 * payload)863 static inline int zynqmp_pm_get_feature_config(enum pm_feature_config_id id,
864 u32 *payload)
865 {
866 return -ENODEV;
867 }
868
zynqmp_pm_register_sgi(u32 sgi_num,u32 reset)869 static inline int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset)
870 {
871 return -ENODEV;
872 }
873
zynqmp_pm_force_pwrdwn(const u32 target,const enum zynqmp_pm_request_ack ack)874 static inline int zynqmp_pm_force_pwrdwn(const u32 target,
875 const enum zynqmp_pm_request_ack ack)
876 {
877 return -ENODEV;
878 }
879
zynqmp_pm_request_wake(const u32 node,const bool set_addr,const u64 address,const enum zynqmp_pm_request_ack ack)880 static inline int zynqmp_pm_request_wake(const u32 node,
881 const bool set_addr,
882 const u64 address,
883 const enum zynqmp_pm_request_ack ack)
884 {
885 return -ENODEV;
886 }
887
zynqmp_pm_get_rpu_mode(u32 node_id,enum rpu_oper_mode * rpu_mode)888 static inline int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode)
889 {
890 return -ENODEV;
891 }
892
zynqmp_pm_set_rpu_mode(u32 node_id,enum rpu_oper_mode rpu_mode)893 static inline int zynqmp_pm_set_rpu_mode(u32 node_id, enum rpu_oper_mode rpu_mode)
894 {
895 return -ENODEV;
896 }
897
zynqmp_pm_set_tcm_config(u32 node_id,enum rpu_tcm_comb tcm_mode)898 static inline int zynqmp_pm_set_tcm_config(u32 node_id, enum rpu_tcm_comb tcm_mode)
899 {
900 return -ENODEV;
901 }
902
zynqmp_pm_set_sd_config(u32 node,enum pm_sd_config_type config,u32 value)903 static inline int zynqmp_pm_set_sd_config(u32 node,
904 enum pm_sd_config_type config,
905 u32 value)
906 {
907 return -ENODEV;
908 }
909
zynqmp_pm_set_gem_config(u32 node,enum pm_gem_config_type config,u32 value)910 static inline int zynqmp_pm_set_gem_config(u32 node,
911 enum pm_gem_config_type config,
912 u32 value)
913 {
914 return -ENODEV;
915 }
916
917 #endif
918
919 #endif /* __FIRMWARE_ZYNQMP_H__ */
920