1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * Copyright (C) 2022-2024, Advanced Micro Devices, Inc. 4 */ 5 6 #ifndef _UAPI_AMDXDNA_ACCEL_H_ 7 #define _UAPI_AMDXDNA_ACCEL_H_ 8 9 #include <linux/stddef.h> 10 #include "drm.h" 11 12 #if defined(__cplusplus) 13 extern "C" { 14 #endif 15 16 #define AMDXDNA_INVALID_CMD_HANDLE (~0UL) 17 #define AMDXDNA_INVALID_ADDR (~0UL) 18 #define AMDXDNA_INVALID_CTX_HANDLE 0 19 #define AMDXDNA_INVALID_BO_HANDLE 0 20 #define AMDXDNA_INVALID_FENCE_HANDLE 0 21 22 /* 23 * Define hardware context priority 24 */ 25 #define AMDXDNA_QOS_REALTIME_PRIORITY 0x100 26 #define AMDXDNA_QOS_HIGH_PRIORITY 0x180 27 #define AMDXDNA_QOS_NORMAL_PRIORITY 0x200 28 #define AMDXDNA_QOS_LOW_PRIORITY 0x280 29 30 enum amdxdna_device_type { 31 AMDXDNA_DEV_TYPE_UNKNOWN = -1, 32 AMDXDNA_DEV_TYPE_KMQ, 33 }; 34 35 enum amdxdna_drm_ioctl_id { 36 DRM_AMDXDNA_CREATE_HWCTX, 37 DRM_AMDXDNA_DESTROY_HWCTX, 38 DRM_AMDXDNA_CONFIG_HWCTX, 39 DRM_AMDXDNA_CREATE_BO, 40 DRM_AMDXDNA_GET_BO_INFO, 41 DRM_AMDXDNA_SYNC_BO, 42 DRM_AMDXDNA_EXEC_CMD, 43 DRM_AMDXDNA_GET_INFO, 44 DRM_AMDXDNA_SET_STATE, 45 DRM_AMDXDNA_GET_ARRAY = 10, 46 }; 47 48 /** 49 * struct qos_info - QoS information for driver. 50 * @gops: Giga operations per second. 51 * @fps: Frames per second. 52 * @dma_bandwidth: DMA bandwidtha. 53 * @latency: Frame response latency. 54 * @frame_exec_time: Frame execution time. 55 * @priority: Request priority. 56 * 57 * User program can provide QoS hints to driver. 58 */ 59 struct amdxdna_qos_info { 60 __u32 gops; 61 __u32 fps; 62 __u32 dma_bandwidth; 63 __u32 latency; 64 __u32 frame_exec_time; 65 __u32 priority; 66 }; 67 68 /** 69 * struct amdxdna_drm_create_hwctx - Create hardware context. 70 * @ext: MBZ. 71 * @ext_flags: MBZ. 72 * @qos_p: Address of QoS info. 73 * @umq_bo: BO handle for user mode queue(UMQ). 74 * @log_buf_bo: BO handle for log buffer. 75 * @max_opc: Maximum operations per cycle. 76 * @num_tiles: Number of AIE tiles. 77 * @mem_size: Size of AIE tile memory. 78 * @umq_doorbell: Returned offset of doorbell associated with UMQ. 79 * @handle: Returned hardware context handle. 80 * @syncobj_handle: Returned syncobj handle for command completion. 81 */ 82 struct amdxdna_drm_create_hwctx { 83 __u64 ext; 84 __u64 ext_flags; 85 __u64 qos_p; 86 __u32 umq_bo; 87 __u32 log_buf_bo; 88 __u32 max_opc; 89 __u32 num_tiles; 90 __u32 mem_size; 91 __u32 umq_doorbell; 92 __u32 handle; 93 __u32 syncobj_handle; 94 }; 95 96 /** 97 * struct amdxdna_drm_destroy_hwctx - Destroy hardware context. 98 * @handle: Hardware context handle. 99 * @pad: MBZ. 100 */ 101 struct amdxdna_drm_destroy_hwctx { 102 __u32 handle; 103 __u32 pad; 104 }; 105 106 /** 107 * struct amdxdna_cu_config - configuration for one CU 108 * @cu_bo: CU configuration buffer bo handle. 109 * @cu_func: Function of a CU. 110 * @pad: MBZ. 111 */ 112 struct amdxdna_cu_config { 113 __u32 cu_bo; 114 __u8 cu_func; 115 __u8 pad[3]; 116 }; 117 118 /** 119 * struct amdxdna_hwctx_param_config_cu - configuration for CUs in hardware context 120 * @num_cus: Number of CUs to configure. 121 * @pad: MBZ. 122 * @cu_configs: Array of CU configurations of struct amdxdna_cu_config. 123 */ 124 struct amdxdna_hwctx_param_config_cu { 125 __u16 num_cus; 126 __u16 pad[3]; 127 struct amdxdna_cu_config cu_configs[] __counted_by(num_cus); 128 }; 129 130 enum amdxdna_drm_config_hwctx_param { 131 DRM_AMDXDNA_HWCTX_CONFIG_CU, 132 DRM_AMDXDNA_HWCTX_ASSIGN_DBG_BUF, 133 DRM_AMDXDNA_HWCTX_REMOVE_DBG_BUF, 134 }; 135 136 /** 137 * struct amdxdna_drm_config_hwctx - Configure hardware context. 138 * @handle: hardware context handle. 139 * @param_type: Value in enum amdxdna_drm_config_hwctx_param. Specifies the 140 * structure passed in via param_val. 141 * @param_val: A structure specified by the param_type struct member. 142 * @param_val_size: Size of the parameter buffer pointed to by the param_val. 143 * If param_val is not a pointer, driver can ignore this. 144 * @pad: MBZ. 145 * 146 * Note: if the param_val is a pointer pointing to a buffer, the maximum size 147 * of the buffer is 4KiB(PAGE_SIZE). 148 */ 149 struct amdxdna_drm_config_hwctx { 150 __u32 handle; 151 __u32 param_type; 152 __u64 param_val; 153 __u32 param_val_size; 154 __u32 pad; 155 }; 156 157 enum amdxdna_bo_type { 158 AMDXDNA_BO_INVALID = 0, 159 AMDXDNA_BO_SHMEM = 1, /* Be compatible with legacy application code. */ 160 AMDXDNA_BO_SHARE = 1, 161 AMDXDNA_BO_DEV_HEAP = 2, 162 AMDXDNA_BO_DEV = 3, 163 AMDXDNA_BO_CMD = 4, 164 }; 165 166 /** 167 * struct amdxdna_drm_va_entry 168 * @vaddr: Virtual address. 169 * @len: Size of entry. 170 */ 171 struct amdxdna_drm_va_entry { 172 __u64 vaddr; 173 __u64 len; 174 }; 175 176 /** 177 * struct amdxdna_drm_va_tbl 178 * @dmabuf_fd: The fd of dmabuf. 179 * @num_entries: Number of va entries. 180 * @va_entries: Array of va entries. 181 * 182 * The input can be either a dmabuf fd or a virtual address entry table. 183 * When dmabuf_fd is used, num_entries must be zero. 184 */ 185 struct amdxdna_drm_va_tbl { 186 __s32 dmabuf_fd; 187 __u32 num_entries; 188 struct amdxdna_drm_va_entry va_entries[]; 189 }; 190 191 /** 192 * struct amdxdna_drm_create_bo - Create a buffer object. 193 * @flags: Buffer flags. MBZ. 194 * @vaddr: User VA of buffer if applied. MBZ. 195 * @size: Size in bytes. 196 * @type: Buffer type. 197 * @handle: Returned DRM buffer object handle. 198 */ 199 struct amdxdna_drm_create_bo { 200 __u64 flags; 201 __u64 vaddr; 202 __u64 size; 203 __u32 type; 204 __u32 handle; 205 }; 206 207 /** 208 * struct amdxdna_drm_get_bo_info - Get buffer object information. 209 * @ext: MBZ. 210 * @ext_flags: MBZ. 211 * @handle: DRM buffer object handle. 212 * @pad: MBZ. 213 * @map_offset: Returned DRM fake offset for mmap(). 214 * @vaddr: Returned user VA of buffer. 0 in case user needs mmap(). 215 * @xdna_addr: Returned XDNA device virtual address. 216 */ 217 struct amdxdna_drm_get_bo_info { 218 __u64 ext; 219 __u64 ext_flags; 220 __u32 handle; 221 __u32 pad; 222 __u64 map_offset; 223 __u64 vaddr; 224 __u64 xdna_addr; 225 }; 226 227 /** 228 * struct amdxdna_drm_sync_bo - Sync buffer object. 229 * @handle: Buffer object handle. 230 * @direction: Direction of sync, can be from device or to device. 231 * @offset: Offset in the buffer to sync. 232 * @size: Size in bytes. 233 */ 234 struct amdxdna_drm_sync_bo { 235 __u32 handle; 236 #define SYNC_DIRECT_TO_DEVICE 0U 237 #define SYNC_DIRECT_FROM_DEVICE 1U 238 __u32 direction; 239 __u64 offset; 240 __u64 size; 241 }; 242 243 enum amdxdna_cmd_type { 244 AMDXDNA_CMD_SUBMIT_EXEC_BUF = 0, 245 AMDXDNA_CMD_SUBMIT_DEPENDENCY, 246 AMDXDNA_CMD_SUBMIT_SIGNAL, 247 }; 248 249 /** 250 * struct amdxdna_drm_exec_cmd - Execute command. 251 * @ext: MBZ. 252 * @ext_flags: MBZ. 253 * @hwctx: Hardware context handle. 254 * @type: One of command type in enum amdxdna_cmd_type. 255 * @cmd_handles: Array of command handles or the command handle itself 256 * in case of just one. 257 * @args: Array of arguments for all command handles. 258 * @cmd_count: Number of command handles in the cmd_handles array. 259 * @arg_count: Number of arguments in the args array. 260 * @seq: Returned sequence number for this command. 261 */ 262 struct amdxdna_drm_exec_cmd { 263 __u64 ext; 264 __u64 ext_flags; 265 __u32 hwctx; 266 __u32 type; 267 __u64 cmd_handles; 268 __u64 args; 269 __u32 cmd_count; 270 __u32 arg_count; 271 __u64 seq; 272 }; 273 274 /** 275 * struct amdxdna_drm_query_aie_status - Query the status of the AIE hardware 276 * @buffer: The user space buffer that will return the AIE status. 277 * @buffer_size: The size of the user space buffer. 278 * @cols_filled: A bitmap of AIE columns whose data has been returned in the buffer. 279 */ 280 struct amdxdna_drm_query_aie_status { 281 __u64 buffer; /* out */ 282 __u32 buffer_size; /* in */ 283 __u32 cols_filled; /* out */ 284 }; 285 286 /** 287 * struct amdxdna_drm_query_aie_version - Query the version of the AIE hardware 288 * @major: The major version number. 289 * @minor: The minor version number. 290 */ 291 struct amdxdna_drm_query_aie_version { 292 __u32 major; /* out */ 293 __u32 minor; /* out */ 294 }; 295 296 /** 297 * struct amdxdna_drm_query_aie_tile_metadata - Query the metadata of AIE tile (core, mem, shim) 298 * @row_count: The number of rows. 299 * @row_start: The starting row number. 300 * @dma_channel_count: The number of dma channels. 301 * @lock_count: The number of locks. 302 * @event_reg_count: The number of events. 303 * @pad: Structure padding. 304 */ 305 struct amdxdna_drm_query_aie_tile_metadata { 306 __u16 row_count; 307 __u16 row_start; 308 __u16 dma_channel_count; 309 __u16 lock_count; 310 __u16 event_reg_count; 311 __u16 pad[3]; 312 }; 313 314 /** 315 * struct amdxdna_drm_query_aie_metadata - Query the metadata of the AIE hardware 316 * @col_size: The size of a column in bytes. 317 * @cols: The total number of columns. 318 * @rows: The total number of rows. 319 * @version: The version of the AIE hardware. 320 * @core: The metadata for all core tiles. 321 * @mem: The metadata for all mem tiles. 322 * @shim: The metadata for all shim tiles. 323 */ 324 struct amdxdna_drm_query_aie_metadata { 325 __u32 col_size; 326 __u16 cols; 327 __u16 rows; 328 struct amdxdna_drm_query_aie_version version; 329 struct amdxdna_drm_query_aie_tile_metadata core; 330 struct amdxdna_drm_query_aie_tile_metadata mem; 331 struct amdxdna_drm_query_aie_tile_metadata shim; 332 }; 333 334 /** 335 * struct amdxdna_drm_query_clock - Metadata for a clock 336 * @name: The clock name. 337 * @freq_mhz: The clock frequency. 338 * @pad: Structure padding. 339 */ 340 struct amdxdna_drm_query_clock { 341 __u8 name[16]; 342 __u32 freq_mhz; 343 __u32 pad; 344 }; 345 346 /** 347 * struct amdxdna_drm_query_clock_metadata - Query metadata for clocks 348 * @mp_npu_clock: The metadata for MP-NPU clock. 349 * @h_clock: The metadata for H clock. 350 */ 351 struct amdxdna_drm_query_clock_metadata { 352 struct amdxdna_drm_query_clock mp_npu_clock; 353 struct amdxdna_drm_query_clock h_clock; 354 }; 355 356 enum amdxdna_sensor_type { 357 AMDXDNA_SENSOR_TYPE_POWER, 358 AMDXDNA_SENSOR_TYPE_COLUMN_UTILIZATION 359 }; 360 361 /** 362 * struct amdxdna_drm_query_sensor - The data for single sensor. 363 * @label: The name for a sensor. 364 * @input: The current value of the sensor. 365 * @max: The maximum value possible for the sensor. 366 * @average: The average value of the sensor. 367 * @highest: The highest recorded sensor value for this driver load for the sensor. 368 * @status: The sensor status. 369 * @units: The sensor units. 370 * @unitm: Translates value member variables into the correct unit via (pow(10, unitm) * value). 371 * @type: The sensor type from enum amdxdna_sensor_type. 372 * @pad: Structure padding. 373 */ 374 struct amdxdna_drm_query_sensor { 375 __u8 label[64]; 376 __u32 input; 377 __u32 max; 378 __u32 average; 379 __u32 highest; 380 __u8 status[64]; 381 __u8 units[16]; 382 __s8 unitm; 383 __u8 type; 384 __u8 pad[6]; 385 }; 386 387 /** 388 * struct amdxdna_drm_query_hwctx - The data for single context. 389 * @context_id: The ID for this context. 390 * @start_col: The starting column for the partition assigned to this context. 391 * @num_col: The number of columns in the partition assigned to this context. 392 * @pad: Structure padding. 393 * @pid: The Process ID of the process that created this context. 394 * @command_submissions: The number of commands submitted to this context. 395 * @command_completions: The number of commands completed by this context. 396 * @migrations: The number of times this context has been moved to a different partition. 397 * @preemptions: The number of times this context has been preempted by another context in the 398 * same partition. 399 * @errors: The errors for this context. 400 */ 401 struct amdxdna_drm_query_hwctx { 402 __u32 context_id; 403 __u32 start_col; 404 __u32 num_col; 405 __u32 pad; 406 __s64 pid; 407 __u64 command_submissions; 408 __u64 command_completions; 409 __u64 migrations; 410 __u64 preemptions; 411 __u64 errors; 412 }; 413 414 enum amdxdna_power_mode_type { 415 POWER_MODE_DEFAULT, /* Fallback to calculated DPM */ 416 POWER_MODE_LOW, /* Set frequency to lowest DPM */ 417 POWER_MODE_MEDIUM, /* Set frequency to medium DPM */ 418 POWER_MODE_HIGH, /* Set frequency to highest DPM */ 419 POWER_MODE_TURBO, /* Maximum power */ 420 }; 421 422 /** 423 * struct amdxdna_drm_get_power_mode - Get the configured power mode 424 * @power_mode: The mode type from enum amdxdna_power_mode_type 425 * @pad: Structure padding. 426 */ 427 struct amdxdna_drm_get_power_mode { 428 __u8 power_mode; 429 __u8 pad[7]; 430 }; 431 432 /** 433 * struct amdxdna_drm_query_firmware_version - Query the firmware version 434 * @major: The major version number 435 * @minor: The minor version number 436 * @patch: The patch level version number 437 * @build: The build ID 438 */ 439 struct amdxdna_drm_query_firmware_version { 440 __u32 major; /* out */ 441 __u32 minor; /* out */ 442 __u32 patch; /* out */ 443 __u32 build; /* out */ 444 }; 445 446 enum amdxdna_drm_get_param { 447 DRM_AMDXDNA_QUERY_AIE_STATUS, 448 DRM_AMDXDNA_QUERY_AIE_METADATA, 449 DRM_AMDXDNA_QUERY_AIE_VERSION, 450 DRM_AMDXDNA_QUERY_CLOCK_METADATA, 451 DRM_AMDXDNA_QUERY_SENSORS, 452 DRM_AMDXDNA_QUERY_HW_CONTEXTS, 453 DRM_AMDXDNA_QUERY_FIRMWARE_VERSION = 8, 454 DRM_AMDXDNA_GET_POWER_MODE, 455 DRM_AMDXDNA_QUERY_TELEMETRY, 456 DRM_AMDXDNA_GET_FORCE_PREEMPT_STATE, 457 DRM_AMDXDNA_QUERY_RESOURCE_INFO, 458 DRM_AMDXDNA_GET_FRAME_BOUNDARY_PREEMPT_STATE, 459 }; 460 461 /** 462 * struct amdxdna_drm_get_resource_info - Get resource information 463 */ 464 struct amdxdna_drm_get_resource_info { 465 /** @npu_clk_max: max H-Clocks */ 466 __u64 npu_clk_max; 467 /** @npu_tops_max: max TOPs */ 468 __u64 npu_tops_max; 469 /** @npu_task_max: max number of tasks */ 470 __u64 npu_task_max; 471 /** @npu_tops_curr: current TOPs */ 472 __u64 npu_tops_curr; 473 /** @npu_task_curr: current number of tasks */ 474 __u64 npu_task_curr; 475 }; 476 477 /** 478 * struct amdxdna_drm_attribute_state - State of an attribute 479 */ 480 struct amdxdna_drm_attribute_state { 481 /** @state: enabled or disabled */ 482 __u8 state; 483 /** @pad: MBZ */ 484 __u8 pad[7]; 485 }; 486 487 /** 488 * struct amdxdna_drm_query_telemetry_header - Telemetry data header 489 */ 490 struct amdxdna_drm_query_telemetry_header { 491 /** @major: Firmware telemetry interface major version number */ 492 __u32 major; 493 /** @minor: Firmware telemetry interface minor version number */ 494 __u32 minor; 495 /** @type: Telemetry query type */ 496 __u32 type; 497 /** @map_num_elements: Total number of elements in the map table */ 498 __u32 map_num_elements; 499 /** @map: Element map */ 500 __u32 map[]; 501 }; 502 503 /** 504 * struct amdxdna_drm_get_info - Get some information from the AIE hardware. 505 * @param: Value in enum amdxdna_drm_get_param. Specifies the structure passed in the buffer. 506 * @buffer_size: Size of the input buffer. Size needed/written by the kernel. 507 * @buffer: A structure specified by the param struct member. 508 */ 509 struct amdxdna_drm_get_info { 510 __u32 param; /* in */ 511 __u32 buffer_size; /* in/out */ 512 __u64 buffer; /* in/out */ 513 }; 514 515 #define AMDXDNA_HWCTX_STATE_IDLE 0 516 #define AMDXDNA_HWCTX_STATE_ACTIVE 1 517 518 /** 519 * struct amdxdna_drm_hwctx_entry - The hardware context array entry 520 */ 521 struct amdxdna_drm_hwctx_entry { 522 /** @context_id: Context ID. */ 523 __u32 context_id; 524 /** @start_col: Start AIE array column assigned to context. */ 525 __u32 start_col; 526 /** @num_col: Number of AIE array columns assigned to context. */ 527 __u32 num_col; 528 /** @hwctx_id: The real hardware context id. */ 529 __u32 hwctx_id; 530 /** @pid: ID of process which created this context. */ 531 __s64 pid; 532 /** @command_submissions: Number of commands submitted. */ 533 __u64 command_submissions; 534 /** @command_completions: Number of commands completed. */ 535 __u64 command_completions; 536 /** @migrations: Number of times been migrated. */ 537 __u64 migrations; 538 /** @preemptions: Number of times been preempted. */ 539 __u64 preemptions; 540 /** @errors: Number of errors happened. */ 541 __u64 errors; 542 /** @priority: Context priority. */ 543 __u64 priority; 544 /** @heap_usage: Usage of device heap buffer. */ 545 __u64 heap_usage; 546 /** @suspensions: Number of times been suspended. */ 547 __u64 suspensions; 548 /** 549 * @state: Context state. 550 * %AMDXDNA_HWCTX_STATE_IDLE 551 * %AMDXDNA_HWCTX_STATE_ACTIVE 552 */ 553 __u32 state; 554 /** @pasid: PASID been bound. */ 555 __u32 pasid; 556 /** @gops: Giga operations per second. */ 557 __u32 gops; 558 /** @fps: Frames per second. */ 559 __u32 fps; 560 /** @dma_bandwidth: DMA bandwidth. */ 561 __u32 dma_bandwidth; 562 /** @latency: Frame response latency. */ 563 __u32 latency; 564 /** @frame_exec_time: Frame execution time. */ 565 __u32 frame_exec_time; 566 /** @txn_op_idx: Index of last control code executed. */ 567 __u32 txn_op_idx; 568 /** @ctx_pc: Program counter. */ 569 __u32 ctx_pc; 570 /** @fatal_error_type: Fatal error type if context crashes. */ 571 __u32 fatal_error_type; 572 /** @fatal_error_exception_type: Firmware exception type. */ 573 __u32 fatal_error_exception_type; 574 /** @fatal_error_exception_pc: Firmware exception program counter. */ 575 __u32 fatal_error_exception_pc; 576 /** @fatal_error_app_module: Exception module name. */ 577 __u32 fatal_error_app_module; 578 /** @pad: Structure pad. */ 579 __u32 pad; 580 }; 581 582 /** 583 * struct amdxdna_async_error - XDNA async error structure 584 */ 585 struct amdxdna_async_error { 586 /** @err_code: Error code. */ 587 __u64 err_code; 588 /** @ts_us: Timestamp. */ 589 __u64 ts_us; 590 /** @ex_err_code: Extra error code */ 591 __u64 ex_err_code; 592 }; 593 594 /** 595 * struct amdxdna_drm_bo_usage - all types of BO usage 596 * BOs managed by XRT/SHIM/driver is counted as internal. 597 * Others are counted as external which are managed by applications. 598 * 599 * Among all types of BOs: 600 * AMDXDNA_BO_DEV_HEAP - is counted for internal. 601 * AMDXDNA_BO_SHARE - is counted for external. 602 * AMDXDNA_BO_CMD - is counted for internal. 603 * AMDXDNA_BO_DEV - is counted by heap_usage only, not internal 604 * or external. It does not add to the total memory 605 * footprint since its mem comes from heap which is 606 * already counted as internal. 607 */ 608 struct amdxdna_drm_bo_usage { 609 /** @pid: The ID of the process to query from. */ 610 __s64 pid; 611 /** @total_usage: Total BO size used by process. */ 612 __u64 total_usage; 613 /** @internal_usage: Total internal BO size used by process. */ 614 __u64 internal_usage; 615 /** @heap_usage: Total device BO size used by process. */ 616 __u64 heap_usage; 617 }; 618 619 /* 620 * Supported params in struct amdxdna_drm_get_array 621 */ 622 #define DRM_AMDXDNA_HW_CONTEXT_ALL 0 623 #define DRM_AMDXDNA_HW_LAST_ASYNC_ERR 2 624 #define DRM_AMDXDNA_BO_USAGE 6 625 626 /** 627 * struct amdxdna_drm_get_array - Get information array. 628 */ 629 struct amdxdna_drm_get_array { 630 /** 631 * @param: 632 * 633 * Supported params: 634 * 635 * %DRM_AMDXDNA_HW_CONTEXT_ALL: 636 * Returns all created hardware contexts. 637 * 638 * %DRM_AMDXDNA_HW_LAST_ASYNC_ERR: 639 * Returns last async error. 640 * 641 * %DRM_AMDXDNA_BO_USAGE: 642 * Returns usage of heap/internal/external BOs. 643 */ 644 __u32 param; 645 /** 646 * @element_size: 647 * 648 * Specifies maximum element size and returns the actual element size. 649 */ 650 __u32 element_size; 651 /** 652 * @num_element: 653 * 654 * Specifies maximum number of elements and returns the actual number 655 * of elements. 656 */ 657 __u32 num_element; /* in/out */ 658 /** @pad: MBZ */ 659 __u32 pad; 660 /** 661 * @buffer: 662 * 663 * Specifies the match conditions and returns the matched information 664 * array. 665 */ 666 __u64 buffer; 667 }; 668 669 enum amdxdna_drm_set_param { 670 DRM_AMDXDNA_SET_POWER_MODE, 671 DRM_AMDXDNA_WRITE_AIE_MEM, 672 DRM_AMDXDNA_WRITE_AIE_REG, 673 DRM_AMDXDNA_SET_FORCE_PREEMPT, 674 DRM_AMDXDNA_SET_FRAME_BOUNDARY_PREEMPT, 675 }; 676 677 /** 678 * struct amdxdna_drm_set_state - Set the state of the AIE hardware. 679 * @param: Value in enum amdxdna_drm_set_param. 680 * @buffer_size: Size of the input param. 681 * @buffer: Pointer to the input param. 682 */ 683 struct amdxdna_drm_set_state { 684 __u32 param; /* in */ 685 __u32 buffer_size; /* in */ 686 __u64 buffer; /* in */ 687 }; 688 689 /** 690 * struct amdxdna_drm_set_power_mode - Set the power mode of the AIE hardware 691 * @power_mode: The sensor type from enum amdxdna_power_mode_type 692 * @pad: MBZ. 693 */ 694 struct amdxdna_drm_set_power_mode { 695 __u8 power_mode; 696 __u8 pad[7]; 697 }; 698 699 #define DRM_IOCTL_AMDXDNA_CREATE_HWCTX \ 700 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CREATE_HWCTX, \ 701 struct amdxdna_drm_create_hwctx) 702 703 #define DRM_IOCTL_AMDXDNA_DESTROY_HWCTX \ 704 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_DESTROY_HWCTX, \ 705 struct amdxdna_drm_destroy_hwctx) 706 707 #define DRM_IOCTL_AMDXDNA_CONFIG_HWCTX \ 708 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CONFIG_HWCTX, \ 709 struct amdxdna_drm_config_hwctx) 710 711 #define DRM_IOCTL_AMDXDNA_CREATE_BO \ 712 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CREATE_BO, \ 713 struct amdxdna_drm_create_bo) 714 715 #define DRM_IOCTL_AMDXDNA_GET_BO_INFO \ 716 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_GET_BO_INFO, \ 717 struct amdxdna_drm_get_bo_info) 718 719 #define DRM_IOCTL_AMDXDNA_SYNC_BO \ 720 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_SYNC_BO, \ 721 struct amdxdna_drm_sync_bo) 722 723 #define DRM_IOCTL_AMDXDNA_EXEC_CMD \ 724 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_EXEC_CMD, \ 725 struct amdxdna_drm_exec_cmd) 726 727 #define DRM_IOCTL_AMDXDNA_GET_INFO \ 728 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_GET_INFO, \ 729 struct amdxdna_drm_get_info) 730 731 #define DRM_IOCTL_AMDXDNA_SET_STATE \ 732 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_SET_STATE, \ 733 struct amdxdna_drm_set_state) 734 735 #define DRM_IOCTL_AMDXDNA_GET_ARRAY \ 736 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_GET_ARRAY, \ 737 struct amdxdna_drm_get_array) 738 739 #if defined(__cplusplus) 740 } /* extern c end */ 741 #endif 742 743 #endif /* _UAPI_AMDXDNA_ACCEL_H_ */ 744