1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #include "amdgpu_ctx.h" 38 39 #include <linux/atomic.h> 40 #include <linux/wait.h> 41 #include <linux/list.h> 42 #include <linux/kref.h> 43 #include <linux/rbtree.h> 44 #include <linux/hashtable.h> 45 #include <linux/dma-fence.h> 46 #include <linux/pci.h> 47 48 #include <drm/ttm/ttm_bo.h> 49 #include <drm/ttm/ttm_placement.h> 50 51 #include <drm/amdgpu_drm.h> 52 #include <drm/drm_gem.h> 53 #include <drm/drm_ioctl.h> 54 55 #include <kgd_kfd_interface.h> 56 #include "dm_pp_interface.h" 57 #include "kgd_pp_interface.h" 58 59 #include "amd_shared.h" 60 #include "amdgpu_utils.h" 61 #include "amdgpu_mode.h" 62 #include "amdgpu_ih.h" 63 #include "amdgpu_irq.h" 64 #include "amdgpu_ucode.h" 65 #include "amdgpu_ttm.h" 66 #include "amdgpu_psp.h" 67 #include "amdgpu_gds.h" 68 #include "amdgpu_sync.h" 69 #include "amdgpu_ring.h" 70 #include "amdgpu_vm.h" 71 #include "amdgpu_dpm.h" 72 #include "amdgpu_acp.h" 73 #include "amdgpu_uvd.h" 74 #include "amdgpu_vce.h" 75 #include "amdgpu_vcn.h" 76 #include "amdgpu_jpeg.h" 77 #include "amdgpu_vpe.h" 78 #include "amdgpu_umsch_mm.h" 79 #include "amdgpu_gmc.h" 80 #include "amdgpu_gfx.h" 81 #include "amdgpu_sdma.h" 82 #include "amdgpu_lsdma.h" 83 #include "amdgpu_nbio.h" 84 #include "amdgpu_reg_access.h" 85 #include "amdgpu_hdp.h" 86 #include "amdgpu_dm.h" 87 #include "amdgpu_virt.h" 88 #include "amdgpu_csa.h" 89 #include "amdgpu_mes_ctx.h" 90 #include "amdgpu_gart.h" 91 #include "amdgpu_debugfs.h" 92 #include "amdgpu_job.h" 93 #include "amdgpu_bo_list.h" 94 #include "amdgpu_gem.h" 95 #include "amdgpu_doorbell.h" 96 #include "amdgpu_amdkfd.h" 97 #include "amdgpu_discovery.h" 98 #include "amdgpu_mes.h" 99 #include "amdgpu_umc.h" 100 #include "amdgpu_mmhub.h" 101 #include "amdgpu_gfxhub.h" 102 #include "amdgpu_df.h" 103 #include "amdgpu_smuio.h" 104 #include "amdgpu_fdinfo.h" 105 #include "amdgpu_mca.h" 106 #include "amdgpu_aca.h" 107 #include "amdgpu_ras.h" 108 #include "amdgpu_cper.h" 109 #include "amdgpu_xcp.h" 110 #include "amdgpu_seq64.h" 111 #include "amdgpu_reg_state.h" 112 #include "amdgpu_userq.h" 113 #include "amdgpu_eviction_fence.h" 114 #include "amdgpu_ip.h" 115 #if defined(CONFIG_DRM_AMD_ISP) 116 #include "amdgpu_isp.h" 117 #endif 118 119 #define MAX_GPU_INSTANCE 64 120 121 #define GFX_SLICE_PERIOD_MS 250 122 123 struct amdgpu_gpu_instance { 124 struct amdgpu_device *adev; 125 int mgpu_fan_enabled; 126 }; 127 128 struct amdgpu_mgpu_info { 129 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 130 struct mutex mutex; 131 uint32_t num_gpu; 132 uint32_t num_dgpu; 133 uint32_t num_apu; 134 }; 135 136 enum amdgpu_ss { 137 AMDGPU_SS_DRV_LOAD, 138 AMDGPU_SS_DEV_D0, 139 AMDGPU_SS_DEV_D3, 140 AMDGPU_SS_DRV_UNLOAD 141 }; 142 143 struct amdgpu_hwip_reg_entry { 144 u32 hwip; 145 u32 inst; 146 u32 seg; 147 u32 reg_offset; 148 const char *reg_name; 149 }; 150 151 struct amdgpu_watchdog_timer { 152 bool timeout_fatal_disable; 153 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 154 }; 155 156 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 157 158 /* 159 * Modules parameters. 160 */ 161 extern int amdgpu_modeset; 162 extern unsigned int amdgpu_vram_limit; 163 extern int amdgpu_vis_vram_limit; 164 extern int amdgpu_gart_size; 165 extern int amdgpu_gtt_size; 166 extern int amdgpu_moverate; 167 extern int amdgpu_audio; 168 extern int amdgpu_disp_priority; 169 extern int amdgpu_hw_i2c; 170 extern int amdgpu_pcie_gen2; 171 extern int amdgpu_msi; 172 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 173 extern int amdgpu_dpm; 174 extern int amdgpu_fw_load_type; 175 extern int amdgpu_aspm; 176 extern int amdgpu_runtime_pm; 177 extern uint amdgpu_ip_block_mask; 178 extern int amdgpu_bapm; 179 extern int amdgpu_deep_color; 180 extern int amdgpu_vm_size; 181 extern int amdgpu_vm_block_size; 182 extern int amdgpu_vm_fragment_size; 183 extern int amdgpu_vm_fault_stop; 184 extern int amdgpu_vm_debug; 185 extern int amdgpu_vm_update_mode; 186 extern int amdgpu_exp_hw_support; 187 extern int amdgpu_dc; 188 extern int amdgpu_sched_jobs; 189 extern int amdgpu_sched_hw_submission; 190 extern uint amdgpu_pcie_gen_cap; 191 extern uint amdgpu_pcie_lane_cap; 192 extern u64 amdgpu_cg_mask; 193 extern uint amdgpu_pg_mask; 194 extern uint amdgpu_sdma_phase_quantum; 195 extern char *amdgpu_disable_cu; 196 extern char *amdgpu_virtual_display; 197 extern uint amdgpu_pp_feature_mask; 198 extern uint amdgpu_force_long_training; 199 extern int amdgpu_lbpw; 200 extern int amdgpu_compute_multipipe; 201 extern int amdgpu_gpu_recovery; 202 extern int amdgpu_emu_mode; 203 extern uint amdgpu_smu_memory_pool_size; 204 extern int amdgpu_smu_pptable_id; 205 extern uint amdgpu_dc_feature_mask; 206 extern uint amdgpu_freesync_vid_mode; 207 extern uint amdgpu_dc_debug_mask; 208 extern uint amdgpu_dc_visual_confirm; 209 extern int amdgpu_dm_abm_level; 210 extern int amdgpu_backlight; 211 extern int amdgpu_damage_clips; 212 extern struct amdgpu_mgpu_info mgpu_info; 213 extern int amdgpu_ras_enable; 214 extern uint amdgpu_ras_mask; 215 extern int amdgpu_bad_page_threshold; 216 extern bool amdgpu_ignore_bad_page_threshold; 217 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 218 extern int amdgpu_async_gfx_ring; 219 extern int amdgpu_mcbp; 220 extern int amdgpu_discovery; 221 extern int amdgpu_mes_log_enable; 222 extern int amdgpu_uni_mes; 223 extern int amdgpu_noretry; 224 extern int amdgpu_force_asic_type; 225 extern int amdgpu_smartshift_bias; 226 extern int amdgpu_use_xgmi_p2p; 227 extern int amdgpu_mtype_local; 228 extern int amdgpu_enforce_isolation; 229 #ifdef CONFIG_HSA_AMD 230 extern int sched_policy; 231 extern bool debug_evictions; 232 extern bool no_system_mem_limit; 233 extern int halt_if_hws_hang; 234 extern uint amdgpu_svm_default_granularity; 235 #else 236 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 237 static const bool __maybe_unused debug_evictions; /* = false */ 238 static const bool __maybe_unused no_system_mem_limit; 239 static const int __maybe_unused halt_if_hws_hang; 240 #endif 241 #ifdef CONFIG_HSA_AMD_P2P 242 extern bool pcie_p2p; 243 #endif 244 245 extern int amdgpu_tmz; 246 extern int amdgpu_reset_method; 247 248 #ifdef CONFIG_DRM_AMDGPU_SI 249 extern int amdgpu_si_support; 250 #endif 251 #ifdef CONFIG_DRM_AMDGPU_CIK 252 extern int amdgpu_cik_support; 253 #endif 254 extern int amdgpu_num_kcq; 255 256 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024) 257 #define AMDGPU_UMSCHFW_LOG_SIZE (32 * 1024) 258 extern int amdgpu_vcnfw_log; 259 extern int amdgpu_sg_display; 260 extern int amdgpu_umsch_mm; 261 extern int amdgpu_seamless; 262 extern int amdgpu_umsch_mm_fwlog; 263 264 extern int amdgpu_user_partt_mode; 265 extern int amdgpu_agp; 266 extern int amdgpu_rebar; 267 268 extern int amdgpu_wbrf; 269 extern int amdgpu_user_queue; 270 271 extern uint amdgpu_hdmi_hpd_debounce_delay_ms; 272 273 #define AMDGPU_VM_MAX_NUM_CTX 4096 274 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 275 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 276 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 277 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 278 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 279 #define AMDGPUFB_CONN_LIMIT 4 280 #define AMDGPU_BIOS_NUM_SCRATCH 16 281 282 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 283 284 /* hard reset data */ 285 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 286 287 /* reset flags */ 288 #define AMDGPU_RESET_GFX (1 << 0) 289 #define AMDGPU_RESET_COMPUTE (1 << 1) 290 #define AMDGPU_RESET_DMA (1 << 2) 291 #define AMDGPU_RESET_CP (1 << 3) 292 #define AMDGPU_RESET_GRBM (1 << 4) 293 #define AMDGPU_RESET_DMA1 (1 << 5) 294 #define AMDGPU_RESET_RLC (1 << 6) 295 #define AMDGPU_RESET_SEM (1 << 7) 296 #define AMDGPU_RESET_IH (1 << 8) 297 #define AMDGPU_RESET_VMC (1 << 9) 298 #define AMDGPU_RESET_MC (1 << 10) 299 #define AMDGPU_RESET_DISPLAY (1 << 11) 300 #define AMDGPU_RESET_UVD (1 << 12) 301 #define AMDGPU_RESET_VCE (1 << 13) 302 #define AMDGPU_RESET_VCE1 (1 << 14) 303 304 /* reset mask */ 305 #define AMDGPU_RESET_TYPE_FULL (1 << 0) /* full adapter reset, mode1/mode2/BACO/etc. */ 306 #define AMDGPU_RESET_TYPE_SOFT_RESET (1 << 1) /* IP level soft reset */ 307 #define AMDGPU_RESET_TYPE_PER_QUEUE (1 << 2) /* per queue */ 308 #define AMDGPU_RESET_TYPE_PER_PIPE (1 << 3) /* per pipe */ 309 310 /* max cursor sizes (in pixels) */ 311 #define CIK_CURSOR_WIDTH 128 312 #define CIK_CURSOR_HEIGHT 128 313 314 /* smart shift bias level limits */ 315 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 316 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 317 318 /* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */ 319 #define AMDGPU_SWCTF_EXTRA_DELAY 50 320 321 struct amdgpu_xcp_mgr; 322 struct amdgpu_device; 323 struct amdgpu_irq_src; 324 struct amdgpu_fpriv; 325 struct amdgpu_bo_va_mapping; 326 struct kfd_vm_fault_info; 327 struct amdgpu_hive_info; 328 struct amdgpu_reset_context; 329 struct amdgpu_reset_control; 330 struct amdgpu_coredump_info; 331 332 enum amdgpu_cp_irq { 333 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 334 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 335 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 336 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 337 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 338 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 339 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 340 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 341 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 342 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 343 344 AMDGPU_CP_IRQ_LAST 345 }; 346 347 enum amdgpu_thermal_irq { 348 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 349 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 350 351 AMDGPU_THERMAL_IRQ_LAST 352 }; 353 354 enum amdgpu_kiq_irq { 355 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 356 AMDGPU_CP_KIQ_IRQ_LAST 357 }; 358 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 359 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 360 #define MAX_KIQ_REG_TRY 1000 361 362 /* 363 * BIOS. 364 */ 365 bool amdgpu_get_bios(struct amdgpu_device *adev); 366 bool amdgpu_read_bios(struct amdgpu_device *adev); 367 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 368 u8 *bios, u32 length_bytes); 369 void amdgpu_bios_release(struct amdgpu_device *adev); 370 /* 371 * Clocks 372 */ 373 374 #define AMDGPU_MAX_PPLL 3 375 376 struct amdgpu_clock { 377 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 378 struct amdgpu_pll spll; 379 struct amdgpu_pll mpll; 380 /* 10 Khz units */ 381 uint32_t default_mclk; 382 uint32_t default_sclk; 383 uint32_t default_dispclk; 384 uint32_t dp_extclk; 385 uint32_t max_pixel_clock; 386 }; 387 388 /* sub-allocation manager, it has to be protected by another lock. 389 * By conception this is an helper for other part of the driver 390 * like the indirect buffer or semaphore, which both have their 391 * locking. 392 * 393 * Principe is simple, we keep a list of sub allocation in offset 394 * order (first entry has offset == 0, last entry has the highest 395 * offset). 396 * 397 * When allocating new object we first check if there is room at 398 * the end total_size - (last_object_offset + last_object_size) >= 399 * alloc_size. If so we allocate new object there. 400 * 401 * When there is not enough room at the end, we start waiting for 402 * each sub object until we reach object_offset+object_size >= 403 * alloc_size, this object then become the sub object we return. 404 * 405 * Alignment can't be bigger than page size. 406 * 407 * Hole are not considered for allocation to keep things simple. 408 * Assumption is that there won't be hole (all object on same 409 * alignment). 410 */ 411 412 struct amdgpu_sa_manager { 413 struct drm_suballoc_manager base; 414 struct amdgpu_bo *bo; 415 uint64_t gpu_addr; 416 void *cpu_ptr; 417 }; 418 419 /* 420 * IRQS. 421 */ 422 423 struct amdgpu_flip_work { 424 struct delayed_work flip_work; 425 struct work_struct unpin_work; 426 struct amdgpu_device *adev; 427 int crtc_id; 428 u32 target_vblank; 429 uint64_t base; 430 struct drm_pending_vblank_event *event; 431 struct amdgpu_bo *old_abo; 432 unsigned shared_count; 433 struct dma_fence **shared; 434 struct dma_fence_cb cb; 435 bool async; 436 }; 437 438 /* 439 * file private structure 440 */ 441 442 struct amdgpu_fpriv { 443 struct amdgpu_vm vm; 444 struct amdgpu_bo_va *prt_va; 445 struct amdgpu_bo_va *csa_va; 446 struct amdgpu_bo_va *seq64_va; 447 struct mutex bo_list_lock; 448 struct idr bo_list_handles; 449 struct amdgpu_ctx_mgr ctx_mgr; 450 struct amdgpu_userq_mgr userq_mgr; 451 452 /* Eviction fence infra */ 453 struct amdgpu_eviction_fence_mgr evf_mgr; 454 455 /** GPU partition selection */ 456 uint32_t xcp_id; 457 }; 458 459 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 460 461 /* 462 * Writeback 463 */ 464 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 465 466 /** 467 * amdgpu_wb - This struct is used for small GPU memory allocation. 468 * 469 * This struct is used to allocate a small amount of GPU memory that can be 470 * used to shadow certain states into the memory. This is especially useful for 471 * providing easy CPU access to some states without requiring register access 472 * (e.g., if some block is power gated, reading register may be problematic). 473 * 474 * Note: the term writeback was initially used because many of the amdgpu 475 * components had some level of writeback memory, and this struct initially 476 * described those components. 477 */ 478 struct amdgpu_wb { 479 480 /** 481 * @wb_obj: 482 * 483 * Buffer Object used for the writeback memory. 484 */ 485 struct amdgpu_bo *wb_obj; 486 487 /** 488 * @wb: 489 * 490 * Pointer to the first writeback slot. In terms of CPU address 491 * this value can be accessed directly by using the offset as an index. 492 * For the GPU address, it is necessary to use gpu_addr and the offset. 493 */ 494 uint32_t *wb; 495 496 /** 497 * @gpu_addr: 498 * 499 * Writeback base address in the GPU. 500 */ 501 uint64_t gpu_addr; 502 503 /** 504 * @num_wb: 505 * 506 * Number of writeback slots reserved for amdgpu. 507 */ 508 u32 num_wb; 509 510 /** 511 * @used: 512 * 513 * Track the writeback slot already used. 514 */ 515 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 516 517 /** 518 * @lock: 519 * 520 * Protects read and write of the used field array. 521 */ 522 spinlock_t lock; 523 }; 524 525 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 526 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 527 528 /* 529 * Benchmarking 530 */ 531 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 532 533 /* 534 * ASIC specific register table accessible by UMD 535 */ 536 struct amdgpu_allowed_register_entry { 537 uint32_t reg_offset; 538 bool grbm_indexed; 539 }; 540 541 /** 542 * enum amd_reset_method - Methods for resetting AMD GPU devices 543 * 544 * @AMD_RESET_METHOD_NONE: The device will not be reset. 545 * @AMD_RESET_LEGACY: Method reserved for SI, CIK and VI ASICs. 546 * @AMD_RESET_MODE0: Reset the entire ASIC. Not currently available for the 547 * any device. 548 * @AMD_RESET_MODE1: Resets all IP blocks on the ASIC (SDMA, GFX, VCN, etc.) 549 * individually. Suitable only for some discrete GPU, not 550 * available for all ASICs. 551 * @AMD_RESET_MODE2: Resets a lesser level of IPs compared to MODE1. Which IPs 552 * are reset depends on the ASIC. Notably doesn't reset IPs 553 * shared with the CPU on APUs or the memory controllers (so 554 * VRAM is not lost). Not available on all ASICs. 555 * @AMD_RESET_LINK: Triggers SW-UP link reset on other GPUs 556 * @AMD_RESET_BACO: BACO (Bus Alive, Chip Off) method powers off and on the card 557 * but without powering off the PCI bus. Suitable only for 558 * discrete GPUs. 559 * @AMD_RESET_PCI: Does a full bus reset using core Linux subsystem PCI reset 560 * and does a secondary bus reset or FLR, depending on what the 561 * underlying hardware supports. 562 * 563 * Methods available for AMD GPU driver for resetting the device. Not all 564 * methods are suitable for every device. User can override the method using 565 * module parameter `reset_method`. 566 */ 567 enum amd_reset_method { 568 AMD_RESET_METHOD_NONE = -1, 569 AMD_RESET_METHOD_LEGACY = 0, 570 AMD_RESET_METHOD_MODE0, 571 AMD_RESET_METHOD_MODE1, 572 AMD_RESET_METHOD_MODE2, 573 AMD_RESET_METHOD_LINK, 574 AMD_RESET_METHOD_BACO, 575 AMD_RESET_METHOD_PCI, 576 AMD_RESET_METHOD_ON_INIT, 577 }; 578 579 struct amdgpu_video_codec_info { 580 u32 codec_type; 581 u32 max_width; 582 u32 max_height; 583 u32 max_pixels_per_frame; 584 u32 max_level; 585 }; 586 587 #define codec_info_build(type, width, height, level) \ 588 .codec_type = type,\ 589 .max_width = width,\ 590 .max_height = height,\ 591 .max_pixels_per_frame = height * width,\ 592 .max_level = level, 593 594 struct amdgpu_video_codecs { 595 const u32 codec_count; 596 const struct amdgpu_video_codec_info *codec_array; 597 }; 598 599 /* 600 * ASIC specific functions. 601 */ 602 struct amdgpu_asic_funcs { 603 bool (*read_disabled_bios)(struct amdgpu_device *adev); 604 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 605 u8 *bios, u32 length_bytes); 606 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 607 u32 sh_num, u32 reg_offset, u32 *value); 608 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 609 int (*reset)(struct amdgpu_device *adev); 610 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 611 /* get the reference clock */ 612 u32 (*get_xclk)(struct amdgpu_device *adev); 613 /* MM block clocks */ 614 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 615 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 616 /* static power management */ 617 int (*get_pcie_lanes)(struct amdgpu_device *adev); 618 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 619 /* get config memsize register */ 620 u32 (*get_config_memsize)(struct amdgpu_device *adev); 621 /* flush hdp write queue */ 622 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 623 /* invalidate hdp read cache */ 624 void (*invalidate_hdp)(struct amdgpu_device *adev, 625 struct amdgpu_ring *ring); 626 /* check if the asic needs a full reset of if soft reset will work */ 627 bool (*need_full_reset)(struct amdgpu_device *adev); 628 /* initialize doorbell layout for specific asic*/ 629 void (*init_doorbell_index)(struct amdgpu_device *adev); 630 /* PCIe bandwidth usage */ 631 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 632 uint64_t *count1); 633 /* do we need to reset the asic at init time (e.g., kexec) */ 634 bool (*need_reset_on_init)(struct amdgpu_device *adev); 635 /* PCIe replay counter */ 636 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 637 /* device supports BACO */ 638 int (*supports_baco)(struct amdgpu_device *adev); 639 /* pre asic_init quirks */ 640 void (*pre_asic_init)(struct amdgpu_device *adev); 641 /* enter/exit umd stable pstate */ 642 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 643 /* query video codecs */ 644 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 645 const struct amdgpu_video_codecs **codecs); 646 /* encode "> 32bits" smn addressing */ 647 u64 (*encode_ext_smn_addressing)(int ext_id); 648 649 ssize_t (*get_reg_state)(struct amdgpu_device *adev, 650 enum amdgpu_reg_state reg_state, void *buf, 651 size_t max_size); 652 }; 653 654 /* 655 * IOCTL. 656 */ 657 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 658 struct drm_file *filp); 659 660 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 661 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 662 struct drm_file *filp); 663 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 664 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 665 struct drm_file *filp); 666 667 /* VRAM scratch page for HDP bug, default vram page */ 668 struct amdgpu_mem_scratch { 669 struct amdgpu_bo *robj; 670 uint32_t *ptr; 671 u64 gpu_addr; 672 }; 673 674 /* 675 * CGS 676 */ 677 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 678 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 679 680 /* 681 * Core structure, functions and helpers. 682 */ 683 struct amdgpu_mmio_remap { 684 u32 reg_offset; 685 resource_size_t bus_addr; 686 struct amdgpu_bo *bo; 687 }; 688 689 enum amdgpu_uid_type { 690 AMDGPU_UID_TYPE_XCD, 691 AMDGPU_UID_TYPE_AID, 692 AMDGPU_UID_TYPE_SOC, 693 AMDGPU_UID_TYPE_MID, 694 AMDGPU_UID_TYPE_MAX 695 }; 696 697 #define AMDGPU_UID_INST_MAX 8 /* max number of instances for each UID type */ 698 699 struct amdgpu_uid { 700 uint64_t uid[AMDGPU_UID_TYPE_MAX][AMDGPU_UID_INST_MAX]; 701 struct amdgpu_device *adev; 702 }; 703 704 #define MAX_UMA_OPTION_NAME 28 705 #define MAX_UMA_OPTION_ENTRIES 19 706 707 #define AMDGPU_UMA_FLAG_AUTO BIT(1) 708 #define AMDGPU_UMA_FLAG_CUSTOM BIT(0) 709 710 /** 711 * struct amdgpu_uma_carveout_option - single UMA carveout option 712 * @name: Name of the carveout option 713 * @memory_carved_mb: Amount of memory carved in MB 714 * @flags: ATCS flags supported by this option 715 */ 716 struct amdgpu_uma_carveout_option { 717 char name[MAX_UMA_OPTION_NAME]; 718 uint32_t memory_carved_mb; 719 uint8_t flags; 720 }; 721 722 /** 723 * struct amdgpu_uma_carveout_info - table of available UMA carveout options 724 * @num_entries: Number of available options 725 * @uma_option_index: The index of the option currently applied 726 * @update_lock: Lock to serialize changes to the option 727 * @entries: The array of carveout options 728 */ 729 struct amdgpu_uma_carveout_info { 730 uint8_t num_entries; 731 uint8_t uma_option_index; 732 struct mutex update_lock; 733 struct amdgpu_uma_carveout_option entries[MAX_UMA_OPTION_ENTRIES]; 734 }; 735 736 struct amd_powerplay { 737 void *pp_handle; 738 const struct amd_pm_funcs *pp_funcs; 739 }; 740 741 /* polaris10 kickers */ 742 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 743 ((rid == 0xE3) || \ 744 (rid == 0xE4) || \ 745 (rid == 0xE5) || \ 746 (rid == 0xE7) || \ 747 (rid == 0xEF))) || \ 748 ((did == 0x6FDF) && \ 749 ((rid == 0xE7) || \ 750 (rid == 0xEF) || \ 751 (rid == 0xFF)))) 752 753 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 754 ((rid == 0xE1) || \ 755 (rid == 0xF7))) 756 757 /* polaris11 kickers */ 758 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 759 ((rid == 0xE0) || \ 760 (rid == 0xE5))) || \ 761 ((did == 0x67FF) && \ 762 ((rid == 0xCF) || \ 763 (rid == 0xEF) || \ 764 (rid == 0xFF)))) 765 766 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 767 ((rid == 0xE2))) 768 769 /* polaris12 kickers */ 770 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 771 ((rid == 0xC0) || \ 772 (rid == 0xC1) || \ 773 (rid == 0xC3) || \ 774 (rid == 0xC7))) || \ 775 ((did == 0x6981) && \ 776 ((rid == 0x00) || \ 777 (rid == 0x01) || \ 778 (rid == 0x10)))) 779 780 enum amdgpu_mqd_update_flag { 781 AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE = 1, 782 AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE = 2, 783 AMDGPU_UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */ 784 }; 785 786 struct amdgpu_mqd_prop { 787 uint64_t mqd_gpu_addr; 788 uint64_t hqd_base_gpu_addr; 789 uint64_t rptr_gpu_addr; 790 uint64_t wptr_gpu_addr; 791 uint32_t queue_size; 792 bool use_doorbell; 793 uint32_t doorbell_index; 794 uint64_t eop_gpu_addr; 795 uint32_t hqd_pipe_priority; 796 uint32_t hqd_queue_priority; 797 uint32_t mqd_stride_size; 798 bool allow_tunneling; 799 bool hqd_active; 800 uint64_t shadow_addr; 801 uint64_t gds_bkup_addr; 802 uint64_t csa_addr; 803 uint64_t fence_address; 804 bool tmz_queue; 805 bool kernel_queue; 806 uint32_t *cu_mask; 807 uint32_t cu_mask_count; 808 uint32_t cu_flags; 809 bool is_user_cu_masked; 810 }; 811 812 struct amdgpu_mqd { 813 unsigned mqd_size; 814 int (*init_mqd)(struct amdgpu_device *adev, void *mqd, 815 struct amdgpu_mqd_prop *p); 816 }; 817 818 struct amdgpu_pcie_reset_ctx { 819 bool in_link_reset; 820 bool occurs_dpc; 821 bool audio_suspended; 822 struct pci_dev *swus; 823 struct pci_saved_state *swus_pcistate; 824 struct pci_saved_state *swds_pcistate; 825 }; 826 827 /* 828 * Custom Init levels could be defined for different situations where a full 829 * initialization of all hardware blocks are not expected. Sample cases are 830 * custom init sequences after resume after S0i3/S3, reset on initialization, 831 * partial reset of blocks etc. Presently, this defines only two levels. Levels 832 * are described in corresponding struct definitions - amdgpu_init_default, 833 * amdgpu_init_minimal_xgmi. 834 */ 835 enum amdgpu_init_lvl_id { 836 AMDGPU_INIT_LEVEL_DEFAULT, 837 AMDGPU_INIT_LEVEL_MINIMAL_XGMI, 838 AMDGPU_INIT_LEVEL_RESET_RECOVERY, 839 }; 840 841 struct amdgpu_init_level { 842 enum amdgpu_init_lvl_id level; 843 uint32_t hwini_ip_block_mask; 844 }; 845 846 #define AMDGPU_RESET_MAGIC_NUM 64 847 #define AMDGPU_MAX_DF_PERFMONS 4 848 struct amdgpu_reset_domain; 849 struct amdgpu_fru_info; 850 851 enum amdgpu_enforce_isolation_mode { 852 AMDGPU_ENFORCE_ISOLATION_DISABLE = 0, 853 AMDGPU_ENFORCE_ISOLATION_ENABLE = 1, 854 AMDGPU_ENFORCE_ISOLATION_ENABLE_LEGACY = 2, 855 AMDGPU_ENFORCE_ISOLATION_NO_CLEANER_SHADER = 3, 856 }; 857 858 struct amdgpu_device { 859 struct device *dev; 860 struct pci_dev *pdev; 861 struct drm_device ddev; 862 863 #ifdef CONFIG_DRM_AMD_ACP 864 struct amdgpu_acp acp; 865 #endif 866 struct amdgpu_hive_info *hive; 867 struct amdgpu_xcp_mgr *xcp_mgr; 868 /* ASIC */ 869 enum amd_asic_type asic_type; 870 uint32_t family; 871 uint32_t rev_id; 872 uint32_t external_rev_id; 873 unsigned long flags; 874 unsigned long apu_flags; 875 int usec_timeout; 876 const struct amdgpu_asic_funcs *asic_funcs; 877 bool shutdown; 878 bool need_swiotlb; 879 bool accel_working; 880 struct notifier_block acpi_nb; 881 struct notifier_block pm_nb; 882 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 883 struct debugfs_blob_wrapper debugfs_vbios_blob; 884 struct mutex srbm_mutex; 885 /* GRBM index mutex. Protects concurrent access to GRBM index */ 886 struct mutex grbm_idx_mutex; 887 struct dev_pm_domain vga_pm_domain; 888 bool have_disp_power_ref; 889 bool have_atomics_support; 890 891 /* BIOS */ 892 bool is_atom_fw; 893 uint8_t *bios; 894 uint32_t bios_size; 895 uint32_t bios_scratch_reg_offset; 896 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 897 898 /* Register/doorbell mmio */ 899 resource_size_t rmmio_base; 900 resource_size_t rmmio_size; 901 void __iomem *rmmio; 902 /* protects concurrent MM_INDEX/DATA based register access */ 903 spinlock_t mmio_idx_lock; 904 struct amdgpu_mmio_remap rmmio_remap; 905 /* Indirect register access blocks */ 906 struct amdgpu_reg_access reg; 907 struct amdgpu_doorbell doorbell; 908 909 /* clock/pll info */ 910 struct amdgpu_clock clock; 911 912 /* MC */ 913 struct amdgpu_gmc gmc; 914 struct amdgpu_gart gart; 915 dma_addr_t dummy_page_addr; 916 struct amdgpu_vm_manager vm_manager; 917 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 918 DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS); 919 920 /* memory management */ 921 struct amdgpu_mman mman; 922 struct amdgpu_mem_scratch mem_scratch; 923 struct amdgpu_wb wb; 924 atomic64_t num_bytes_moved; 925 atomic64_t num_evictions; 926 atomic64_t num_vram_cpu_page_faults; 927 atomic_t gpu_reset_counter; 928 atomic_t vram_lost_counter; 929 930 /* data for buffer migration throttling */ 931 struct { 932 spinlock_t lock; 933 s64 last_update_us; 934 s64 accum_us; /* accumulated microseconds */ 935 s64 accum_us_vis; /* for visible VRAM */ 936 u32 log2_max_MBps; 937 } mm_stats; 938 939 /* discovery*/ 940 struct amdgpu_discovery_info discovery; 941 942 /* display */ 943 bool enable_virtual_display; 944 struct amdgpu_vkms_output *amdgpu_vkms_output; 945 struct amdgpu_mode_info mode_info; 946 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 947 struct delayed_work hotplug_work; 948 struct amdgpu_irq_src crtc_irq; 949 struct amdgpu_irq_src vline0_irq; 950 struct amdgpu_irq_src vupdate_irq; 951 struct amdgpu_irq_src pageflip_irq; 952 struct amdgpu_irq_src hpd_irq; 953 struct amdgpu_irq_src dmub_trace_irq; 954 struct amdgpu_irq_src dmub_outbox_irq; 955 956 /* rings */ 957 u64 fence_context; 958 unsigned num_rings; 959 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 960 struct dma_fence __rcu *gang_submit; 961 bool ib_pool_ready; 962 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 963 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 964 965 /* interrupts */ 966 struct amdgpu_irq irq; 967 968 /* powerplay */ 969 struct amd_powerplay powerplay; 970 struct amdgpu_pm pm; 971 u64 cg_flags; 972 u32 pg_flags; 973 974 /* nbio */ 975 struct amdgpu_nbio nbio; 976 977 /* hdp */ 978 struct amdgpu_hdp hdp; 979 980 /* smuio */ 981 struct amdgpu_smuio smuio; 982 983 /* mmhub */ 984 struct amdgpu_mmhub mmhub; 985 986 /* gfxhub */ 987 struct amdgpu_gfxhub gfxhub; 988 989 /* gfx */ 990 struct amdgpu_gfx gfx; 991 992 /* sdma */ 993 struct amdgpu_sdma sdma; 994 995 /* lsdma */ 996 struct amdgpu_lsdma lsdma; 997 998 /* uvd */ 999 struct amdgpu_uvd uvd; 1000 1001 /* vce */ 1002 struct amdgpu_vce vce; 1003 1004 /* vcn */ 1005 struct amdgpu_vcn vcn; 1006 1007 /* jpeg */ 1008 struct amdgpu_jpeg jpeg; 1009 1010 /* vpe */ 1011 struct amdgpu_vpe vpe; 1012 1013 /* umsch */ 1014 struct amdgpu_umsch_mm umsch_mm; 1015 bool enable_umsch_mm; 1016 1017 /* firmwares */ 1018 struct amdgpu_firmware firmware; 1019 1020 /* PSP */ 1021 struct psp_context psp; 1022 1023 /* GDS */ 1024 struct amdgpu_gds gds; 1025 1026 /* for userq and VM fences */ 1027 struct amdgpu_seq64 seq64; 1028 1029 /* UMC */ 1030 struct amdgpu_umc umc; 1031 1032 /* display related functionality */ 1033 struct amdgpu_display_manager dm; 1034 1035 #if defined(CONFIG_DRM_AMD_ISP) 1036 /* isp */ 1037 struct amdgpu_isp isp; 1038 #endif 1039 1040 /* mes */ 1041 bool enable_mes; 1042 bool enable_mes_kiq; 1043 bool enable_uni_mes; 1044 struct amdgpu_mes mes; 1045 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM]; 1046 const struct amdgpu_userq_funcs *userq_funcs[AMDGPU_HW_IP_NUM]; 1047 1048 /* xarray used to retrieve the user queue fence driver reference 1049 * in the EOP interrupt handler to signal the particular user 1050 * queue fence. 1051 */ 1052 struct xarray userq_xa; 1053 /** 1054 * @userq_doorbell_xa: Global user queue map (doorbell index → queue) 1055 * Key: doorbell_index (unique global identifier for the queue) 1056 * Value: struct amdgpu_usermode_queue 1057 */ 1058 struct xarray userq_doorbell_xa; 1059 1060 /* df */ 1061 struct amdgpu_df df; 1062 1063 /* MCA */ 1064 struct amdgpu_mca mca; 1065 1066 /* ACA */ 1067 struct amdgpu_aca aca; 1068 1069 /* CPER */ 1070 struct amdgpu_cper cper; 1071 1072 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 1073 uint32_t harvest_ip_mask; 1074 int num_ip_blocks; 1075 struct mutex mn_lock; 1076 DECLARE_HASHTABLE(mn_hash, 7); 1077 1078 /* tracking pinned memory */ 1079 atomic64_t vram_pin_size; 1080 atomic64_t visible_pin_size; 1081 atomic64_t gart_pin_size; 1082 1083 /* soc15 register offset based on ip, instance and segment */ 1084 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 1085 struct amdgpu_ip_map_info ip_map; 1086 1087 /* delayed work_func for deferring clockgating during resume */ 1088 struct delayed_work delayed_init_work; 1089 1090 struct amdgpu_virt virt; 1091 1092 /* record hw reset is performed */ 1093 bool has_hw_reset; 1094 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1095 1096 /* s3/s4 mask */ 1097 bool in_suspend; 1098 bool in_s3; 1099 bool in_s4; 1100 bool in_s0ix; 1101 suspend_state_t last_suspend_state; 1102 1103 enum pp_mp1_state mp1_state; 1104 struct amdgpu_doorbell_index doorbell_index; 1105 1106 struct mutex notifier_lock; 1107 1108 int asic_reset_res; 1109 struct work_struct xgmi_reset_work; 1110 struct list_head reset_list; 1111 1112 long gfx_timeout; 1113 long sdma_timeout; 1114 long video_timeout; 1115 long compute_timeout; 1116 long psp_timeout; 1117 1118 uint64_t unique_id; 1119 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1120 1121 /* enable runtime pm on the device */ 1122 bool in_runpm; 1123 bool has_pr3; 1124 1125 bool ucode_sysfs_en; 1126 1127 struct amdgpu_fru_info *fru_info; 1128 atomic_t throttling_logging_enabled; 1129 struct ratelimit_state throttling_logging_rs; 1130 uint32_t ras_hw_enabled; 1131 uint32_t ras_enabled; 1132 bool ras_default_ecc_enabled; 1133 1134 bool no_hw_access; 1135 struct pci_saved_state *pci_state; 1136 pci_channel_state_t pci_channel_state; 1137 1138 struct amdgpu_pcie_reset_ctx pcie_reset_ctx; 1139 1140 /* Track auto wait count on s_barrier settings */ 1141 bool barrier_has_auto_waitcnt; 1142 1143 struct amdgpu_reset_control *reset_cntl; 1144 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]; 1145 1146 bool ram_is_direct_mapped; 1147 1148 struct list_head ras_list; 1149 1150 struct amdgpu_reset_domain *reset_domain; 1151 1152 #ifdef CONFIG_DEV_COREDUMP 1153 struct amdgpu_coredump_info *coredump; 1154 struct work_struct coredump_work; 1155 #endif 1156 1157 struct mutex benchmark_mutex; 1158 1159 bool scpm_enabled; 1160 uint32_t scpm_status; 1161 1162 struct work_struct reset_work; 1163 1164 bool dc_enabled; 1165 /* Mask of active clusters */ 1166 uint32_t aid_mask; 1167 1168 /* Debug */ 1169 bool debug_vm; 1170 bool debug_largebar; 1171 bool debug_disable_soft_recovery; 1172 bool debug_use_vram_fw_buf; 1173 bool debug_enable_ras_aca; 1174 bool debug_exp_resets; 1175 bool debug_disable_gpu_ring_reset; 1176 bool debug_vm_userptr; 1177 bool debug_disable_ce_logs; 1178 bool debug_enable_ce_cs; 1179 1180 /* Protection for the following isolation structure */ 1181 struct mutex enforce_isolation_mutex; 1182 enum amdgpu_enforce_isolation_mode enforce_isolation[MAX_XCP]; 1183 struct amdgpu_isolation { 1184 void *owner; 1185 struct dma_fence *spearhead; 1186 struct amdgpu_sync active; 1187 struct amdgpu_sync prev; 1188 } isolation[MAX_XCP]; 1189 1190 struct amdgpu_init_level *init_lvl; 1191 1192 /* This flag is used to determine how VRAM allocations are handled for APUs 1193 * in KFD: VRAM or GTT. 1194 */ 1195 bool apu_prefer_gtt; 1196 1197 bool userq_halt_for_enforce_isolation; 1198 struct work_struct userq_reset_work; 1199 struct amdgpu_uid *uid_info; 1200 1201 struct amdgpu_uma_carveout_info uma_info; 1202 1203 /* KFD 1204 * Must be last --ends in a flexible-array member. 1205 */ 1206 struct amdgpu_kfd_dev kfd; 1207 }; 1208 1209 /* 1210 * MES FW uses address(mqd_addr + sizeof(struct mqd) + 3*sizeof(uint32_t)) 1211 * as fence address and writes a 32 bit fence value to this address. 1212 * Driver needs to allocate at least 4 DWs extra memory in addition to 1213 * sizeof(struct mqd). Add 8 DWs and align to AMDGPU_GPU_PAGE_SIZE for safety. 1214 */ 1215 #define AMDGPU_MQD_SIZE_ALIGN(mqd_size) AMDGPU_GPU_PAGE_ALIGN(((mqd_size) + 32)) 1216 1217 static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, 1218 uint8_t ip, uint8_t inst) 1219 { 1220 /* This considers only major/minor/rev and ignores 1221 * subrevision/variant fields. 1222 */ 1223 return adev->ip_versions[ip][inst] & ~0xFFU; 1224 } 1225 1226 static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev, 1227 uint8_t ip, uint8_t inst) 1228 { 1229 /* This returns full version - major/minor/rev/variant/subrevision */ 1230 return adev->ip_versions[ip][inst]; 1231 } 1232 1233 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1234 { 1235 return container_of(ddev, struct amdgpu_device, ddev); 1236 } 1237 1238 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1239 { 1240 return &adev->ddev; 1241 } 1242 1243 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1244 { 1245 return container_of(bdev, struct amdgpu_device, mman.bdev); 1246 } 1247 1248 static inline bool amdgpu_is_multi_aid(struct amdgpu_device *adev) 1249 { 1250 return !!adev->aid_mask; 1251 } 1252 1253 int amdgpu_device_init(struct amdgpu_device *adev, 1254 uint32_t flags); 1255 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1256 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1257 1258 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1259 1260 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1261 void *buf, size_t size, bool write); 1262 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1263 void *buf, size_t size, bool write); 1264 1265 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1266 void *buf, size_t size, bool write); 1267 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev); 1268 bool amdgpu_device_asic_has_dc_support(struct pci_dev *pdev, 1269 enum amd_asic_type asic_type); 1270 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1271 1272 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev); 1273 1274 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1275 struct amdgpu_reset_context *reset_context); 1276 1277 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1278 struct amdgpu_reset_context *reset_context); 1279 1280 int amdgpu_device_reinit_after_reset(struct amdgpu_reset_context *reset_context); 1281 1282 int emu_soc_asic_init(struct amdgpu_device *adev); 1283 1284 /* 1285 * Registers read & write functions. 1286 */ 1287 #define AMDGPU_REGS_NO_KIQ (1<<1) 1288 #define AMDGPU_REGS_RLC (1<<2) 1289 1290 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1291 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1292 1293 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg), 0) 1294 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v), 0) 1295 1296 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1297 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1298 1299 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1300 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1301 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1302 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1303 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1304 #define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst) 1305 #define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst) 1306 #define RREG32_PCIE(reg) amdgpu_reg_pcie_rd32(adev, (reg)) 1307 #define WREG32_PCIE(reg, v) amdgpu_reg_pcie_wr32(adev, (reg), (v)) 1308 #define RREG32_PCIE_PORT(reg) amdgpu_reg_pciep_rd32(adev, (reg)) 1309 #define WREG32_PCIE_PORT(reg, v) amdgpu_reg_pciep_wr32(adev, (reg), (v)) 1310 #define RREG32_PCIE_EXT(reg) amdgpu_reg_pcie_ext_rd32(adev, (reg)) 1311 #define WREG32_PCIE_EXT(reg, v) amdgpu_reg_pcie_ext_wr32(adev, (reg), (v)) 1312 #define RREG64_PCIE(reg) amdgpu_reg_pcie_rd64(adev, (reg)) 1313 #define WREG64_PCIE(reg, v) amdgpu_reg_pcie_wr64(adev, (reg), (v)) 1314 #define RREG64_PCIE_EXT(reg) amdgpu_reg_pcie_ext_rd64(adev, (reg)) 1315 #define WREG64_PCIE_EXT(reg, v) amdgpu_reg_pcie_ext_wr64(adev, (reg), (v)) 1316 #define RREG32_SMC(reg) amdgpu_reg_smc_rd32(adev, (reg)) 1317 #define WREG32_SMC(reg, v) amdgpu_reg_smc_wr32(adev, (reg), (v)) 1318 #define RREG32_UVD_CTX(reg) amdgpu_reg_uvd_ctx_rd32(adev, (reg)) 1319 #define WREG32_UVD_CTX(reg, v) amdgpu_reg_uvd_ctx_wr32(adev, (reg), (v)) 1320 #define RREG32_DIDT(reg) amdgpu_reg_didt_rd32(adev, (reg)) 1321 #define WREG32_DIDT(reg, v) amdgpu_reg_didt_wr32(adev, (reg), (v)) 1322 #define RREG32_GC_CAC(reg) amdgpu_reg_gc_cac_rd32(adev, (reg)) 1323 #define WREG32_GC_CAC(reg, v) amdgpu_reg_gc_cac_wr32(adev, (reg), (v)) 1324 #define RREG32_SE_CAC(reg) amdgpu_reg_se_cac_rd32(adev, (reg)) 1325 #define WREG32_SE_CAC(reg, v) amdgpu_reg_se_cac_wr32(adev, (reg), (v)) 1326 #define RREG32_AUDIO_ENDPT(block, reg) \ 1327 amdgpu_reg_audio_endpt_rd32(adev, (block), (reg)) 1328 #define WREG32_AUDIO_ENDPT(block, reg, v) \ 1329 amdgpu_reg_audio_endpt_wr32(adev, (block), (reg), (v)) 1330 #define WREG32_P(reg, val, mask) \ 1331 do { \ 1332 uint32_t tmp_ = RREG32(reg); \ 1333 tmp_ &= (mask); \ 1334 tmp_ |= ((val) & ~(mask)); \ 1335 WREG32(reg, tmp_); \ 1336 } while (0) 1337 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1338 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1339 #define WREG32_PLL_P(reg, val, mask) \ 1340 do { \ 1341 uint32_t tmp_ = RREG32_PLL(reg); \ 1342 tmp_ &= (mask); \ 1343 tmp_ |= ((val) & ~(mask)); \ 1344 WREG32_PLL(reg, tmp_); \ 1345 } while (0) 1346 1347 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1348 do { \ 1349 u32 tmp = RREG32_SMC(_Reg); \ 1350 tmp &= (_Mask); \ 1351 tmp |= ((_Val) & ~(_Mask)); \ 1352 WREG32_SMC(_Reg, tmp); \ 1353 } while (0) 1354 1355 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1356 1357 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1358 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1359 1360 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1361 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1362 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1363 1364 #define REG_GET_FIELD(value, reg, field) \ 1365 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1366 1367 #define WREG32_FIELD(reg, field, val) \ 1368 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1369 1370 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1371 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1372 1373 #define AMDGPU_GET_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> (l)) 1374 /* 1375 * BIOS helpers. 1376 */ 1377 #define RBIOS8(i) (adev->bios[i]) 1378 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1379 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1380 1381 /* 1382 * ASICs macro. 1383 */ 1384 #define amdgpu_asic_set_vga_state(adev, state) \ 1385 ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0) 1386 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1387 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1388 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1389 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1390 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1391 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1392 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1393 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1394 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1395 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1396 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1397 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1398 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1399 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1400 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1401 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1402 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1403 #define amdgpu_asic_supports_baco(adev) \ 1404 ((adev)->asic_funcs->supports_baco ? (adev)->asic_funcs->supports_baco((adev)) : 0) 1405 #define amdgpu_asic_pre_asic_init(adev) \ 1406 { \ 1407 if ((adev)->asic_funcs && (adev)->asic_funcs->pre_asic_init) \ 1408 (adev)->asic_funcs->pre_asic_init((adev)); \ 1409 } 1410 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1411 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1412 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1413 1414 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)) 1415 1416 #define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i)) 1417 #define for_each_inst(i, inst_mask) \ 1418 for (i = ffs(inst_mask); i-- != 0; \ 1419 i = ffs(inst_mask & BIT_MASK_UPPER(i + 1))) 1420 1421 /* Common functions */ 1422 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1423 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1424 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1425 struct amdgpu_job *job, 1426 struct amdgpu_reset_context *reset_context); 1427 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1428 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1429 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1430 bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev); 1431 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1432 1433 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1434 u64 num_vis_bytes); 1435 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1436 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1437 const u32 *registers, 1438 const u32 array_size); 1439 1440 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1441 int amdgpu_device_link_reset(struct amdgpu_device *adev); 1442 bool amdgpu_device_supports_atpx(struct amdgpu_device *adev); 1443 bool amdgpu_device_supports_px(struct amdgpu_device *adev); 1444 bool amdgpu_device_supports_boco(struct amdgpu_device *adev); 1445 bool amdgpu_device_supports_smart_shift(struct amdgpu_device *adev); 1446 int amdgpu_device_supports_baco(struct amdgpu_device *adev); 1447 void amdgpu_device_detect_runtime_pm_mode(struct amdgpu_device *adev); 1448 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1449 struct amdgpu_device *peer_adev); 1450 int amdgpu_device_baco_enter(struct amdgpu_device *adev); 1451 int amdgpu_device_baco_exit(struct amdgpu_device *adev); 1452 1453 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1454 struct amdgpu_ring *ring); 1455 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1456 struct amdgpu_ring *ring); 1457 1458 void amdgpu_device_halt(struct amdgpu_device *adev); 1459 struct dma_fence *amdgpu_device_get_gang(struct amdgpu_device *adev); 1460 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, 1461 struct dma_fence *gang); 1462 struct dma_fence *amdgpu_device_enforce_isolation(struct amdgpu_device *adev, 1463 struct amdgpu_ring *ring, 1464 struct amdgpu_job *job); 1465 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev); 1466 ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu_ring *ring); 1467 ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset); 1468 void amdgpu_sdma_set_vm_pte_scheds(struct amdgpu_device *adev, 1469 const struct amdgpu_vm_pte_funcs *vm_pte_funcs); 1470 1471 /* atpx handler */ 1472 #if defined(CONFIG_VGA_SWITCHEROO) 1473 void amdgpu_register_atpx_handler(void); 1474 void amdgpu_unregister_atpx_handler(void); 1475 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1476 bool amdgpu_is_atpx_hybrid(void); 1477 bool amdgpu_has_atpx(void); 1478 #else 1479 static inline void amdgpu_register_atpx_handler(void) {} 1480 static inline void amdgpu_unregister_atpx_handler(void) {} 1481 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1482 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1483 static inline bool amdgpu_has_atpx(void) { return false; } 1484 #endif 1485 1486 /* 1487 * KMS 1488 */ 1489 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1490 extern const int amdgpu_max_kms_ioctl; 1491 1492 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1493 void amdgpu_driver_unload_kms(struct drm_device *dev); 1494 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1495 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1496 struct drm_file *file_priv); 1497 void amdgpu_driver_release_kms(struct drm_device *dev); 1498 1499 int amdgpu_device_prepare(struct drm_device *dev); 1500 void amdgpu_device_complete(struct drm_device *dev); 1501 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1502 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1503 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1504 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1505 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1506 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1507 struct drm_file *filp); 1508 1509 /* 1510 * functions used by amdgpu_encoder.c 1511 */ 1512 struct amdgpu_afmt_acr { 1513 u32 clock; 1514 1515 int n_32khz; 1516 int cts_32khz; 1517 1518 int n_44_1khz; 1519 int cts_44_1khz; 1520 1521 int n_48khz; 1522 int cts_48khz; 1523 1524 }; 1525 1526 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1527 1528 /* amdgpu_acpi.c */ 1529 1530 struct amdgpu_numa_info { 1531 uint64_t size; 1532 int pxm; 1533 int nid; 1534 }; 1535 1536 /* ATCS Device/Driver State */ 1537 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 1538 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 1539 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 1540 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 1541 1542 #if defined(CONFIG_ACPI) 1543 int amdgpu_acpi_init(struct amdgpu_device *adev); 1544 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1545 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1546 bool amdgpu_acpi_is_power_shift_control_supported(void); 1547 bool amdgpu_acpi_is_set_uma_allocation_size_supported(void); 1548 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1549 u8 perf_req, bool advertise); 1550 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1551 u8 dev_state, bool drv_state); 1552 int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev, 1553 enum amdgpu_ss ss_state); 1554 int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 index, u8 type); 1555 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1556 int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset, 1557 u64 *tmr_size); 1558 int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id, 1559 struct amdgpu_numa_info *numa_info); 1560 1561 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 1562 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev); 1563 void amdgpu_acpi_detect(void); 1564 void amdgpu_acpi_release(void); 1565 #else 1566 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1567 static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, 1568 u64 *tmr_offset, u64 *tmr_size) 1569 { 1570 return -EINVAL; 1571 } 1572 static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, 1573 int xcc_id, 1574 struct amdgpu_numa_info *numa_info) 1575 { 1576 return -EINVAL; 1577 } 1578 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1579 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; } 1580 static inline void amdgpu_acpi_detect(void) { } 1581 static inline void amdgpu_acpi_release(void) { } 1582 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 1583 static inline bool amdgpu_acpi_is_set_uma_allocation_size_supported(void) { return false; } 1584 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1585 u8 dev_state, bool drv_state) { return 0; } 1586 static inline int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev, 1587 enum amdgpu_ss ss_state) 1588 { 1589 return 0; 1590 } 1591 static inline int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 index, u8 type) 1592 { 1593 return -EINVAL; 1594 } 1595 static inline void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps) { } 1596 #endif 1597 1598 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 1599 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 1600 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1601 #else 1602 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 1603 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 1604 #endif 1605 1606 #if defined(CONFIG_DRM_AMD_ISP) 1607 int amdgpu_acpi_get_isp4_dev(struct acpi_device **dev); 1608 #endif 1609 1610 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1611 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1612 1613 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1614 pci_channel_state_t state); 1615 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1616 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1617 void amdgpu_pci_resume(struct pci_dev *pdev); 1618 1619 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1620 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1621 1622 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1623 1624 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1625 enum amd_clockgating_state state); 1626 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1627 enum amd_powergating_state state); 1628 1629 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) 1630 { 1631 return amdgpu_gpu_recovery != 0 && 1632 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT && 1633 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT && 1634 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT && 1635 adev->video_timeout != MAX_SCHEDULE_TIMEOUT; 1636 } 1637 1638 #include "amdgpu_object.h" 1639 1640 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1641 { 1642 return adev->gmc.tmz_enabled; 1643 } 1644 1645 int amdgpu_in_reset(struct amdgpu_device *adev); 1646 1647 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 1648 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 1649 extern const struct attribute_group amdgpu_flash_attr_group; 1650 1651 void amdgpu_set_init_level(struct amdgpu_device *adev, 1652 enum amdgpu_init_lvl_id lvl); 1653 1654 static inline int amdgpu_device_bus_status_check(struct amdgpu_device *adev) 1655 { 1656 u32 status; 1657 int r; 1658 1659 r = pci_read_config_dword(adev->pdev, PCI_COMMAND, &status); 1660 if (r || PCI_POSSIBLE_ERROR(status)) { 1661 dev_err(adev->dev, "device lost from bus!"); 1662 return -ENODEV; 1663 } 1664 1665 return 0; 1666 } 1667 1668 void amdgpu_device_set_uid(struct amdgpu_uid *uid_info, 1669 enum amdgpu_uid_type type, uint8_t inst, 1670 uint64_t uid); 1671 uint64_t amdgpu_device_get_uid(struct amdgpu_uid *uid_info, 1672 enum amdgpu_uid_type type, uint8_t inst); 1673 #endif 1674