1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #ifndef DC_TYPES_H_ 26 #define DC_TYPES_H_ 27 28 /* AND EdidUtility only needs a portion 29 * of this file, including the rest only 30 * causes additional issues. 31 */ 32 #include "os_types.h" 33 #include "fixed31_32.h" 34 #include "irq_types.h" 35 #include "dc_ddc_types.h" 36 #include "dc_dp_types.h" 37 #include "dc_hdmi_types.h" 38 #include "dc_hw_types.h" 39 #include "dal_types.h" 40 #include "grph_object_defs.h" 41 #include "grph_object_ctrl_defs.h" 42 43 #include "dm_cp_psp.h" 44 45 /* forward declarations */ 46 struct dc_plane_state; 47 struct dc_stream_state; 48 struct dc_link; 49 struct dc_sink; 50 struct dal; 51 struct dc_dmub_srv; 52 53 /******************************** 54 * Environment definitions 55 ********************************/ 56 enum dce_environment { 57 DCE_ENV_PRODUCTION_DRV = 0, 58 /* Emulation on FPGA, in "Maximus" System. 59 * This environment enforces that *only* DC registers accessed. 60 * (access to non-DC registers will hang FPGA) */ 61 DCE_ENV_FPGA_MAXIMUS, 62 /* Emulation on real HW or on FPGA. Used by Diagnostics, enforces 63 * requirements of Diagnostics team. */ 64 DCE_ENV_DIAG, 65 /* 66 * Guest VM system, DC HW may exist but is not virtualized and 67 * should not be used. SW support for VDI only. 68 */ 69 DCE_ENV_VIRTUAL_HW 70 }; 71 72 struct dc_perf_trace { 73 unsigned long read_count; 74 unsigned long write_count; 75 unsigned long last_entry_read; 76 unsigned long last_entry_write; 77 }; 78 79 #define NUM_PIXEL_FORMATS 10 80 81 enum tiling_mode { 82 TILING_MODE_INVALID, 83 TILING_MODE_LINEAR, 84 TILING_MODE_TILED, 85 TILING_MODE_COUNT 86 }; 87 88 enum view_3d_format { 89 VIEW_3D_FORMAT_NONE = 0, 90 VIEW_3D_FORMAT_FRAME_SEQUENTIAL, 91 VIEW_3D_FORMAT_SIDE_BY_SIDE, 92 VIEW_3D_FORMAT_TOP_AND_BOTTOM, 93 VIEW_3D_FORMAT_COUNT, 94 VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL 95 }; 96 97 enum plane_stereo_format { 98 PLANE_STEREO_FORMAT_NONE = 0, 99 PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1, 100 PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2, 101 PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3, 102 PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5, 103 PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6, 104 PLANE_STEREO_FORMAT_CHECKER_BOARD = 7 105 }; 106 107 /* TODO: Find way to calculate number of bits 108 * Please increase if pixel_format enum increases 109 * num from PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32 110 */ 111 112 enum dc_edid_connector_type { 113 DC_EDID_CONNECTOR_UNKNOWN = 0, 114 DC_EDID_CONNECTOR_ANALOG = 1, 115 DC_EDID_CONNECTOR_DIGITAL = 10, 116 DC_EDID_CONNECTOR_DVI = 11, 117 DC_EDID_CONNECTOR_HDMIA = 12, 118 DC_EDID_CONNECTOR_MDDI = 14, 119 DC_EDID_CONNECTOR_DISPLAYPORT = 15 120 }; 121 122 enum dc_edid_status { 123 EDID_OK, 124 EDID_BAD_INPUT, 125 EDID_NO_RESPONSE, 126 EDID_BAD_CHECKSUM, 127 EDID_THE_SAME, 128 EDID_FALL_BACK, 129 EDID_PARTIAL_VALID, 130 }; 131 132 enum act_return_status { 133 ACT_SUCCESS, 134 ACT_LINK_LOST, 135 ACT_FAILED 136 }; 137 138 /* audio capability from EDID*/ 139 struct dc_cea_audio_mode { 140 uint8_t format_code; /* ucData[0] [6:3]*/ 141 uint8_t channel_count; /* ucData[0] [2:0]*/ 142 uint8_t sample_rate; /* ucData[1]*/ 143 union { 144 uint8_t sample_size; /* for LPCM*/ 145 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/ 146 uint8_t max_bit_rate; 147 uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/ 148 }; 149 }; 150 151 struct dc_edid { 152 uint32_t length; 153 uint8_t raw_edid[DC_MAX_EDID_BUFFER_SIZE]; 154 }; 155 156 /* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION 157 * is used. In this case we assume speaker location are: front left, front 158 * right and front center. */ 159 #define DEFAULT_SPEAKER_LOCATION 5 160 161 #define DC_MAX_AUDIO_DESC_COUNT 16 162 163 #define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20 164 165 struct dc_panel_patch { 166 unsigned int dppowerup_delay; 167 unsigned int extra_t12_ms; 168 unsigned int extra_delay_backlight_off; 169 unsigned int extra_t7_ms; 170 unsigned int skip_scdc_overwrite; 171 unsigned int delay_ignore_msa; 172 unsigned int disable_fec; 173 unsigned int extra_t3_ms; 174 unsigned int max_dsc_target_bpp_limit; 175 unsigned int embedded_tiled_slave; 176 unsigned int disable_fams; 177 unsigned int skip_avmute; 178 unsigned int skip_audio_sab_check; 179 unsigned int mst_start_top_delay; 180 unsigned int remove_sink_ext_caps; 181 unsigned int disable_colorimetry; 182 uint8_t blankstream_before_otg_off; 183 bool oled_optimize_display_on; 184 unsigned int force_mst_blocked_discovery; 185 unsigned int wait_after_dpcd_poweroff_ms; 186 }; 187 188 struct dc_edid_caps { 189 /* sink identification */ 190 uint16_t manufacturer_id; 191 uint16_t product_id; 192 uint32_t serial_number; 193 uint8_t manufacture_week; 194 uint8_t manufacture_year; 195 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS]; 196 197 /* audio caps */ 198 uint8_t speaker_flags; 199 uint32_t audio_mode_count; 200 struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT]; 201 uint32_t audio_latency; 202 uint32_t video_latency; 203 204 uint8_t qs_bit; 205 uint8_t qy_bit; 206 207 uint32_t max_tmds_clk_mhz; 208 209 /*HDMI 2.0 caps*/ 210 bool lte_340mcsc_scramble; 211 212 bool edid_hdmi; 213 bool hdr_supported; 214 bool rr_capable; 215 216 struct dc_panel_patch panel_patch; 217 }; 218 219 struct dc_mode_flags { 220 /* note: part of refresh rate flag*/ 221 uint32_t INTERLACE :1; 222 /* native display timing*/ 223 uint32_t NATIVE :1; 224 /* preferred is the recommended mode, one per display */ 225 uint32_t PREFERRED :1; 226 /* true if this mode should use reduced blanking timings 227 *_not_ related to the Reduced Blanking adjustment*/ 228 uint32_t REDUCED_BLANKING :1; 229 /* note: part of refreshrate flag*/ 230 uint32_t VIDEO_OPTIMIZED_RATE :1; 231 /* should be reported to upper layers as mode_flags*/ 232 uint32_t PACKED_PIXEL_FORMAT :1; 233 /*< preferred view*/ 234 uint32_t PREFERRED_VIEW :1; 235 /* this timing should be used only in tiled mode*/ 236 uint32_t TILED_MODE :1; 237 uint32_t DSE_MODE :1; 238 /* Refresh rate divider when Miracast sink is using a 239 different rate than the output display device 240 Must be zero for wired displays and non-zero for 241 Miracast displays*/ 242 uint32_t MIRACAST_REFRESH_DIVIDER; 243 }; 244 245 246 enum dc_timing_source { 247 TIMING_SOURCE_UNDEFINED, 248 249 /* explicitly specifed by user, most important*/ 250 TIMING_SOURCE_USER_FORCED, 251 TIMING_SOURCE_USER_OVERRIDE, 252 TIMING_SOURCE_CUSTOM, 253 TIMING_SOURCE_EXPLICIT, 254 255 /* explicitly specified by the display device, more important*/ 256 TIMING_SOURCE_EDID_CEA_SVD_3D, 257 TIMING_SOURCE_EDID_CEA_SVD_PREFERRED, 258 TIMING_SOURCE_EDID_CEA_SVD_420, 259 TIMING_SOURCE_EDID_DETAILED, 260 TIMING_SOURCE_EDID_ESTABLISHED, 261 TIMING_SOURCE_EDID_STANDARD, 262 TIMING_SOURCE_EDID_CEA_SVD, 263 TIMING_SOURCE_EDID_CVT_3BYTE, 264 TIMING_SOURCE_EDID_4BYTE, 265 TIMING_SOURCE_EDID_CEA_DISPLAYID_VTDB, 266 TIMING_SOURCE_EDID_CEA_RID, 267 TIMING_SOURCE_EDID_DISPLAYID_TYPE5, 268 TIMING_SOURCE_VBIOS, 269 TIMING_SOURCE_CV, 270 TIMING_SOURCE_TV, 271 TIMING_SOURCE_HDMI_VIC, 272 273 /* implicitly specified by display device, still safe but less important*/ 274 TIMING_SOURCE_DEFAULT, 275 276 /* only used for custom base modes */ 277 TIMING_SOURCE_CUSTOM_BASE, 278 279 /* these timing might not work, least important*/ 280 TIMING_SOURCE_RANGELIMIT, 281 TIMING_SOURCE_OS_FORCED, 282 TIMING_SOURCE_IMPLICIT, 283 284 /* only used by default mode list*/ 285 TIMING_SOURCE_BASICMODE, 286 287 TIMING_SOURCE_COUNT 288 }; 289 290 291 struct stereo_3d_features { 292 bool supported ; 293 bool allTimings ; 294 bool cloneMode ; 295 bool scaling ; 296 bool singleFrameSWPacked; 297 }; 298 299 enum dc_timing_support_method { 300 TIMING_SUPPORT_METHOD_UNDEFINED, 301 TIMING_SUPPORT_METHOD_EXPLICIT, 302 TIMING_SUPPORT_METHOD_IMPLICIT, 303 TIMING_SUPPORT_METHOD_NATIVE 304 }; 305 306 struct dc_mode_info { 307 uint32_t pixel_width; 308 uint32_t pixel_height; 309 uint32_t field_rate; 310 /* Vertical refresh rate for progressive modes. 311 * Field rate for interlaced modes.*/ 312 313 enum dc_timing_standard timing_standard; 314 enum dc_timing_source timing_source; 315 struct dc_mode_flags flags; 316 }; 317 318 enum dc_power_state { 319 DC_POWER_STATE_ON = 1, 320 DC_POWER_STATE_STANDBY, 321 DC_POWER_STATE_SUSPEND, 322 DC_POWER_STATE_OFF 323 }; 324 325 /* DC PowerStates */ 326 enum dc_video_power_state { 327 DC_VIDEO_POWER_UNSPECIFIED = 0, 328 DC_VIDEO_POWER_ON = 1, 329 DC_VIDEO_POWER_STANDBY, 330 DC_VIDEO_POWER_SUSPEND, 331 DC_VIDEO_POWER_OFF, 332 DC_VIDEO_POWER_HIBERNATE, 333 DC_VIDEO_POWER_SHUTDOWN, 334 DC_VIDEO_POWER_ULPS, /* BACO or Ultra-Light-Power-State */ 335 DC_VIDEO_POWER_AFTER_RESET, 336 DC_VIDEO_POWER_MAXIMUM 337 }; 338 339 enum dc_acpi_cm_power_state { 340 DC_ACPI_CM_POWER_STATE_D0 = 1, 341 DC_ACPI_CM_POWER_STATE_D1 = 2, 342 DC_ACPI_CM_POWER_STATE_D2 = 4, 343 DC_ACPI_CM_POWER_STATE_D3 = 8 344 }; 345 346 enum dc_connection_type { 347 dc_connection_none, 348 dc_connection_single, 349 dc_connection_mst_branch, 350 dc_connection_sst_branch 351 }; 352 353 struct dc_csc_adjustments { 354 struct fixed31_32 contrast; 355 struct fixed31_32 saturation; 356 struct fixed31_32 brightness; 357 struct fixed31_32 hue; 358 }; 359 360 /* Scaling format */ 361 enum scaling_transformation { 362 SCALING_TRANSFORMATION_UNINITIALIZED, 363 SCALING_TRANSFORMATION_IDENTITY = 0x0001, 364 SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002, 365 SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004, 366 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008, 367 SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010, 368 SCALING_TRANSFORMATION_INVALID = 0x80000000, 369 370 /* Flag the first and last */ 371 SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY, 372 SCALING_TRANSFORMATION_END = 373 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE 374 }; 375 376 enum display_content_type { 377 DISPLAY_CONTENT_TYPE_NO_DATA = 0, 378 DISPLAY_CONTENT_TYPE_GRAPHICS = 1, 379 DISPLAY_CONTENT_TYPE_PHOTO = 2, 380 DISPLAY_CONTENT_TYPE_CINEMA = 4, 381 DISPLAY_CONTENT_TYPE_GAME = 8 382 }; 383 384 enum cm_gamut_adjust_type { 385 CM_GAMUT_ADJUST_TYPE_BYPASS = 0, 386 CM_GAMUT_ADJUST_TYPE_HW, /* without adjustments */ 387 CM_GAMUT_ADJUST_TYPE_SW /* use adjustments */ 388 }; 389 390 struct cm_grph_csc_adjustment { 391 struct fixed31_32 temperature_matrix[12]; 392 enum cm_gamut_adjust_type gamut_adjust_type; 393 enum cm_gamut_coef_format gamut_coef_format; 394 }; 395 396 /* writeback */ 397 struct dwb_stereo_params { 398 bool stereo_enabled; /* false: normal mode, true: 3D stereo */ 399 enum dwb_stereo_type stereo_type; /* indicates stereo format */ 400 bool stereo_polarity; /* indicates left eye or right eye comes first in stereo mode */ 401 enum dwb_stereo_eye_select stereo_eye_select; /* indicate which eye should be captured */ 402 }; 403 404 struct dc_dwb_cnv_params { 405 unsigned int src_width; /* input active width */ 406 unsigned int src_height; /* input active height (half-active height in interlaced mode) */ 407 unsigned int crop_width; /* cropped window width at cnv output */ 408 bool crop_en; /* window cropping enable in cnv */ 409 unsigned int crop_height; /* cropped window height at cnv output */ 410 unsigned int crop_x; /* cropped window start x value at cnv output */ 411 unsigned int crop_y; /* cropped window start y value at cnv output */ 412 enum dwb_cnv_out_bpc cnv_out_bpc; /* cnv output pixel depth - 8bpc or 10bpc */ 413 enum dwb_out_format fc_out_format; /* dwb output pixel format - 2101010 or 16161616 and ARGB or RGBA */ 414 enum dwb_out_denorm out_denorm_mode;/* dwb output denormalization mode */ 415 unsigned int out_max_pix_val;/* pixel values greater than out_max_pix_val are clamped to out_max_pix_val */ 416 unsigned int out_min_pix_val;/* pixel values less than out_min_pix_val are clamped to out_min_pix_val */ 417 }; 418 419 struct dc_dwb_params { 420 unsigned int dwbscl_black_color; /* must be in FP1.5.10 */ 421 unsigned int hdr_mult; /* must be in FP1.6.12 */ 422 struct cm_grph_csc_adjustment csc_params; 423 struct dwb_stereo_params stereo_params; 424 struct dc_dwb_cnv_params cnv_params; /* CNV source size and cropping window parameters */ 425 unsigned int dest_width; /* Destination width */ 426 unsigned int dest_height; /* Destination height */ 427 enum dwb_scaler_mode out_format; /* default = YUV420 - TODO: limit this to 0 and 1 on dcn3 */ 428 enum dwb_output_depth output_depth; /* output pixel depth - 8bpc or 10bpc */ 429 enum dwb_capture_rate capture_rate; /* controls the frame capture rate */ 430 struct scaling_taps scaler_taps; /* Scaling taps */ 431 enum dwb_subsample_position subsample_position; 432 const struct dc_transfer_func *out_transfer_func; 433 }; 434 435 /* audio*/ 436 437 union audio_sample_rates { 438 struct sample_rates { 439 uint8_t RATE_32:1; 440 uint8_t RATE_44_1:1; 441 uint8_t RATE_48:1; 442 uint8_t RATE_88_2:1; 443 uint8_t RATE_96:1; 444 uint8_t RATE_176_4:1; 445 uint8_t RATE_192:1; 446 } rate; 447 448 uint8_t all; 449 }; 450 451 struct audio_speaker_flags { 452 uint32_t FL_FR:1; 453 uint32_t LFE:1; 454 uint32_t FC:1; 455 uint32_t RL_RR:1; 456 uint32_t RC:1; 457 uint32_t FLC_FRC:1; 458 uint32_t RLC_RRC:1; 459 uint32_t SUPPORT_AI:1; 460 }; 461 462 struct audio_speaker_info { 463 uint32_t ALLSPEAKERS:7; 464 uint32_t SUPPORT_AI:1; 465 }; 466 467 468 struct audio_info_flags { 469 470 union { 471 472 struct audio_speaker_flags speaker_flags; 473 struct audio_speaker_info info; 474 475 uint8_t all; 476 }; 477 }; 478 479 enum audio_format_code { 480 AUDIO_FORMAT_CODE_FIRST = 1, 481 AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST, 482 483 AUDIO_FORMAT_CODE_AC3, 484 /*Layers 1 & 2 */ 485 AUDIO_FORMAT_CODE_MPEG1, 486 /*MPEG1 Layer 3 */ 487 AUDIO_FORMAT_CODE_MP3, 488 /*multichannel */ 489 AUDIO_FORMAT_CODE_MPEG2, 490 AUDIO_FORMAT_CODE_AAC, 491 AUDIO_FORMAT_CODE_DTS, 492 AUDIO_FORMAT_CODE_ATRAC, 493 AUDIO_FORMAT_CODE_1BITAUDIO, 494 AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS, 495 AUDIO_FORMAT_CODE_DTS_HD, 496 AUDIO_FORMAT_CODE_MAT_MLP, 497 AUDIO_FORMAT_CODE_DST, 498 AUDIO_FORMAT_CODE_WMAPRO, 499 AUDIO_FORMAT_CODE_LAST, 500 AUDIO_FORMAT_CODE_COUNT = 501 AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST 502 }; 503 504 struct audio_mode { 505 /* ucData[0] [6:3] */ 506 enum audio_format_code format_code; 507 /* ucData[0] [2:0] */ 508 uint8_t channel_count; 509 /* ucData[1] */ 510 union audio_sample_rates sample_rates; 511 union { 512 /* for LPCM */ 513 uint8_t sample_size; 514 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */ 515 uint8_t max_bit_rate; 516 /* for Audio Formats 9-15 */ 517 uint8_t vendor_specific; 518 }; 519 }; 520 521 struct audio_info { 522 struct audio_info_flags flags; 523 uint32_t video_latency; 524 uint32_t audio_latency; 525 uint32_t display_index; 526 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS]; 527 uint32_t manufacture_id; 528 uint32_t product_id; 529 /* PortID used for ContainerID when defined */ 530 uint32_t port_id[2]; 531 uint32_t mode_count; 532 /* this field must be last in this struct */ 533 struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT]; 534 }; 535 struct audio_check { 536 unsigned int audio_packet_type; 537 unsigned int max_audiosample_rate; 538 unsigned int acat; 539 }; 540 enum dc_infoframe_type { 541 DC_HDMI_INFOFRAME_TYPE_VENDOR = 0x81, 542 DC_HDMI_INFOFRAME_TYPE_AVI = 0x82, 543 DC_HDMI_INFOFRAME_TYPE_SPD = 0x83, 544 DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84, 545 DC_DP_INFOFRAME_TYPE_PPS = 0x10, 546 }; 547 548 struct dc_info_packet { 549 bool valid; 550 uint8_t hb0; 551 uint8_t hb1; 552 uint8_t hb2; 553 uint8_t hb3; 554 uint8_t sb[32]; 555 }; 556 557 struct dc_info_packet_128 { 558 bool valid; 559 uint8_t hb0; 560 uint8_t hb1; 561 uint8_t hb2; 562 uint8_t hb3; 563 uint8_t sb[128]; 564 }; 565 566 #define DC_PLANE_UPDATE_TIMES_MAX 10 567 568 struct dc_plane_flip_time { 569 unsigned int time_elapsed_in_us[DC_PLANE_UPDATE_TIMES_MAX]; 570 unsigned int index; 571 unsigned int prev_update_time_in_us; 572 }; 573 574 enum dc_psr_state { 575 PSR_STATE0 = 0x0, 576 PSR_STATE1, 577 PSR_STATE1a, 578 PSR_STATE2, 579 PSR_STATE2a, 580 PSR_STATE2b, 581 PSR_STATE3, 582 PSR_STATE3Init, 583 PSR_STATE4, 584 PSR_STATE4a, 585 PSR_STATE4b, 586 PSR_STATE4c, 587 PSR_STATE4d, 588 PSR_STATE4_FULL_FRAME, 589 PSR_STATE4a_FULL_FRAME, 590 PSR_STATE4b_FULL_FRAME, 591 PSR_STATE4c_FULL_FRAME, 592 PSR_STATE4_FULL_FRAME_POWERUP, 593 PSR_STATE4_FULL_FRAME_HW_LOCK, 594 PSR_STATE5, 595 PSR_STATE5a, 596 PSR_STATE5b, 597 PSR_STATE5c, 598 PSR_STATE_HWLOCK_MGR, 599 PSR_STATE_POLLVUPDATE, 600 PSR_STATE_RELEASE_HWLOCK_MGR_FULL_FRAME, 601 PSR_STATE_INVALID = 0xFF 602 }; 603 604 struct psr_config { 605 unsigned char psr_version; 606 unsigned int psr_rfb_setup_time; 607 bool psr_exit_link_training_required; 608 bool psr_frame_capture_indication_req; 609 unsigned int psr_sdp_transmit_line_num_deadline; 610 bool allow_smu_optimizations; 611 bool allow_multi_disp_optimizations; 612 /* Panel self refresh 2 selective update granularity required */ 613 bool su_granularity_required; 614 /* psr2 selective update y granularity capability */ 615 uint8_t su_y_granularity; 616 unsigned int line_time_in_us; 617 uint8_t rate_control_caps; 618 uint16_t dsc_slice_height; 619 }; 620 621 union dmcu_psr_level { 622 struct { 623 unsigned int SKIP_CRC:1; 624 unsigned int SKIP_DP_VID_STREAM_DISABLE:1; 625 unsigned int SKIP_PHY_POWER_DOWN:1; 626 unsigned int SKIP_AUX_ACK_CHECK:1; 627 unsigned int SKIP_CRTC_DISABLE:1; 628 unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1; 629 unsigned int SKIP_SMU_NOTIFICATION:1; 630 unsigned int SKIP_AUTO_STATE_ADVANCE:1; 631 unsigned int DISABLE_PSR_ENTRY_ABORT:1; 632 unsigned int SKIP_SINGLE_OTG_DISABLE:1; 633 unsigned int DISABLE_ALPM:1; 634 unsigned int ALPM_DEFAULT_PD_MODE:1; 635 unsigned int RESERVED:20; 636 } bits; 637 unsigned int u32all; 638 }; 639 640 enum physical_phy_id { 641 PHYLD_0, 642 PHYLD_1, 643 PHYLD_2, 644 PHYLD_3, 645 PHYLD_4, 646 PHYLD_5, 647 PHYLD_6, 648 PHYLD_7, 649 PHYLD_8, 650 PHYLD_9, 651 PHYLD_COUNT, 652 PHYLD_UNKNOWN = (-1L) 653 }; 654 655 enum phy_type { 656 PHY_TYPE_UNKNOWN = 1, 657 PHY_TYPE_PCIE_PHY = 2, 658 PHY_TYPE_UNIPHY = 3, 659 }; 660 661 struct psr_context { 662 /* ddc line */ 663 enum channel_id channel; 664 /* Transmitter id */ 665 enum transmitter transmitterId; 666 /* Engine Id is used for Dig Be source select */ 667 enum engine_id engineId; 668 /* Controller Id used for Dig Fe source select */ 669 enum controller_id controllerId; 670 /* Pcie or Uniphy */ 671 enum phy_type phyType; 672 /* Physical PHY Id used by SMU interpretation */ 673 enum physical_phy_id smuPhyId; 674 /* Vertical total pixels from crtc timing. 675 * This is used for static screen detection. 676 * ie. If we want to detect half a frame, 677 * we use this to determine the hyst lines. 678 */ 679 unsigned int crtcTimingVerticalTotal; 680 /* PSR supported from panel capabilities and 681 * current display configuration 682 */ 683 bool psrSupportedDisplayConfig; 684 /* Whether fast link training is supported by the panel */ 685 bool psrExitLinkTrainingRequired; 686 /* If RFB setup time is greater than the total VBLANK time, 687 * it is not possible for the sink to capture the video frame 688 * in the same frame the SDP is sent. In this case, 689 * the frame capture indication bit should be set and an extra 690 * static frame should be transmitted to the sink. 691 */ 692 bool psrFrameCaptureIndicationReq; 693 /* Set the last possible line SDP may be transmitted without violating 694 * the RFB setup time or entering the active video frame. 695 */ 696 unsigned int sdpTransmitLineNumDeadline; 697 /* The VSync rate in Hz used to calculate the 698 * step size for smooth brightness feature 699 */ 700 unsigned int vsync_rate_hz; 701 unsigned int skipPsrWaitForPllLock; 702 unsigned int numberOfControllers; 703 /* Unused, for future use. To indicate that first changed frame from 704 * state3 shouldn't result in psr_inactive, but rather to perform 705 * an automatic single frame rfb_update. 706 */ 707 bool rfb_update_auto_en; 708 /* Number of frame before entering static screen */ 709 unsigned int timehyst_frames; 710 /* Partial frames before entering static screen */ 711 unsigned int hyst_lines; 712 /* # of repeated AUX transaction attempts to make before 713 * indicating failure to the driver 714 */ 715 unsigned int aux_repeats; 716 /* Controls hw blocks to power down during PSR active state */ 717 union dmcu_psr_level psr_level; 718 /* Controls additional delay after remote frame capture before 719 * continuing powerd own 720 */ 721 unsigned int frame_delay; 722 bool allow_smu_optimizations; 723 bool allow_multi_disp_optimizations; 724 /* Panel self refresh 2 selective update granularity required */ 725 bool su_granularity_required; 726 /* psr2 selective update y granularity capability */ 727 uint8_t su_y_granularity; 728 unsigned int line_time_in_us; 729 uint8_t rate_control_caps; 730 uint16_t dsc_slice_height; 731 }; 732 733 struct colorspace_transform { 734 struct fixed31_32 matrix[12]; 735 bool enable_remap; 736 }; 737 738 enum i2c_mot_mode { 739 I2C_MOT_UNDEF, 740 I2C_MOT_TRUE, 741 I2C_MOT_FALSE 742 }; 743 744 struct AsicStateEx { 745 unsigned int memoryClock; 746 unsigned int displayClock; 747 unsigned int engineClock; 748 unsigned int maxSupportedDppClock; 749 unsigned int dppClock; 750 unsigned int socClock; 751 unsigned int dcfClockDeepSleep; 752 unsigned int fClock; 753 unsigned int phyClock; 754 }; 755 756 757 enum dc_clock_type { 758 DC_CLOCK_TYPE_DISPCLK = 0, 759 DC_CLOCK_TYPE_DPPCLK = 1, 760 }; 761 762 struct dc_clock_config { 763 uint32_t max_clock_khz; 764 uint32_t min_clock_khz; 765 uint32_t bw_requirequired_clock_khz; 766 uint32_t current_clock_khz;/*current clock in use*/ 767 }; 768 769 struct hw_asic_id { 770 uint32_t chip_id; 771 uint32_t chip_family; 772 uint32_t pci_revision_id; 773 uint32_t hw_internal_rev; 774 uint32_t vram_type; 775 uint32_t vram_width; 776 uint32_t feature_flags; 777 uint32_t fake_paths_num; 778 void *atombios_base_address; 779 }; 780 781 struct dc_context { 782 struct dc *dc; 783 784 void *driver_context; /* e.g. amdgpu_device */ 785 struct dal_logger *logger; 786 struct dc_perf_trace *perf_trace; 787 void *cgs_device; 788 789 enum dce_environment dce_environment; 790 struct hw_asic_id asic_id; 791 792 /* todo: below should probably move to dc. to facilitate removal 793 * of AS we will store these here 794 */ 795 enum dce_version dce_version; 796 struct dc_bios *dc_bios; 797 bool created_bios; 798 struct gpio_service *gpio_service; 799 uint32_t dc_sink_id_count; 800 uint32_t dc_stream_id_count; 801 uint32_t dc_edp_id_count; 802 uint64_t fbc_gpu_addr; 803 struct dc_dmub_srv *dmub_srv; 804 struct cp_psp cp_psp; 805 uint32_t *dcn_reg_offsets; 806 uint32_t *nbio_reg_offsets; 807 uint32_t *clk_reg_offsets; 808 }; 809 810 /* DSC DPCD capabilities */ 811 union dsc_slice_caps1 { 812 struct { 813 uint8_t NUM_SLICES_1 : 1; 814 uint8_t NUM_SLICES_2 : 1; 815 uint8_t RESERVED : 1; 816 uint8_t NUM_SLICES_4 : 1; 817 uint8_t NUM_SLICES_6 : 1; 818 uint8_t NUM_SLICES_8 : 1; 819 uint8_t NUM_SLICES_10 : 1; 820 uint8_t NUM_SLICES_12 : 1; 821 } bits; 822 uint8_t raw; 823 }; 824 825 union dsc_slice_caps2 { 826 struct { 827 uint8_t NUM_SLICES_16 : 1; 828 uint8_t NUM_SLICES_20 : 1; 829 uint8_t NUM_SLICES_24 : 1; 830 uint8_t RESERVED : 5; 831 } bits; 832 uint8_t raw; 833 }; 834 835 union dsc_color_formats { 836 struct { 837 uint8_t RGB : 1; 838 uint8_t YCBCR_444 : 1; 839 uint8_t YCBCR_SIMPLE_422 : 1; 840 uint8_t YCBCR_NATIVE_422 : 1; 841 uint8_t YCBCR_NATIVE_420 : 1; 842 uint8_t RESERVED : 3; 843 } bits; 844 uint8_t raw; 845 }; 846 847 union dsc_color_depth { 848 struct { 849 uint8_t RESERVED1 : 1; 850 uint8_t COLOR_DEPTH_8_BPC : 1; 851 uint8_t COLOR_DEPTH_10_BPC : 1; 852 uint8_t COLOR_DEPTH_12_BPC : 1; 853 uint8_t RESERVED2 : 3; 854 } bits; 855 uint8_t raw; 856 }; 857 858 struct dsc_dec_dpcd_caps { 859 bool is_dsc_supported; 860 uint8_t dsc_version; 861 int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */ 862 union dsc_slice_caps1 slice_caps1; 863 union dsc_slice_caps2 slice_caps2; 864 int32_t lb_bit_depth; 865 bool is_block_pred_supported; 866 int32_t edp_max_bits_per_pixel; /* Valid only in eDP */ 867 union dsc_color_formats color_formats; 868 union dsc_color_depth color_depth; 869 int32_t throughput_mode_0_mps; /* In MPs */ 870 int32_t throughput_mode_1_mps; /* In MPs */ 871 int32_t max_slice_width; 872 uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */ 873 874 /* Extended DSC caps */ 875 uint32_t branch_overall_throughput_0_mps; /* In MPs */ 876 uint32_t branch_overall_throughput_1_mps; /* In MPs */ 877 uint32_t branch_max_line_width; 878 bool is_dp; /* Decoded format */ 879 }; 880 881 struct hblank_expansion_dpcd_caps { 882 bool expansion_supported; 883 bool reduction_supported; 884 bool buffer_unit_bytes; /* True: buffer size in bytes. False: buffer size in pixels*/ 885 bool buffer_per_port; /* True: buffer size per port. False: buffer size per lane*/ 886 uint32_t buffer_size; /* Add 1 to value and multiply by 32 */ 887 }; 888 889 struct dc_golden_table { 890 uint16_t dc_golden_table_ver; 891 uint32_t aux_dphy_rx_control0_val; 892 uint32_t aux_dphy_tx_control_val; 893 uint32_t aux_dphy_rx_control1_val; 894 uint32_t dc_gpio_aux_ctrl_0_val; 895 uint32_t dc_gpio_aux_ctrl_1_val; 896 uint32_t dc_gpio_aux_ctrl_2_val; 897 uint32_t dc_gpio_aux_ctrl_3_val; 898 uint32_t dc_gpio_aux_ctrl_4_val; 899 uint32_t dc_gpio_aux_ctrl_5_val; 900 }; 901 902 enum dc_gpu_mem_alloc_type { 903 DC_MEM_ALLOC_TYPE_GART, 904 DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 905 DC_MEM_ALLOC_TYPE_INVISIBLE_FRAME_BUFFER, 906 DC_MEM_ALLOC_TYPE_AGP 907 }; 908 909 enum dc_link_encoding_format { 910 DC_LINK_ENCODING_UNSPECIFIED = 0, 911 DC_LINK_ENCODING_DP_8b_10b, 912 DC_LINK_ENCODING_DP_128b_132b, 913 DC_LINK_ENCODING_HDMI_TMDS, 914 DC_LINK_ENCODING_HDMI_FRL 915 }; 916 917 enum dc_psr_version { 918 DC_PSR_VERSION_1 = 0, 919 DC_PSR_VERSION_SU_1 = 1, 920 DC_PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 921 }; 922 923 /* Possible values of display_endpoint_id.endpoint */ 924 enum display_endpoint_type { 925 DISPLAY_ENDPOINT_PHY = 0, /* Physical connector. */ 926 DISPLAY_ENDPOINT_USB4_DPIA, /* USB4 DisplayPort tunnel. */ 927 DISPLAY_ENDPOINT_UNKNOWN = -1 928 }; 929 930 /* Extends graphics_object_id with an additional member 'ep_type' for 931 * distinguishing between physical endpoints (with entries in BIOS connector table) and 932 * logical endpoints. 933 */ 934 struct display_endpoint_id { 935 struct graphics_object_id link_id; 936 enum display_endpoint_type ep_type; 937 }; 938 939 enum backlight_control_type { 940 BACKLIGHT_CONTROL_PWM = 0, 941 BACKLIGHT_CONTROL_VESA_AUX = 1, 942 BACKLIGHT_CONTROL_AMD_AUX = 2, 943 }; 944 945 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 946 #define MAX_CRC_WINDOW_NUM 2 947 948 struct otg_phy_mux { 949 uint8_t phy_output_num; 950 uint8_t otg_output_num; 951 }; 952 953 struct crc_window { 954 struct rect rect; 955 bool enable; 956 }; 957 #endif 958 959 enum dc_detect_reason { 960 DETECT_REASON_BOOT, 961 DETECT_REASON_RESUMEFROMS3S4, 962 DETECT_REASON_HPD, 963 DETECT_REASON_HPDRX, 964 DETECT_REASON_FALLBACK, 965 DETECT_REASON_RETRAIN, 966 DETECT_REASON_TDR, 967 }; 968 969 struct dc_link_status { 970 bool link_active; 971 struct dpcd_caps *dpcd_caps; 972 }; 973 974 union hdcp_rx_caps { 975 struct { 976 uint8_t version; 977 uint8_t reserved; 978 struct { 979 uint8_t repeater : 1; 980 uint8_t hdcp_capable : 1; 981 uint8_t reserved : 6; 982 } byte0; 983 } fields; 984 uint8_t raw[3]; 985 }; 986 987 union hdcp_bcaps { 988 struct { 989 uint8_t HDCP_CAPABLE:1; 990 uint8_t REPEATER:1; 991 uint8_t RESERVED:6; 992 } bits; 993 uint8_t raw; 994 }; 995 996 struct hdcp_caps { 997 union hdcp_rx_caps rx_caps; 998 union hdcp_bcaps bcaps; 999 }; 1000 1001 /* DP MST stream allocation (payload bandwidth number) */ 1002 struct link_mst_stream_allocation { 1003 /* DIG front */ 1004 const struct stream_encoder *stream_enc; 1005 /* HPO DP Stream Encoder */ 1006 const struct hpo_dp_stream_encoder *hpo_dp_stream_enc; 1007 /* associate DRM payload table with DC stream encoder */ 1008 uint8_t vcp_id; 1009 /* number of slots required for the DP stream in transport packet */ 1010 uint8_t slot_count; 1011 }; 1012 1013 #define MAX_CONTROLLER_NUM 6 1014 1015 /* DP MST stream allocation table */ 1016 struct link_mst_stream_allocation_table { 1017 /* number of DP video streams */ 1018 int stream_count; 1019 /* array of stream allocations */ 1020 struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM]; 1021 }; 1022 1023 /* PSR feature flags */ 1024 struct psr_settings { 1025 bool psr_feature_enabled; // PSR is supported by sink 1026 bool psr_allow_active; // PSR is currently active 1027 enum dc_psr_version psr_version; // Internal PSR version, determined based on DPCD 1028 bool psr_vtotal_control_support; // Vtotal control is supported by sink 1029 unsigned long long psr_dirty_rects_change_timestamp_ns; // for delay of enabling PSR-SU 1030 1031 /* These parameters are calculated in Driver, 1032 * based on display timing and Sink capabilities. 1033 * If VBLANK region is too small and Sink takes a long time 1034 * to set up RFB, it may take an extra frame to enter PSR state. 1035 */ 1036 bool psr_frame_capture_indication_req; 1037 unsigned int psr_sdp_transmit_line_num_deadline; 1038 uint8_t force_ffu_mode; 1039 unsigned int psr_power_opt; 1040 1041 /** 1042 * Some panels cannot handle idle pattern during PSR entry. 1043 * To power down phy before disable stream to avoid sending 1044 * idle pattern. 1045 */ 1046 uint8_t power_down_phy_before_disable_stream; 1047 }; 1048 1049 enum replay_coasting_vtotal_type { 1050 PR_COASTING_TYPE_NOM = 0, 1051 PR_COASTING_TYPE_STATIC, 1052 PR_COASTING_TYPE_FULL_SCREEN_VIDEO, 1053 PR_COASTING_TYPE_TEST_HARNESS, 1054 PR_COASTING_TYPE_NUM, 1055 }; 1056 1057 enum replay_link_off_frame_count_level { 1058 PR_LINK_OFF_FRAME_COUNT_FAIL = 0x0, 1059 PR_LINK_OFF_FRAME_COUNT_GOOD = 0x2, 1060 PR_LINK_OFF_FRAME_COUNT_BEST = 0x6, 1061 }; 1062 1063 /* 1064 * This is general Interface for Replay to 1065 * set an 32 bit variable to dmub 1066 * The Message_type indicates which variable 1067 * passed to DMUB. 1068 */ 1069 enum replay_FW_Message_type { 1070 Replay_Msg_Not_Support = -1, 1071 Replay_Set_Timing_Sync_Supported, 1072 Replay_Set_Residency_Frameupdate_Timer, 1073 Replay_Set_Pseudo_VTotal, 1074 Replay_Disabled_Adaptive_Sync_SDP, 1075 Replay_Set_General_Cmd, 1076 }; 1077 1078 union replay_error_status { 1079 struct { 1080 unsigned int STATE_TRANSITION_ERROR :1; 1081 unsigned int LINK_CRC_ERROR :1; 1082 unsigned int DESYNC_ERROR :1; 1083 unsigned int RESERVED_3 :1; 1084 unsigned int LOW_RR_INCORRECT_VTOTAL :1; 1085 unsigned int NO_DOUBLED_RR :1; 1086 unsigned int RESERVED_6_7 :2; 1087 } bits; 1088 unsigned char raw; 1089 }; 1090 1091 union replay_low_refresh_rate_enable_options { 1092 struct { 1093 //BIT[0-3]: Replay Low Hz Support control 1094 unsigned int ENABLE_LOW_RR_SUPPORT :1; 1095 unsigned int SKIP_ASIC_CHECK :1; 1096 unsigned int RESERVED_2_3 :2; 1097 //BIT[4-15]: Replay Low Hz Enable Scenarios 1098 unsigned int ENABLE_STATIC_SCREEN :1; 1099 unsigned int ENABLE_FULL_SCREEN_VIDEO :1; 1100 unsigned int ENABLE_GENERAL_UI :1; 1101 unsigned int RESERVED_7_15 :9; 1102 //BIT[16-31]: Replay Low Hz Enable Check 1103 unsigned int ENABLE_STATIC_FLICKER_CHECK :1; 1104 unsigned int RESERVED_17_31 :15; 1105 } bits; 1106 unsigned int raw; 1107 }; 1108 1109 struct replay_config { 1110 /* Replay feature is supported */ 1111 bool replay_supported; 1112 /* Replay caps support DPCD & EDID caps*/ 1113 bool replay_cap_support; 1114 /* Power opt flags that are supported */ 1115 unsigned int replay_power_opt_supported; 1116 /* SMU optimization is supported */ 1117 bool replay_smu_opt_supported; 1118 /* Replay enablement option */ 1119 unsigned int replay_enable_option; 1120 /* Replay debug flags */ 1121 uint32_t debug_flags; 1122 /* Replay sync is supported */ 1123 bool replay_timing_sync_supported; 1124 /* Replay Disable desync error check. */ 1125 bool force_disable_desync_error_check; 1126 /* Replay Received Desync Error HPD. */ 1127 bool received_desync_error_hpd; 1128 /* Replay feature is supported long vblank */ 1129 bool replay_support_fast_resync_in_ultra_sleep_mode; 1130 /* Replay error status */ 1131 union replay_error_status replay_error_status; 1132 /* Replay Low Hz enable Options */ 1133 union replay_low_refresh_rate_enable_options low_rr_enable_options; 1134 /* Replay coasting vtotal is within low refresh rate range. */ 1135 bool low_rr_activated; 1136 /* Replay low refresh rate supported*/ 1137 bool low_rr_supported; 1138 /* Replay Video Conferencing Optimization Enabled */ 1139 bool replay_video_conferencing_optimization_enabled; 1140 }; 1141 1142 /* Replay feature flags*/ 1143 struct replay_settings { 1144 /* Replay configuration */ 1145 struct replay_config config; 1146 /* Replay feature is ready for activating */ 1147 bool replay_feature_enabled; 1148 /* Replay is currently active */ 1149 bool replay_allow_active; 1150 /* Replay is currently active */ 1151 bool replay_allow_long_vblank; 1152 /* Power opt flags that are activated currently */ 1153 unsigned int replay_power_opt_active; 1154 /* SMU optimization is enabled */ 1155 bool replay_smu_opt_enable; 1156 /* Current Coasting vtotal */ 1157 uint32_t coasting_vtotal; 1158 /* Coasting vtotal table */ 1159 uint32_t coasting_vtotal_table[PR_COASTING_TYPE_NUM]; 1160 /* Defer Update Coasting vtotal table */ 1161 uint32_t defer_update_coasting_vtotal_table[PR_COASTING_TYPE_NUM]; 1162 /* Maximum link off frame count */ 1163 uint32_t link_off_frame_count; 1164 /* Replay pseudo vtotal for low refresh rate*/ 1165 uint16_t low_rr_full_screen_video_pseudo_vtotal; 1166 /* Replay last pseudo vtotal set to DMUB */ 1167 uint16_t last_pseudo_vtotal; 1168 /* Replay desync error */ 1169 uint32_t replay_desync_error_fail_count; 1170 }; 1171 1172 /* To split out "global" and "per-panel" config settings. 1173 * Add a struct dc_panel_config under dc_link 1174 */ 1175 struct dc_panel_config { 1176 /* extra panel power sequence parameters */ 1177 struct pps { 1178 unsigned int extra_t3_ms; 1179 unsigned int extra_t7_ms; 1180 unsigned int extra_delay_backlight_off; 1181 unsigned int extra_post_t7_ms; 1182 unsigned int extra_pre_t11_ms; 1183 unsigned int extra_t12_ms; 1184 unsigned int extra_post_OUI_ms; 1185 } pps; 1186 /* nit brightness */ 1187 struct nits_brightness { 1188 unsigned int peak; /* nits */ 1189 unsigned int max_avg; /* nits */ 1190 unsigned int min; /* 1/10000 nits */ 1191 unsigned int max_nonboost_brightness_millinits; 1192 unsigned int min_brightness_millinits; 1193 } nits_brightness; 1194 /* PSR */ 1195 struct psr { 1196 bool disable_psr; 1197 bool disallow_psrsu; 1198 bool disallow_replay; 1199 bool rc_disable; 1200 bool rc_allow_static_screen; 1201 bool rc_allow_fullscreen_VPB; 1202 unsigned int replay_enable_option; 1203 } psr; 1204 /* ABM */ 1205 struct varib { 1206 unsigned int varibright_feature_enable; 1207 unsigned int def_varibright_level; 1208 unsigned int abm_config_setting; 1209 } varib; 1210 /* edp DSC */ 1211 struct dsc { 1212 bool disable_dsc_edp; 1213 unsigned int force_dsc_edp_policy; 1214 } dsc; 1215 /* eDP ILR */ 1216 struct ilr { 1217 bool optimize_edp_link_rate; /* eDP ILR */ 1218 } ilr; 1219 }; 1220 1221 #define MAX_SINKS_PER_LINK 4 1222 1223 /* 1224 * USB4 DPIA BW ALLOCATION STRUCTS 1225 */ 1226 struct dc_dpia_bw_alloc { 1227 int remote_sink_req_bw[MAX_SINKS_PER_LINK]; // BW requested by remote sinks 1228 int link_verified_bw; // The Verified BW that link can allocated and use that has been verified already 1229 int link_max_bw; // The Max BW that link can require/support 1230 int allocated_bw; // The Actual Allocated BW for this DPIA 1231 int estimated_bw; // The estimated available BW for this DPIA 1232 int bw_granularity; // BW Granularity 1233 int dp_overhead; // DP overhead in dp tunneling 1234 bool bw_alloc_enabled; // The BW Alloc Mode Support is turned ON for all 3: DP-Tx & Dpia & CM 1235 uint8_t nrd_max_lane_count; // Non-reduced max lane count 1236 uint8_t nrd_max_link_rate; // Non-reduced max link rate 1237 }; 1238 1239 enum dc_hpd_enable_select { 1240 HPD_EN_FOR_ALL_EDP = 0, 1241 HPD_EN_FOR_PRIMARY_EDP_ONLY, 1242 HPD_EN_FOR_SECONDARY_EDP_ONLY, 1243 }; 1244 1245 enum dc_cm2_shaper_3dlut_setting { 1246 DC_CM2_SHAPER_3DLUT_SETTING_BYPASS_ALL, 1247 DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER, 1248 /* Bypassing Shaper will always bypass 3DLUT */ 1249 DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT 1250 }; 1251 1252 enum dc_cm2_gpu_mem_layout { 1253 DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_RGB, 1254 DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_BGR, 1255 DC_CM2_GPU_MEM_LAYOUT_1D_PACKED_LINEAR 1256 }; 1257 1258 enum dc_cm2_gpu_mem_pixel_component_order { 1259 DC_CM2_GPU_MEM_PIXEL_COMPONENT_ORDER_RGBA, 1260 }; 1261 1262 enum dc_cm2_gpu_mem_format { 1263 DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12MSB, 1264 DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12LSB, 1265 DC_CM2_GPU_MEM_FORMAT_16161616_FLOAT_FP1_5_10 1266 }; 1267 1268 struct dc_cm2_gpu_mem_format_parameters { 1269 enum dc_cm2_gpu_mem_format format; 1270 union { 1271 struct { 1272 /* bias & scale for float only */ 1273 uint16_t bias; 1274 uint16_t scale; 1275 } float_params; 1276 }; 1277 }; 1278 1279 enum dc_cm2_gpu_mem_size { 1280 DC_CM2_GPU_MEM_SIZE_171717, 1281 DC_CM2_GPU_MEM_SIZE_TRANSFORMED, 1282 }; 1283 1284 struct dc_cm2_gpu_mem_parameters { 1285 struct dc_plane_address addr; 1286 enum dc_cm2_gpu_mem_layout layout; 1287 struct dc_cm2_gpu_mem_format_parameters format_params; 1288 enum dc_cm2_gpu_mem_pixel_component_order component_order; 1289 enum dc_cm2_gpu_mem_size size; 1290 uint16_t bit_depth; 1291 }; 1292 1293 enum dc_cm2_transfer_func_source { 1294 DC_CM2_TRANSFER_FUNC_SOURCE_SYSMEM, 1295 DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM 1296 }; 1297 1298 struct dc_cm2_component_settings { 1299 enum dc_cm2_shaper_3dlut_setting shaper_3dlut_setting; 1300 bool lut1d_enable; 1301 }; 1302 1303 /* 1304 * All pointers in this struct must remain valid for as long as the 3DLUTs are used 1305 */ 1306 struct dc_cm2_func_luts { 1307 const struct dc_transfer_func *shaper; 1308 struct { 1309 enum dc_cm2_transfer_func_source lut3d_src; 1310 union { 1311 const struct dc_3dlut *lut3d_func; 1312 struct dc_cm2_gpu_mem_parameters gpu_mem_params; 1313 }; 1314 bool rmcm_3dlut_shaper_select; 1315 bool mpc_3dlut_enable; 1316 bool rmcm_3dlut_enable; 1317 bool mpc_mcm_post_blend; 1318 uint8_t rmcm_tmz; 1319 } lut3d_data; 1320 const struct dc_transfer_func *lut1d_func; 1321 }; 1322 1323 struct dc_cm2_parameters { 1324 struct dc_cm2_component_settings component_settings; 1325 struct dc_cm2_func_luts cm2_luts; 1326 }; 1327 1328 enum mall_stream_type { 1329 SUBVP_NONE, // subvp not in use 1330 SUBVP_MAIN, // subvp in use, this stream is main stream 1331 SUBVP_PHANTOM, // subvp in use, this stream is a phantom stream 1332 }; 1333 1334 enum dc_power_source_type { 1335 DC_POWER_SOURCE_AC, // wall power 1336 DC_POWER_SOURCE_DC, // battery power 1337 }; 1338 1339 struct dc_state_create_params { 1340 enum dc_power_source_type power_source; 1341 }; 1342 1343 struct dc_commit_streams_params { 1344 struct dc_stream_state **streams; 1345 uint8_t stream_count; 1346 enum dc_power_source_type power_source; 1347 }; 1348 1349 struct set_backlight_level_params { 1350 /* backlight in pwm */ 1351 uint32_t backlight_pwm_u16_16; 1352 /* brightness ramping */ 1353 uint32_t frame_ramp; 1354 /* backlight control type 1355 * 0: PWM backlight control 1356 * 1: VESA AUX backlight control 1357 * 2: AMD AUX backlight control 1358 */ 1359 enum backlight_control_type control_type; 1360 /* backlight in millinits */ 1361 uint32_t backlight_millinits; 1362 /* transition time in ms */ 1363 uint32_t transition_time_in_ms; 1364 /* minimum luminance in nits */ 1365 uint32_t min_luminance; 1366 /* maximum luminance in nits */ 1367 uint32_t max_luminance; 1368 /* minimum backlight in pwm */ 1369 uint32_t min_backlight_pwm; 1370 /* maximum backlight in pwm */ 1371 uint32_t max_backlight_pwm; 1372 /* AUX HW instance */ 1373 uint8_t aux_inst; 1374 }; 1375 1376 enum dc_validate_mode { 1377 /* validate the mode and program HW */ 1378 DC_VALIDATE_MODE_AND_PROGRAMMING = 0, 1379 /* only validate the mode */ 1380 DC_VALIDATE_MODE_ONLY = 1, 1381 /* validate the mode and get the max state (voltage level) */ 1382 DC_VALIDATE_MODE_AND_STATE_INDEX = 2, 1383 }; 1384 1385 struct dc_validation_dpia_set { 1386 const struct dc_link *link; 1387 const struct dc_tunnel_settings *tunnel_settings; 1388 uint32_t required_bw; 1389 }; 1390 1391 #endif /* DC_TYPES_H_ */ 1392