en Copyright 2025 Java http://opengrok.net:8080/history/src/sys/arm/qualcomm/std.ipq4018#7fead5f144a874a317cba29130a76a11629903ea qcom_gcc: begin refactoring sys/dev/qcom_gcc to support multiple chipsetsAlthough the driver structure is almost supportive of multiplechipsets, there's a lot of subtle hard coded IPQ4018 assumptionshere.This is a partial refactor of the driver in order to have a singleqcom_gcc driver that will eventually support multiple chipsets.* rename qcom_gcc_ipq4018 -> qcom_gcc* remove the ipq4018 specific naming from things* create a table to drive probe/attach, with a chipset id to use during attach* migrate the clock register accessors to not be ipq4018 specific* migrate the reset register accessors to not be ipq4018 specificNote this won't compile (yet) for an arm64 kernel because there'sa hard-coded clock tree for an earlier 64 bit MSM part insys/arm64/qualcomm/qcom_gcc.c . That will need to be rolled into thisdriver.Differential Revision: https://reviews.freebsd.org/D49683 List of files: /src/sys/arm/qualcomm/std.ipq4018 Sat, 05 Apr 2025 03:59:58 +0000 Adrian Chadd <adrian@FreeBSD.org> http://opengrok.net:8080/history/src/sys/arm/qualcomm/std.ipq4018#9f32893b05dabedc7f8332ec12e2a944b6543158 qcom_ess_edma: Add the IPQ4018/IPQ4019 ethernet MAC/MDIO driver.This adds the ESS EDMA driver introduced by the IPQ4018/IPQ4019.It provides a number of transmit and receive rings which can be mappedinto virtual ethernet devices, which this driver supports.It's partially integrated into the ar40xx etherswitch which suppliesthe port and some filtering/VPN offload functionality. This driveronly currently supports the per-port options which allow for thevirtual ethernet driver mapping.This was written by reverse engineering the functionality of theethernet switch and ethernet driver support provided by QualcommAtheros via their OpenWRT contributions. The code is all originallyauthored by myself.Differential Revision: https://reviews.freebsd.org/D49027 List of files: /src/sys/arm/qualcomm/std.ipq4018 Wed, 05 Apr 2023 04:36:52 +0000 Adrian Chadd <adrian@FreeBSD.org> http://opengrok.net:8080/history/src/sys/arm/qualcomm/std.ipq4018#e388de98bd0272b4ba237dcd44dcf12360d70d41 ar40xx_switch: add initial switch for the IPQ4018/IPQ4019.Summary:This switch is based off of the AR8327/AR8337 external switch/PHY.However unlike the AR8327/AR8337 it itself doesn't have any PHYs;instead an external PHY connects to it using the PSGMII port.Differential Revision: https://reviews.freebsd.org/D34112Reviewed by: manuThis code is inspired by the ar40xx code in openwrt, which itselfis based on the Qualcomm QCA-SSDK. Both of these sources are, amusingly,BSD licenced - and thus I have included some of the comments in thehardware workaround paths to document some of the magic numbers. List of files: /src/sys/arm/qualcomm/std.ipq4018 Sun, 30 Jan 2022 03:04:19 +0000 Adrian Chadd <adrian@FreeBSD.org> http://opengrok.net:8080/history/src/sys/arm/qualcomm/std.ipq4018#29332c0dcee1e80c9fb871e06c3160bd5deb1b44 qcom_mdio: add initial IPQ4018 MDIO supportThis adds support for the IPQ4018/IPQ4019 MDIO bus. This is used totalk to external PHYs and switches. (There's an internal switchin the IPQ4018/IPQ4019 as well, but it's accessible via MMIO/AXI.)Differential Revision: https://reviews.freebsd.org/D34110Reviewed by: manu List of files: /src/sys/arm/qualcomm/std.ipq4018 Sun, 30 Jan 2022 02:27:58 +0000 Adrian Chadd <adrian@FreeBSD.org> http://opengrok.net:8080/history/src/sys/arm/qualcomm/std.ipq4018#777963afb5a0dba75cdd7117d3070d9486b2ee96 qcom_dwc3: add initial Qualcomm SoC DWC3 controller glueThis adds some very simple DWC3 glue for the IPQ4018/IPQ4019.Other chipsets introduce reset line iteration, some furtherclock line iteration and some customisations; I'll look at addingthose later.This is enough to finally bring up USB 3.0 on my IPQ4018 ASUSRT-58U router. List of files: /src/sys/arm/qualcomm/std.ipq4018 Tue, 28 Dec 2021 02:25:32 +0000 Adrian Chadd <adrian@FreeBSD.org> http://opengrok.net:8080/history/src/sys/arm/qualcomm/std.ipq4018#86f0c3ec13aa6d583a586f343329d15faf22bd75 ipq4018_usb_phy: add USB 2.0 and 3.0 PHY supportThis adds the USB 2.0 and 3.0 PHY support for the IPQ4018/IPQ4019.All it really needs to do is gate the relevant clocks on/off in theright order with the right delays. List of files: /src/sys/arm/qualcomm/std.ipq4018 Tue, 28 Dec 2021 02:21:36 +0000 Adrian Chadd <adrian@FreeBSD.org> http://opengrok.net:8080/history/src/sys/arm/qualcomm/std.ipq4018#d11f81afd5a4a71d5f725950b0592ca212084780 qcom_tcsr: add initial top control and status register (TCSR) supportThe Qualcomm TCSR is some top level glue between multiple IP blocks,both for doing configuration of said IP blocks, some IPC betweenthem (mostly between multiple execution environments - eg trustzoneand non-TZ), and interrupt status bits for them.However, for the IPQ4018/IPQ4019, it only is used as a small subsetof IP block configuration. As for what it actually gets used asfor other Qualcomm chipsets? Well, that'll have to wait.It's a bit of a mess in linux and openwrt. See, every differentSoC support branch ends up with some different TCSR code for it.So instead, I'm going to land a single TCSR driver that I'm goingto use for the IPQ4018/IPQ4019. When I add the next chipset, I'llfigure out how to organise things so there's a single TCSR driverthat works for multiple platforms. List of files: /src/sys/arm/qualcomm/std.ipq4018 Mon, 27 Dec 2021 23:45:40 +0000 Adrian Chadd <adrian@FreeBSD.org> http://opengrok.net:8080/history/src/sys/arm/qualcomm/std.ipq4018#d27ba3088424e53eabc0b0186ed122ec43119501 qcom_qup: add initial v1/v2 QUP SPI driverThe Qualcomm Universal Peripherals Engine (QUP) is a unified SPI and I2Cperipheral that ships with a variety of Qualcomm SoCs.It supports three transfer modes - single PIO, block PIO and DMA.This driver only supports the single PIO mode, which is enough tobootstrap the rest of the SPI NAND/NOR support and means I can dothings like read the Wifi calibration data from NOR. It has somehardware support code for the other transfer modes as well assome support for split transfers (ie, transfers with no read orwrite phase), but I haven't yet implemented those.This driver is based on four sources - the linux driver, the u-bootdriver, some initial work done for APQ8064 by mmel@, and the APQ8064Technical Reference Manual which is surprisingly free and open toread. The linux and u-boot drivers approach a variety of thingscompletely differently, from how PIO is done, the hardware supportfor re-ordering bytes in a transfer word and how the CS linesare used.Tested:* IPQ4018, SPI to NAND/NOR flash, PIO only List of files: /src/sys/arm/qualcomm/std.ipq4018 Mon, 27 Dec 2021 23:27:29 +0000 Adrian Chadd <adrian@FreeBSD.org> http://opengrok.net:8080/history/src/sys/arm/qualcomm/std.ipq4018#cd32ac640b884eda4e34673256b3816897e754d4 Add support for qualcomm clock nodes the the IPQ4018/IPQ4019 clock tree.Summary: I've tested this with cpufreq_dt, SPI and USB. They all seem to work fine.Test Plan: * IPQ4018, bootSubscribers: imp, andrewDifferential Revision: https://reviews.freebsd.org/D33665 List of files: /src/sys/arm/qualcomm/std.ipq4018 Sun, 26 Dec 2021 17:08:57 +0000 Adrian Chadd <adrian@FreeBSD.org> http://opengrok.net:8080/history/src/sys/arm/qualcomm/std.ipq4018#e34a491b35626b4209ef0a195e85a03a1089c572 qcom_clk: add the qualcomm clock nodes for the IPQ4018These clock nodes are used by the IPQ4018/IPQ4019 and derivatives.They're also used by other 32 and 64 bit qualcomm parts; so it'sbest to put these nodes here in a single qcom_clk driver and addto it as we grow new Qualcomm SoC support.Tested:* IPQ4018, bootDifferential Revision: https://reviews.freebsd.org/D33665 List of files: /src/sys/arm/qualcomm/std.ipq4018 Sun, 26 Dec 2021 17:07:21 +0000 Adrian Chadd <adrian@FreeBSD.org> http://opengrok.net:8080/history/src/sys/arm/qualcomm/std.ipq4018#4abe6533e9a2a2252faed907246eab96c4541210 qcom_tlmm: add initial gpio/pinmux controller (TLMM)The qualcomm TLMM (top level mode manager) is their gpio/pinmux hardwarecontroller.Although the pinmux is generic enough to use for the IPQ/APQ serieschips, I'm directly calling the IPQ4018 routines to expedite bring-up.Notably, I'm not yet implementing the interrupt support - it's notrequired at this stage of bring-up.Differential Revision: https://reviews.freebsd.org/D33554 List of files: /src/sys/arm/qualcomm/std.ipq4018 Sun, 19 Dec 2021 04:03:40 +0000 Adrian Chadd <adrian@FreeBSD.org> http://opengrok.net:8080/history/src/sys/arm/qualcomm/std.ipq4018#cfd06987029ac1bf5f6a6be2d87ade7358bd59ca ipq4018: add qcom-gcc-ipq4018 and dependencies into the build* add the extres stuff into the build, I'm going to end up leveraging all of it* include the qcom-gcc-ipq4018 driver which currently implements the hwreset side of the API.Reviewed by: andrew, manu, impDifferential Revision: https://reviews.freebsd.org/D32723 List of files: /src/sys/arm/qualcomm/std.ipq4018 Sun, 31 Oct 2021 03:45:17 +0000 Adrian Chadd <adrian@FreeBSD.org> http://opengrok.net:8080/history/src/sys/arm/qualcomm/std.ipq4018#b12a863a1e14610f6b145f235aa7452602038f9a ipq4018: add initial reset driver support for the clock/reset controller.This implements the "reset controller" side of the clock/reset controller.It's a simple array of registers and bits to set.The register table itself comes from Linux; the rest of the code is areimplementation.It doesn't yet implement or expose the clock side - I have a lot ofreverse engineering to do before that!Reviewed by: andrew, manu, impDifferential Revision: https://reviews.freebsd.org/D32723Obtained from: Linux (registers) List of files: /src/sys/arm/qualcomm/std.ipq4018 Sun, 31 Oct 2021 03:43:27 +0000 Adrian Chadd <adrian@FreeBSD.org> http://opengrok.net:8080/history/src/sys/arm/qualcomm/std.ipq4018#d3514c294207bd5cda7f4276ebff5235bb239b8a ipq401x: add MP core start-up path for the CPU regulator/clock gate usedThis code implements the "kpssv2" flavour of CPU regulator/clock gatingin Linux. It's used by at least the ipq4018/4019 to power on and offCPU cores.This is based on the Linux implementation - the register definitionsand values are from Linux and I've reverse engineered the sequencingrequirements.The MP bring-up is:* set cold boot address via an SCM call - this is the address used by the bootloader/TZ firmware to jump to when the CPUs boot* power down the LDO feeding the CPU core and wait for it to settle* program in the right set of LDO and power tree configuration for the CPU regulator to power up the core. Unfortunately these are magic numbers that I've not found documented anywhere.* (I think) power up the shared L2 cache connect if it isn't.* Clamp the power into the core down; put the core into reset* Unclamp the power rail; release reset; and then set the core to boot.The MP core will then boot the bootloader/TZ firmware and thenwill wait until an incoming interrupt kicks it to start @ mpentry.Tested:* IPQ4019, 4 CPUsRelease APsCPU(3) applied BP hardening: not necessaryCPU(1) applied BP hardening: not necessaryCPU(2) applied BP hardening: not necessaryReviewed by: andrew, manu, impDifferential Revision: https://reviews.freebsd.org/D32723 List of files: /src/sys/arm/qualcomm/std.ipq4018 Sat, 30 Oct 2021 04:27:02 +0000 Adrian Chadd <adrian@FreeBSD.org> http://opengrok.net:8080/history/src/sys/arm/qualcomm/std.ipq4018#960e65d23aaa55dd00255e95f14c2f6256a4fce3 qcom: add initial SCM legacy APIThis is a very simple implementation of Qualcomm's SCM API.It is just the structure/field definitions and the atomic SCMcall which doesn't use the structs yet - it uses the fielddefinitions inside registers.I've tested that setting the cold boot address via the atomicAPI is fine - Linux does the same thing. But not all SCM callscan be done via the legacy API.This is a reimplementation based on the Linux qualcomm SCM legacycode and definitions.Tested:* Qualcomm IPQ4018 AP, as part of other changes for doing SMP bring-upReviewed by: andrew, manu, impDifferential Revision: https://reviews.freebsd.org/D32723 List of files: /src/sys/arm/qualcomm/std.ipq4018 Sat, 30 Oct 2021 03:34:08 +0000 Adrian Chadd <adrian@FreeBSD.org> http://opengrok.net:8080/history/src/sys/arm/qualcomm/std.ipq4018#a516ccc4ae04975a54882651104c4a0369c3eaba ipq4018: add SoC reset and qcom_rnd driverSummary:This is enough to allow this ASUS router to reboot successfully.I tried the watchdog path and although it fires, it isn't rebooting!It's just hanging, likely somewhere in TZ.This is the MVP required to initialise and consume random data fromthe QCA PRNG hardware found on the IPQ401x.Test Plan: * ASUS RT-AC58U router, IPQ4019Subscribers: imp, andrewDifferential Revision: https://reviews.freebsd.org/D32723 List of files: /src/sys/arm/qualcomm/std.ipq4018 Thu, 21 Oct 2021 03:08:56 +0000 Adrian Chadd <adrian@FreeBSD.org> http://opengrok.net:8080/history/src/sys/arm/qualcomm/std.ipq4018#02438ce5fd1892e3f59e4f1e83a0ac810396853f ipq4018: add initial IPQ4018/IPQ4019 supportThis is for the Qualcomm Atheros quad-core ARMv7 SoC with built-in2x2 2GHz and 5GHz ath10k devices.It's enough (with an upcoming set of config files) to netbooton an ASUS router I have here and get to a single core mountrootprompt. List of files: /src/sys/arm/qualcomm/std.ipq4018 Sat, 16 Oct 2021 18:47:44 +0000 Adrian Chadd <adrian@FreeBSD.org> http://opengrok.net:8080/history/src/sys/arm/qualcomm/std.ipq4018#7fead5f144a874a317cba29130a76a11629903ea qcom_gcc: begin refactoring sys/dev/qcom_gcc to support multiple chipsetsAlthough the driver structure is almost supportive of multiplechipsets, there's a lot of subtle hard coded IPQ4018 assumptionshere.This is a partial refactor of the driver in order to have a singleqcom_gcc driver that will eventually support multiple chipsets.* rename qcom_gcc_ipq4018 -> qcom_gcc* remove the ipq4018 specific naming from things* create a table to drive probe/attach, with a chipset id to use during attach* migrate the clock register accessors to not be ipq4018 specific* migrate the reset register accessors to not be ipq4018 specificNote this won't compile (yet) for an arm64 kernel because there'sa hard-coded clock tree for an earlier 64 bit MSM part insys/arm64/qualcomm/qcom_gcc.c . That will need to be rolled into thisdriver.Differential Revision: https://reviews.freebsd.org/D49683 List of files: /src/sys/arm/qualcomm/std.ipq4018 Sat, 05 Apr 2025 03:59:58 +0000 Adrian Chadd <adrian@FreeBSD.org> http://opengrok.net:8080/history/src/sys/arm/qualcomm/std.ipq4018#9f32893b05dabedc7f8332ec12e2a944b6543158 qcom_ess_edma: Add the IPQ4018/IPQ4019 ethernet MAC/MDIO driver.This adds the ESS EDMA driver introduced by the IPQ4018/IPQ4019.It provides a number of transmit and receive rings which can be mappedinto virtual ethernet devices, which this driver supports.It's partially integrated into the ar40xx etherswitch which suppliesthe port and some filtering/VPN offload functionality. This driveronly currently supports the per-port options which allow for thevirtual ethernet driver mapping.This was written by reverse engineering the functionality of theethernet switch and ethernet driver support provided by QualcommAtheros via their OpenWRT contributions. The code is all originallyauthored by myself.Differential Revision: https://reviews.freebsd.org/D49027 List of files: /src/sys/arm/qualcomm/std.ipq4018 Wed, 05 Apr 2023 04:36:52 +0000 Adrian Chadd <adrian@FreeBSD.org> http://opengrok.net:8080/history/src/sys/arm/qualcomm/std.ipq4018#e388de98bd0272b4ba237dcd44dcf12360d70d41 ar40xx_switch: add initial switch for the IPQ4018/IPQ4019.Summary:This switch is based off of the AR8327/AR8337 external switch/PHY.However unlike the AR8327/AR8337 it itself doesn't have any PHYs;instead an external PHY connects to it using the PSGMII port.Differential Revision: https://reviews.freebsd.org/D34112Reviewed by: manuThis code is inspired by the ar40xx code in openwrt, which itselfis based on the Qualcomm QCA-SSDK. Both of these sources are, amusingly,BSD licenced - and thus I have included some of the comments in thehardware workaround paths to document some of the magic numbers. List of files: /src/sys/arm/qualcomm/std.ipq4018 Sun, 30 Jan 2022 03:04:19 +0000 Adrian Chadd <adrian@FreeBSD.org>