49 #define	GETREG(bas, reg)	\  argument
50     bus_space_read_4((bas)->bst, (bas)->bsh, (reg))
51 #define	SETREG(bas, reg, value)	\  argument
52     bus_space_write_4((bas)->bst, (bas)->bsh, (reg), (value))
59 static int	msm_probe(struct uart_bas *bas);
60 static void	msm_init(struct uart_bas *bas, int, int, int, int);
61 static void	msm_term(struct uart_bas *bas);
62 static void	msm_putc(struct uart_bas *bas, int);
63 static int	msm_rxready(struct uart_bas *bas);
64 static int	msm_getc(struct uart_bas *bas, struct mtx *mtx);
69 msm_uart_param(struct uart_bas *bas, int baudrate, int databits,  in msm_uart_param()  argument
121 	uart_setreg(bas, UART_DM_MR2, ulcon);  in msm_uart_param()
122 	uart_barrier(bas);  in msm_uart_param()
137 msm_probe(struct uart_bas *bas)  in msm_probe()  argument
140 	bas->regiowidth = 4;  in msm_probe()
146 msm_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,  in msm_init()  argument
150 	if (bas->rclk == 0)  in msm_init()
151 		bas->rclk = DEF_CLK;  in msm_init()
153 	KASSERT(bas->rclk != 0, ("msm_init: Invalid rclk"));  in msm_init()
156 	msm_uart_param(bas, baudrate, databits, stopbits, parity);  in msm_init()
162 	uart_setreg(bas, UART_DM_MR1, 0x0);  in msm_init()
165 	uart_setreg(bas, UART_DM_IMR, 0);  in msm_init()
172 	uart_setreg(bas, UART_DM_TFWR, UART_DM_TFW_VALUE);  in msm_init()
175 	uart_setreg(bas, UART_DM_RFWR, UART_DM_RFW_VALUE);  in msm_init()
181 	uart_setreg(bas, UART_DM_IPR, UART_DM_STALE_TIMEOUT_LSB);  in msm_init()
184 	uart_setreg(bas, UART_DM_IRDA, 0x0);  in msm_init()
191 	uart_setreg(bas, UART_DM_HCR, 0x0);  in msm_init()
194 	SETREG(bas, UART_DM_CR, UART_DM_RESET_TX);  in msm_init()
195 	SETREG(bas, UART_DM_CR, UART_DM_RESET_RX);  in msm_init()
196 	SETREG(bas, UART_DM_CR, UART_DM_RESET_ERROR_STATUS);  in msm_init()
197 	SETREG(bas, UART_DM_CR, UART_DM_RESET_BREAK_INT);  in msm_init()
198 	SETREG(bas, UART_DM_CR, UART_DM_RESET_STALE_INT);  in msm_init()
201 	uart_setreg(bas, UART_DM_DMEN, UART_DM_DMEN_RX_SC_ENABLE);  in msm_init()
204 	uart_setreg(bas, UART_DM_CR, UART_DM_CR_RX_ENABLE);  in msm_init()
205 	uart_setreg(bas, UART_DM_CR, UART_DM_CR_TX_ENABLE);  in msm_init()
207 	uart_barrier(bas);  in msm_init()
211 msm_term(struct uart_bas *bas)  in msm_term()  argument
218 msm_putc(struct uart_bas *bas, int c)  in msm_putc()  argument
233 	if (!(uart_getreg(bas, UART_DM_SR) & UART_DM_SR_TXEMT)) {  in msm_putc()
234 		while ((uart_getreg(bas, UART_DM_ISR) & UART_DM_TX_READY) == 0  in msm_putc()
237 		SETREG(bas, UART_DM_CR, UART_DM_CLEAR_TX_READY);  in msm_putc()
240 	uart_setreg(bas, UART_DM_NO_CHARS_FOR_TX, 1);  in msm_putc()
243 	while ((uart_getreg(bas, UART_DM_SR) & UART_DM_SR_TXRDY) == 0)  in msm_putc()
247 	SETREG(bas, UART_DM_TF(0), (c & 0xff));  in msm_putc()
251 msm_rxready(struct uart_bas *bas)  in msm_rxready()  argument
255 	return ((uart_getreg(bas, UART_DM_SR) & UART_DM_SR_RXRDY) ==  in msm_rxready()
260 msm_getc(struct uart_bas *bas, struct mtx *mtx)  in msm_getc()  argument
267 	while ((uart_getreg(bas, UART_DM_SR) & UART_DM_SR_RXRDY) !=  in msm_getc()
272 	if (uart_getreg(bas, UART_DM_SR) & UART_DM_SR_UART_OVERRUN)  in msm_getc()
273 		uart_setreg(bas, UART_DM_CR, UART_DM_RESET_ERROR_STATUS);  in msm_getc()
276 	c = uart_getreg(bas, UART_DM_RF(0));  in msm_getc()
323 	struct uart_bas *bas;  in msm_bus_probe()  local
325 	bas = &sc->sc_bas;  in msm_bus_probe()
326 	bas->regiowidth = 4;  in msm_bus_probe()
340 	struct uart_bas *bas = &sc->sc_bas;  in msm_bus_attach()  local
349 	uart_setreg(bas, UART_DM_IMR, u->ier);  in msm_bus_attach()
361 	struct uart_bas *bas = &sc->sc_bas;  in msm_bus_transmit()  local
369 		msm_putc(bas, sc->sc_txbuf[i]);  in msm_bus_transmit()
370 		uart_barrier(bas);  in msm_bus_transmit()
375 	SETREG(bas, UART_DM_IMR, u->ier);  in msm_bus_transmit()
376 	uart_barrier(bas);  in msm_bus_transmit()
399 	struct uart_bas *bas;  in msm_bus_receive()  local
402 	bas = &sc->sc_bas;  in msm_bus_receive()
406 	SETREG(bas, UART_DM_CR, UART_DM_RESET_STALE_INT);  in msm_bus_receive()
407 	SETREG(bas, UART_DM_CR, UART_DM_STALE_EVENT_ENABLE);  in msm_bus_receive()
409 	SETREG(bas, UART_DM_IMR, u->ier);  in msm_bus_receive()
412 	while (uart_getreg(bas, UART_DM_SR) & UART_DM_SR_RXRDY) {  in msm_bus_receive()
420 		c = uart_getreg(bas, UART_DM_RF(0));  in msm_bus_receive()
421 		uart_barrier(bas);  in msm_bus_receive()
454 	struct uart_bas *bas = &sc->sc_bas;  in msm_bus_ipend()  local
461 	isr = GETREG(bas, UART_DM_MISR);  in msm_bus_ipend()
468 		SETREG(bas, UART_DM_IMR, u->ier);  in msm_bus_ipend()
469 		uart_barrier(bas);  in msm_bus_ipend()
476 		SETREG(bas, UART_DM_CR, UART_DM_STALE_EVENT_DISABLE);  in msm_bus_ipend()
477 		SETREG(bas, UART_DM_CR, UART_DM_RESET_STALE_INT);  in msm_bus_ipend()
478 		uart_barrier(bas);  in msm_bus_ipend()
485 		SETREG(bas, UART_DM_CR, UART_DM_CLEAR_TX_READY);  in msm_bus_ipend()
489 		SETREG(bas, UART_DM_IMR, u->ier);  in msm_bus_ipend()
490 		uart_barrier(bas);  in msm_bus_ipend()
499 		SETREG(bas, UART_DM_IMR, u->ier);  in msm_bus_ipend()
500 		uart_barrier(bas);  in msm_bus_ipend()
534 	struct uart_bas *bas = &sc->sc_bas;  in msm_bus_grab()  local
541 	SETREG(bas, UART_DM_CR, UART_DM_RESET_STALE_INT);  in msm_bus_grab()
542 	SETREG(bas, UART_DM_IMR, 0);  in msm_bus_grab()
543 	uart_barrier(bas);  in msm_bus_grab()
551 	struct uart_bas *bas = &sc->sc_bas;  in msm_bus_ungrab()  local
557 	SETREG(bas, UART_DM_IMR, u->ier);  in msm_bus_ungrab()
558 	uart_barrier(bas);  in msm_bus_ungrab()