Lines Matching +full:disable +full:- +full:eop
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2001-2024, Intel Corporation
6 * Copyright (c) 2021-2024 Rubicon Communications, LLC (Netgate)
50 /* Intel(R) PRO/1000 Network Connection - igc */
52 "Intel(R) Ethernet Controller I225-LM"),
54 "Intel(R) Ethernet Controller I225-V"),
56 "Intel(R) Ethernet Controller I225-K"),
58 "Intel(R) Ethernet Controller I225-IT"),
60 "Intel(R) Ethernet Controller I220-V"),
62 "Intel(R) Ethernet Controller I225-K(2)"),
64 "Intel(R) Ethernet Controller I225-LMvP(2)"),
66 "Intel(R) Ethernet Controller I226-K"),
68 "Intel(R) Ethernet Controller I226-LMvP"),
70 "Intel(R) Ethernet Controller I225-IT(2)"),
72 "Intel(R) Ethernet Controller I226-LM"),
74 "Intel(R) Ethernet Controller I226-V"),
76 "Intel(R) Ethernet Controller I226-IT"),
78 "Intel(R) Ethernet Controller I221-V"),
156 /* MSI-X handlers */
246 &igc_disable_crc_stripping, 0, "Disable CRC Stripping");
258 /* Energy efficient ethernet - default to OFF */
319 struct igc_hw *hw = &sc->hw; in igc_get_regs()
395 if_softc_ctx_t scctx = sc->shared; in igc_get_regs()
396 struct rx_ring *rxr = &rx_que->rxr; in igc_get_regs()
397 struct tx_ring *txr = &tx_que->txr; in igc_get_regs()
398 int ntxd = scctx->isc_ntxd[0]; in igc_get_regs()
399 int nrxd = scctx->isc_nrxd[0]; in igc_get_regs()
403 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); in igc_get_regs()
404 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); in igc_get_regs()
407 j, rxr->rx_base[j].read.buffer_addr, staterr, length); in igc_get_regs()
411 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; in igc_get_regs()
414 "[3]: %08x eop: %d DD=%d\n", in igc_get_regs()
415 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, in igc_get_regs()
416 buf->eop != -1 ? in igc_get_regs()
417 txr->tx_base[buf->eop].upper.fields.status & in igc_get_regs()
472 sc->ctx = sc->osdep.ctx = ctx; in igc_if_attach_pre()
473 sc->dev = sc->osdep.dev = dev; in igc_if_attach_pre()
474 scctx = sc->shared = iflib_get_softc_ctx(ctx); in igc_if_attach_pre()
475 sc->media = iflib_get_media(ctx); in igc_if_attach_pre()
476 hw = &sc->hw; in igc_if_attach_pre()
484 sc->enable_aim = igc_enable_aim; in igc_if_attach_pre()
488 &sc->enable_aim, 0, in igc_if_attach_pre()
549 scctx->isc_tx_nsegments = IGC_MAX_SCATTER; in igc_if_attach_pre()
550 scctx->isc_nrxqsets_max = in igc_if_attach_pre()
551 scctx->isc_ntxqsets_max = igc_set_num_queues(ctx); in igc_if_attach_pre()
554 scctx->isc_ntxqsets_max); in igc_if_attach_pre()
556 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * in igc_if_attach_pre()
558 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * in igc_if_attach_pre()
560 scctx->isc_txd_size[0] = sizeof(union igc_adv_tx_desc); in igc_if_attach_pre()
561 scctx->isc_rxd_size[0] = sizeof(union igc_adv_rx_desc); in igc_if_attach_pre()
562 scctx->isc_txrx = &igc_txrx; in igc_if_attach_pre()
563 scctx->isc_tx_tso_segments_max = IGC_MAX_SCATTER; in igc_if_attach_pre()
564 scctx->isc_tx_tso_size_max = IGC_TSO_SIZE; in igc_if_attach_pre()
565 scctx->isc_tx_tso_segsize_max = IGC_TSO_SEG_SIZE; in igc_if_attach_pre()
566 scctx->isc_capabilities = scctx->isc_capenable = IGC_CAPS; in igc_if_attach_pre()
567 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | in igc_if_attach_pre()
575 scctx->isc_msix_bar = PCIR_BAR(IGC_MSIX_BAR); in igc_if_attach_pre()
576 if (pci_read_config(dev, scctx->isc_msix_bar, 4) == 0) in igc_if_attach_pre()
577 scctx->isc_msix_bar += 4; in igc_if_attach_pre()
598 hw->mac.autoneg = DO_AUTO_NEG; in igc_if_attach_pre()
599 hw->phy.autoneg_wait_to_complete = false; in igc_if_attach_pre()
600 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; in igc_if_attach_pre()
603 if (hw->phy.media_type == igc_media_type_copper) { in igc_if_attach_pre()
604 hw->phy.mdix = AUTO_ALL_MODES; in igc_if_attach_pre()
611 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size = in igc_if_attach_pre()
615 sc->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * in igc_if_attach_pre()
617 if (sc->mta == NULL) { in igc_if_attach_pre()
630 sc->hw.dev_spec._i225.eee_disable = igc_eee_setting; in igc_if_attach_pre()
636 "Disable Energy Efficient Ethernet"); in igc_if_attach_pre()
648 ** Some PCI-E parts fail the first check due to in igc_if_attach_pre()
668 if (!igc_is_valid_ether_addr(hw->mac.addr)) { in igc_if_attach_pre()
680 * Get Wake-on-Lan and Management info for later use in igc_if_attach_pre()
685 scctx->isc_capenable &= ~IFCAP_WOL; in igc_if_attach_pre()
686 if (sc->wol != 0) in igc_if_attach_pre()
687 scctx->isc_capenable |= IFCAP_WOL_MAGIC; in igc_if_attach_pre()
689 iflib_set_mac(ctx, hw->mac.addr); in igc_if_attach_pre()
697 free(sc->mta, M_DEVBUF); in igc_if_attach_pre()
706 struct igc_hw *hw = &sc->hw; in igc_if_attach_post()
719 hw->mac.get_link_status = true; in igc_if_attach_post()
734 free(sc->mta, M_DEVBUF); in igc_if_attach_post()
755 igc_phy_hw_reset(&sc->hw); in igc_if_detach()
808 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { in igc_if_mtu_set()
812 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size = in igc_if_mtu_set()
830 if_softc_ctx_t scctx = sc->shared; in igc_if_init()
838 bcopy(if_getlladdr(ifp), sc->hw.mac.addr, in igc_if_init()
842 igc_rar_set(&sc->hw, sc->hw.mac.addr, 0); in igc_if_init()
848 for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues; in igc_if_init()
850 struct tx_ring *txr = &tx_que->txr; in igc_if_init()
852 txr->tx_rs_cidx = txr->tx_rs_pidx; in igc_if_init()
856 * off-by-one error when calculating how many descriptors are in igc_if_init()
859 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; in igc_if_init()
863 IGC_WRITE_REG(&sc->hw, IGC_VET, ETHERTYPE_VLAN); in igc_if_init()
871 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); in igc_if_init()
879 igc_clear_hw_cntrs_base_generic(&sc->hw); in igc_if_init()
881 if (sc->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ in igc_if_init()
885 IGC_READ_REG(&sc->hw, IGC_ICR); in igc_if_init()
886 IGC_WRITE_REG(&sc->hw, IGC_ICS, IGC_ICS_LSC); in igc_if_init()
892 igc_set_eee_i225(&sc->hw, true, true, true); in igc_if_init()
910 struct igc_hw *hw = &sc->hw; in igc_neweitr()
916 rxbytes = atomic_load_long(&rxr->rx_bytes); in igc_neweitr()
917 txbytes = atomic_load_long(&txr->tx_bytes); in igc_neweitr()
925 if (sc->enable_aim) { in igc_neweitr()
926 nextlatency = rxr->rx_nextlatency; in igc_neweitr()
928 /* Use half default (4K) ITR if sub-gig */ in igc_neweitr()
929 if (sc->link_speed < 1000) { in igc_neweitr()
934 if (sc->shared->isc_max_frame_size * 2 > (sc->pba << 10)) { in igc_neweitr()
936 sc->enable_aim = 0; in igc_neweitr()
942 txpackets = atomic_load_long(&txr->tx_packets); in igc_neweitr()
948 rxpackets = atomic_load_long(&rxr->rx_packets); in igc_neweitr()
993 device_printf(sc->dev, in igc_neweitr()
1000 if (sc->enable_aim == 1 && nextlatency == eitr_latency_lowest) in igc_neweitr()
1004 rxr->rx_nextlatency = nextlatency; in igc_neweitr()
1008 rxr->rx_nextlatency = nextlatency; in igc_neweitr()
1033 if (neweitr != que->eitr_setting) { in igc_neweitr()
1034 que->eitr_setting = neweitr; in igc_neweitr()
1035 IGC_WRITE_REG(hw, IGC_EITR(que->msix), que->eitr_setting); in igc_neweitr()
1048 struct igc_hw *hw = &sc->hw; in igc_intr()
1049 struct igc_rx_queue *que = &sc->rx_queues[0]; in igc_intr()
1050 struct tx_ring *txr = &sc->tx_queues[0].txr; in igc_intr()
1051 struct rx_ring *rxr = &que->rxr; in igc_intr()
1052 if_ctx_t ctx = sc->ctx; in igc_intr()
1069 * Only MSI-X interrupts have one-shot behavior by taking advantage in igc_intr()
1070 * of the EIAC register. Thus, explicitly disable interrupts. This in igc_intr()
1081 sc->rx_overruns++; in igc_intr()
1086 txr->tx_bytes = 0; in igc_intr()
1087 txr->tx_packets = 0; in igc_intr()
1088 rxr->rx_bytes = 0; in igc_intr()
1089 rxr->rx_packets = 0; in igc_intr()
1098 struct igc_rx_queue *rxq = &sc->rx_queues[rxqid]; in igc_if_rx_queue_intr_enable()
1100 IGC_WRITE_REG(&sc->hw, IGC_EIMS, rxq->eims); in igc_if_rx_queue_intr_enable()
1108 struct igc_tx_queue *txq = &sc->tx_queues[txqid]; in igc_if_tx_queue_intr_enable()
1110 IGC_WRITE_REG(&sc->hw, IGC_EIMS, txq->eims); in igc_if_tx_queue_intr_enable()
1116 * MSI-X RX Interrupt Service routine
1123 struct igc_softc *sc = que->sc; in igc_msix_que()
1124 struct tx_ring *txr = &sc->tx_queues[que->msix].txr; in igc_msix_que()
1125 struct rx_ring *rxr = &que->rxr; in igc_msix_que()
1127 ++que->irqs; in igc_msix_que()
1132 txr->tx_bytes = 0; in igc_msix_que()
1133 txr->tx_packets = 0; in igc_msix_que()
1134 rxr->rx_bytes = 0; in igc_msix_que()
1135 rxr->rx_packets = 0; in igc_msix_que()
1142 * MSI-X Link Fast Interrupt Service routine
1151 ++sc->link_irq; in igc_msix_link()
1152 MPASS(sc->hw.back != NULL); in igc_msix_link()
1153 reg_icr = IGC_READ_REG(&sc->hw, IGC_ICR); in igc_msix_link()
1156 sc->rx_overruns++; in igc_msix_link()
1159 igc_handle_link(sc->ctx); in igc_msix_link()
1162 IGC_WRITE_REG(&sc->hw, IGC_IMS, IGC_IMS_LSC); in igc_msix_link()
1163 IGC_WRITE_REG(&sc->hw, IGC_EIMS, sc->link_mask); in igc_msix_link()
1174 sc->hw.mac.get_link_status = true; in igc_handle_link()
1195 ifmr->ifm_status = IFM_AVALID; in igc_if_media_status()
1196 ifmr->ifm_active = IFM_ETHER; in igc_if_media_status()
1198 if (!sc->link_active) { in igc_if_media_status()
1202 ifmr->ifm_status |= IFM_ACTIVE; in igc_if_media_status()
1204 switch (sc->link_speed) { in igc_if_media_status()
1206 ifmr->ifm_active |= IFM_10_T; in igc_if_media_status()
1209 ifmr->ifm_active |= IFM_100_TX; in igc_if_media_status()
1212 ifmr->ifm_active |= IFM_1000_T; in igc_if_media_status()
1215 ifmr->ifm_active |= IFM_2500_T; in igc_if_media_status()
1219 if (sc->link_duplex == FULL_DUPLEX) in igc_if_media_status()
1220 ifmr->ifm_active |= IFM_FDX; in igc_if_media_status()
1222 ifmr->ifm_active |= IFM_HDX; in igc_if_media_status()
1241 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) in igc_if_media_change()
1244 sc->hw.mac.autoneg = DO_AUTO_NEG; in igc_if_media_change()
1246 switch (IFM_SUBTYPE(ifm->ifm_media)) { in igc_if_media_change()
1248 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; in igc_if_media_change()
1251 sc->hw.phy.autoneg_advertised = ADVERTISE_2500_FULL; in igc_if_media_change()
1254 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; in igc_if_media_change()
1257 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) in igc_if_media_change()
1258 sc->hw.phy.autoneg_advertised = ADVERTISE_100_FULL; in igc_if_media_change()
1260 sc->hw.phy.autoneg_advertised = ADVERTISE_100_HALF; in igc_if_media_change()
1263 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) in igc_if_media_change()
1264 sc->hw.phy.autoneg_advertised = ADVERTISE_10_FULL; in igc_if_media_change()
1266 sc->hw.phy.autoneg_advertised = ADVERTISE_10_HALF; in igc_if_media_change()
1269 device_printf(sc->dev, "Unsupported media type\n"); in igc_if_media_change()
1285 reg_rctl = IGC_READ_REG(&sc->hw, IGC_RCTL); in igc_if_set_promisc()
1292 /* Don't disable if in MAX groups */ in igc_if_set_promisc()
1295 IGC_WRITE_REG(&sc->hw, IGC_RCTL, reg_rctl); in igc_if_set_promisc()
1302 IGC_WRITE_REG(&sc->hw, IGC_RCTL, reg_rctl); in igc_if_set_promisc()
1306 IGC_WRITE_REG(&sc->hw, IGC_RCTL, reg_rctl); in igc_if_set_promisc()
1342 mta = sc->mta; in igc_if_multi_set()
1347 reg_rctl = IGC_READ_REG(&sc->hw, IGC_RCTL); in igc_if_multi_set()
1362 igc_update_mc_addr_list(&sc->hw, mta, mcnt); in igc_if_multi_set()
1364 IGC_WRITE_REG(&sc->hw, IGC_RCTL, reg_rctl); in igc_if_multi_set()
1372 * controller-specific hardware patting.
1389 struct igc_hw *hw = &sc->hw; in igc_if_update_admin_status()
1395 switch (hw->phy.media_type) { in igc_if_update_admin_status()
1397 if (hw->mac.get_link_status == true) { in igc_if_update_admin_status()
1400 link_check = !hw->mac.get_link_status; in igc_if_update_admin_status()
1406 link_check = !hw->mac.get_link_status; in igc_if_update_admin_status()
1413 if (link_check && (sc->link_active == 0)) { in igc_if_update_admin_status()
1414 igc_get_speed_and_duplex(hw, &sc->link_speed, in igc_if_update_admin_status()
1415 &sc->link_duplex); in igc_if_update_admin_status()
1418 sc->link_speed, in igc_if_update_admin_status()
1419 ((sc->link_duplex == FULL_DUPLEX) ? in igc_if_update_admin_status()
1421 sc->link_active = 1; in igc_if_update_admin_status()
1423 IF_Mbps(sc->link_speed)); in igc_if_update_admin_status()
1424 } else if (!link_check && (sc->link_active == 1)) { in igc_if_update_admin_status()
1425 sc->link_speed = 0; in igc_if_update_admin_status()
1426 sc->link_duplex = 0; in igc_if_update_admin_status()
1427 sc->link_active = 0; in igc_if_update_admin_status()
1442 sc->watchdog_events++; in igc_if_watchdog_reset()
1458 igc_reset_hw(&sc->hw); in igc_if_stop()
1459 IGC_WRITE_REG(&sc->hw, IGC_WUC, 0); in igc_if_stop()
1474 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); in igc_identify_hardware()
1477 sc->hw.vendor_id = pci_get_vendor(dev); in igc_identify_hardware()
1478 sc->hw.device_id = pci_get_device(dev); in igc_identify_hardware()
1479 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); in igc_identify_hardware()
1480 sc->hw.subsystem_vendor_id = in igc_identify_hardware()
1482 sc->hw.subsystem_device_id = in igc_identify_hardware()
1486 if (igc_set_mac_type(&sc->hw)) { in igc_identify_hardware()
1500 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, in igc_allocate_pci_resources()
1502 if (sc->memory == NULL) { in igc_allocate_pci_resources()
1507 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory); in igc_allocate_pci_resources()
1508 sc->osdep.mem_bus_space_handle = in igc_allocate_pci_resources()
1509 rman_get_bushandle(sc->memory); in igc_allocate_pci_resources()
1510 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle; in igc_allocate_pci_resources()
1512 sc->hw.back = &sc->osdep; in igc_allocate_pci_resources()
1519 * Set up the MSI-X Interrupt handlers
1526 struct igc_rx_queue *rx_que = sc->rx_queues; in igc_if_msix_intr_assign()
1527 struct igc_tx_queue *tx_que = sc->tx_queues; in igc_if_msix_intr_assign()
1532 for (i = 0; i < sc->rx_num_queues; i++, rx_que++, vector++) { in igc_if_msix_intr_assign()
1535 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, in igc_if_msix_intr_assign()
1536 IFLIB_INTR_RXTX, igc_msix_que, rx_que, rx_que->me, buf); in igc_if_msix_intr_assign()
1541 sc->rx_num_queues = i + 1; in igc_if_msix_intr_assign()
1545 rx_que->msix = vector; in igc_if_msix_intr_assign()
1549 * in IGC_IMS -- bits 20 and 21 in igc_if_msix_intr_assign()
1551 * NOTHING to do with the MSI-X vector in igc_if_msix_intr_assign()
1553 rx_que->eims = 1 << vector; in igc_if_msix_intr_assign()
1558 for (i = 0; i < sc->tx_num_queues; i++, tx_que++, vector++) { in igc_if_msix_intr_assign()
1560 tx_que = &sc->tx_queues[i]; in igc_if_msix_intr_assign()
1562 &sc->rx_queues[i % sc->rx_num_queues].que_irq, in igc_if_msix_intr_assign()
1563 IFLIB_INTR_TX, tx_que, tx_que->me, buf); in igc_if_msix_intr_assign()
1565 tx_que->msix = (vector % sc->rx_num_queues); in igc_if_msix_intr_assign()
1569 * in IGC_IMS -- bits 22 and 23 in igc_if_msix_intr_assign()
1571 * NOTHING to do with the MSI-X vector in igc_if_msix_intr_assign()
1573 tx_que->eims = 1 << i; in igc_if_msix_intr_assign()
1578 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, IFLIB_INTR_ADMIN, in igc_if_msix_intr_assign()
1586 sc->linkvec = rx_vectors; in igc_if_msix_intr_assign()
1589 iflib_irq_free(ctx, &sc->irq); in igc_if_msix_intr_assign()
1590 rx_que = sc->rx_queues; in igc_if_msix_intr_assign()
1591 for (int i = 0; i < sc->rx_num_queues; i++, rx_que++) in igc_if_msix_intr_assign()
1592 iflib_irq_free(ctx, &rx_que->que_irq); in igc_if_msix_intr_assign()
1599 struct igc_hw *hw = &sc->hw; in igc_configure_queues()
1609 /* Turn on MSI-X */ in igc_configure_queues()
1611 for (int i = 0; i < sc->rx_num_queues; i++) { in igc_configure_queues()
1614 rx_que = &sc->rx_queues[i]; in igc_configure_queues()
1617 ivar |= (rx_que->msix | IGC_IVAR_VALID) << 16; in igc_configure_queues()
1620 ivar |= rx_que->msix | IGC_IVAR_VALID; in igc_configure_queues()
1625 for (int i = 0; i < sc->tx_num_queues; i++) { in igc_configure_queues()
1628 tx_que = &sc->tx_queues[i]; in igc_configure_queues()
1631 ivar |= (tx_que->msix | IGC_IVAR_VALID) << 24; in igc_configure_queues()
1634 ivar |= (tx_que->msix | IGC_IVAR_VALID) << 8; in igc_configure_queues()
1637 sc->que_mask |= tx_que->eims; in igc_configure_queues()
1641 ivar = (sc->linkvec | IGC_IVAR_VALID) << 8; in igc_configure_queues()
1642 sc->link_mask = 1 << sc->linkvec; in igc_configure_queues()
1651 for (int i = 0; i < sc->rx_num_queues; i++) { in igc_configure_queues()
1652 rx_que = &sc->rx_queues[i]; in igc_configure_queues()
1653 IGC_WRITE_REG(hw, IGC_EITR(rx_que->msix), newitr); in igc_configure_queues()
1663 struct igc_rx_queue *que = sc->rx_queues; in igc_free_pci_resources()
1666 /* Release all MSI-X queue resources */ in igc_free_pci_resources()
1667 if (sc->intr_type == IFLIB_INTR_MSIX) in igc_free_pci_resources()
1668 iflib_irq_free(ctx, &sc->irq); in igc_free_pci_resources()
1670 for (int i = 0; i < sc->rx_num_queues; i++, que++) { in igc_free_pci_resources()
1671 iflib_irq_free(ctx, &que->que_irq); in igc_free_pci_resources()
1674 if (sc->memory != NULL) { in igc_free_pci_resources()
1676 rman_get_rid(sc->memory), sc->memory); in igc_free_pci_resources()
1677 sc->memory = NULL; in igc_free_pci_resources()
1680 if (sc->flash != NULL) { in igc_free_pci_resources()
1682 rman_get_rid(sc->flash), sc->flash); in igc_free_pci_resources()
1683 sc->flash = NULL; in igc_free_pci_resources()
1686 if (sc->ioport != NULL) { in igc_free_pci_resources()
1688 rman_get_rid(sc->ioport), sc->ioport); in igc_free_pci_resources()
1689 sc->ioport = NULL; in igc_free_pci_resources()
1693 /* Set up MSI or MSI-X */
1708 device_t dev = sc->dev; in igc_init_dmac()
1709 struct igc_hw *hw = &sc->hw; in igc_init_dmac()
1715 max_frame_size = sc->shared->isc_max_frame_size; in igc_init_dmac()
1717 if (sc->dmac == 0) { /* Disabling it */ in igc_init_dmac()
1726 hwm = 64 * pba - max_frame_size / 16; in igc_init_dmac()
1727 if (hwm < 64 * (pba - 6)) in igc_init_dmac()
1728 hwm = 64 * (pba - 6); in igc_init_dmac()
1735 dmac = pba - max_frame_size / 512; in igc_init_dmac()
1736 if (dmac < pba - 10) in igc_init_dmac()
1737 dmac = pba - 10; in igc_init_dmac()
1755 reg |= ((sc->dmac * 5) >> 6); in igc_init_dmac()
1757 reg |= (sc->dmac >> 5); in igc_init_dmac()
1781 IGC_WRITE_REG(hw, IGC_DMCTXTH, (IGC_TXPBSIZE - in igc_init_dmac()
1801 struct igc_hw *hw = &sc->hw; in igc_reset()
1821 * - High water mark should allow for at least two frames to be in igc_reset()
1823 * - Low water mark works best when it is very near the high water in igc_reset()
1831 * - The pause time is fairly large at 1000 x 512ns = 512 usec. in igc_reset()
1834 hw->fc.high_water = rx_buffer_size - in igc_reset()
1835 roundup2(sc->hw.mac.max_frame_size, 1024); in igc_reset()
1836 /* 16-byte granularity */ in igc_reset()
1837 hw->fc.low_water = hw->fc.high_water - 16; in igc_reset()
1839 if (sc->fc) /* locally set flow control value? */ in igc_reset()
1840 hw->fc.requested_mode = sc->fc; in igc_reset()
1842 hw->fc.requested_mode = igc_fc_full; in igc_reset()
1844 hw->fc.pause_time = IGC_FC_PAUSE_TIME; in igc_reset()
1846 hw->fc.send_xon = true; in igc_reset()
1852 /* and a re-init */ in igc_reset()
1862 sc->pba = pba; in igc_reset()
1878 struct igc_hw *hw = &sc->hw; in igc_initialize_rss_mapping()
1890 * This just allocates buckets to queues using round-robin in igc_initialize_rss_mapping()
1915 queue_id = queue_id % sc->rx_num_queues; in igc_initialize_rss_mapping()
1917 queue_id = (i % sc->rx_num_queues); in igc_initialize_rss_mapping()
1972 if_softc_ctx_t scctx = sc->shared; in igc_setup_interface()
1977 if (sc->tx_num_queues == 1) { in igc_setup_interface()
1978 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); in igc_setup_interface()
1986 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL); in igc_setup_interface()
1987 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); in igc_setup_interface()
1988 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); in igc_setup_interface()
1989 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); in igc_setup_interface()
1990 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); in igc_setup_interface()
1991 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); in igc_setup_interface()
1992 ifmedia_add(sc->media, IFM_ETHER | IFM_2500_T, 0, NULL); in igc_setup_interface()
1994 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); in igc_setup_interface()
1995 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO); in igc_setup_interface()
2004 if_softc_ctx_t scctx = sc->shared; in igc_if_tx_queues_alloc()
2009 MPASS(sc->tx_num_queues > 0); in igc_if_tx_queues_alloc()
2010 MPASS(sc->tx_num_queues == ntxqsets); in igc_if_tx_queues_alloc()
2013 if (!(sc->tx_queues = in igc_if_tx_queues_alloc()
2015 sc->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { in igc_if_tx_queues_alloc()
2021 for (i = 0, que = sc->tx_queues; i < sc->tx_num_queues; i++, que++) { in igc_if_tx_queues_alloc()
2024 struct tx_ring *txr = &que->txr; in igc_if_tx_queues_alloc()
2025 txr->sc = que->sc = sc; in igc_if_tx_queues_alloc()
2026 que->me = txr->me = i; in igc_if_tx_queues_alloc()
2029 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * in igc_if_tx_queues_alloc()
2030 scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { in igc_if_tx_queues_alloc()
2036 for (j = 0; j < scctx->isc_ntxd[0]; j++) in igc_if_tx_queues_alloc()
2037 txr->tx_rsq[j] = QIDX_INVALID; in igc_if_tx_queues_alloc()
2039 txr->tx_base = (struct igc_tx_desc *)vaddrs[i*ntxqs]; in igc_if_tx_queues_alloc()
2040 txr->tx_paddr = paddrs[i*ntxqs]; in igc_if_tx_queues_alloc()
2045 "allocated for %d tx_queues\n", sc->tx_num_queues); in igc_if_tx_queues_alloc()
2061 MPASS(sc->rx_num_queues > 0); in igc_if_rx_queues_alloc()
2062 MPASS(sc->rx_num_queues == nrxqsets); in igc_if_rx_queues_alloc()
2065 if (!(sc->rx_queues = in igc_if_rx_queues_alloc()
2067 sc->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { in igc_if_rx_queues_alloc()
2074 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) { in igc_if_rx_queues_alloc()
2076 struct rx_ring *rxr = &que->rxr; in igc_if_rx_queues_alloc()
2077 rxr->sc = que->sc = sc; in igc_if_rx_queues_alloc()
2078 rxr->que = que; in igc_if_rx_queues_alloc()
2079 que->me = rxr->me = i; in igc_if_rx_queues_alloc()
2082 rxr->rx_base = (union igc_rx_desc_extended *)vaddrs[i*nrxqs]; in igc_if_rx_queues_alloc()
2083 rxr->rx_paddr = paddrs[i*nrxqs]; in igc_if_rx_queues_alloc()
2088 "allocated for %d rx_queues\n", sc->rx_num_queues); in igc_if_rx_queues_alloc()
2100 struct igc_tx_queue *tx_que = sc->tx_queues; in igc_if_queues_free()
2101 struct igc_rx_queue *rx_que = sc->rx_queues; in igc_if_queues_free()
2104 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { in igc_if_queues_free()
2105 struct tx_ring *txr = &tx_que->txr; in igc_if_queues_free()
2106 if (txr->tx_rsq == NULL) in igc_if_queues_free()
2109 free(txr->tx_rsq, M_DEVBUF); in igc_if_queues_free()
2110 txr->tx_rsq = NULL; in igc_if_queues_free()
2112 free(sc->tx_queues, M_DEVBUF); in igc_if_queues_free()
2113 sc->tx_queues = NULL; in igc_if_queues_free()
2117 free(sc->rx_queues, M_DEVBUF); in igc_if_queues_free()
2118 sc->rx_queues = NULL; in igc_if_queues_free()
2121 if (sc->mta != NULL) { in igc_if_queues_free()
2122 free(sc->mta, M_DEVBUF); in igc_if_queues_free()
2135 if_softc_ctx_t scctx = sc->shared; in igc_initialize_transmit_unit()
2138 struct igc_hw *hw = &sc->hw; in igc_initialize_transmit_unit()
2143 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { in igc_initialize_transmit_unit()
2147 que = &sc->tx_queues[i]; in igc_initialize_transmit_unit()
2148 txr = &que->txr; in igc_initialize_transmit_unit()
2149 bus_addr = txr->tx_paddr; in igc_initialize_transmit_unit()
2152 offp = (caddr_t)&txr->csum_flags; in igc_initialize_transmit_unit()
2154 bzero(offp, endp - offp); in igc_initialize_transmit_unit()
2158 scctx->isc_ntxd[0] * sizeof(struct igc_tx_desc)); in igc_initialize_transmit_unit()
2168 IGC_READ_REG(&sc->hw, IGC_TDBAL(i)), in igc_initialize_transmit_unit()
2169 IGC_READ_REG(&sc->hw, IGC_TDLEN(i))); in igc_initialize_transmit_unit()
2183 tctl = IGC_READ_REG(&sc->hw, IGC_TCTL); in igc_initialize_transmit_unit()
2189 IGC_WRITE_REG(&sc->hw, IGC_TCTL, tctl); in igc_initialize_transmit_unit()
2197 #define BSIZEPKT_ROUNDUP ((1<<IGC_SRRCTL_BSIZEPKT_SHIFT)-1)
2203 if_softc_ctx_t scctx = sc->shared; in igc_initialize_receive_unit()
2205 struct igc_hw *hw = &sc->hw; in igc_initialize_receive_unit()
2223 (hw->mac.mc_filter_type << IGC_RCTL_MO_SHIFT); in igc_initialize_receive_unit()
2241 if (sc->tx_num_queues > 1) in igc_initialize_receive_unit()
2246 if (sc->tx_num_queues > 1) in igc_initialize_receive_unit()
2253 if (sc->rx_num_queues > 1) in igc_initialize_receive_unit()
2257 psize = scctx->isc_max_frame_size; in igc_initialize_receive_unit()
2261 IGC_WRITE_REG(&sc->hw, IGC_RLPML, psize); in igc_initialize_receive_unit()
2265 srrctl |= (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> in igc_initialize_receive_unit()
2276 if ((sc->rx_num_queues > 1) && in igc_initialize_receive_unit()
2277 (sc->fc == igc_fc_none || in igc_initialize_receive_unit()
2278 sc->fc == igc_fc_rx_pause)) { in igc_initialize_receive_unit()
2283 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { in igc_initialize_receive_unit()
2284 struct rx_ring *rxr = &que->rxr; in igc_initialize_receive_unit()
2285 u64 bus_addr = rxr->rx_paddr; in igc_initialize_receive_unit()
2289 /* Configure for header split? -- ignore for now */ in igc_initialize_receive_unit()
2290 rxr->hdr_split = igc_header_split; in igc_initialize_receive_unit()
2296 scctx->isc_nrxd[0] * sizeof(struct igc_rx_desc)); in igc_initialize_receive_unit()
2326 struct igc_hw *hw = &sc->hw; in igc_setup_vlan_hw_support()
2348 struct igc_hw *hw = &sc->hw; in igc_if_intr_enable()
2351 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { in igc_if_intr_enable()
2352 mask = (sc->que_mask | sc->link_mask); in igc_if_intr_enable()
2366 struct igc_hw *hw = &sc->hw; in igc_if_intr_disable()
2368 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { in igc_if_intr_disable()
2387 if (sc->vf_ifp) in igc_get_hw_control()
2390 ctrl_ext = IGC_READ_REG(&sc->hw, IGC_CTRL_EXT); in igc_get_hw_control()
2391 IGC_WRITE_REG(&sc->hw, IGC_CTRL_EXT, in igc_get_hw_control()
2406 ctrl_ext = IGC_READ_REG(&sc->hw, IGC_CTRL_EXT); in igc_release_hw_control()
2407 IGC_WRITE_REG(&sc->hw, IGC_CTRL_EXT, in igc_release_hw_control()
2426 ** to both system management and wake-on-lan for
2436 eeprom_data = IGC_READ_REG(&sc->hw, IGC_WUC); in igc_get_wakeup()
2439 sc->wol = IGC_WUFC_LNKC; in igc_get_wakeup()
2463 sc->wol &= ~IGC_WUFC_MAG; in igc_enable_wakeup()
2466 sc->wol &= ~IGC_WUFC_EX; in igc_enable_wakeup()
2469 sc->wol &= ~IGC_WUFC_MC; in igc_enable_wakeup()
2471 rctl = IGC_READ_REG(&sc->hw, IGC_RCTL); in igc_enable_wakeup()
2473 IGC_WRITE_REG(&sc->hw, IGC_RCTL, rctl); in igc_enable_wakeup()
2476 if (!(sc->wol & (IGC_WUFC_EX | IGC_WUFC_MAG | IGC_WUFC_MC))) in igc_enable_wakeup()
2480 ctrl = IGC_READ_REG(&sc->hw, IGC_CTRL); in igc_enable_wakeup()
2482 IGC_WRITE_REG(&sc->hw, IGC_CTRL, ctrl); in igc_enable_wakeup()
2485 IGC_WRITE_REG(&sc->hw, IGC_WUC, IGC_WUC_PME_EN); in igc_enable_wakeup()
2486 IGC_WRITE_REG(&sc->hw, IGC_WUFC, sc->wol); in igc_enable_wakeup()
2503 u64 prev_xoffrxc = sc->stats.xoffrxc; in igc_update_stats_counters()
2505 sc->stats.crcerrs += IGC_READ_REG(&sc->hw, IGC_CRCERRS); in igc_update_stats_counters()
2506 sc->stats.mpc += IGC_READ_REG(&sc->hw, IGC_MPC); in igc_update_stats_counters()
2507 sc->stats.scc += IGC_READ_REG(&sc->hw, IGC_SCC); in igc_update_stats_counters()
2508 sc->stats.ecol += IGC_READ_REG(&sc->hw, IGC_ECOL); in igc_update_stats_counters()
2510 sc->stats.mcc += IGC_READ_REG(&sc->hw, IGC_MCC); in igc_update_stats_counters()
2511 sc->stats.latecol += IGC_READ_REG(&sc->hw, IGC_LATECOL); in igc_update_stats_counters()
2512 sc->stats.colc += IGC_READ_REG(&sc->hw, IGC_COLC); in igc_update_stats_counters()
2513 sc->stats.colc += IGC_READ_REG(&sc->hw, IGC_RERC); in igc_update_stats_counters()
2514 sc->stats.dc += IGC_READ_REG(&sc->hw, IGC_DC); in igc_update_stats_counters()
2515 sc->stats.rlec += IGC_READ_REG(&sc->hw, IGC_RLEC); in igc_update_stats_counters()
2516 sc->stats.xonrxc += IGC_READ_REG(&sc->hw, IGC_XONRXC); in igc_update_stats_counters()
2517 sc->stats.xontxc += IGC_READ_REG(&sc->hw, IGC_XONTXC); in igc_update_stats_counters()
2518 sc->stats.xoffrxc += IGC_READ_REG(&sc->hw, IGC_XOFFRXC); in igc_update_stats_counters()
2523 if (sc->stats.xoffrxc != prev_xoffrxc) in igc_update_stats_counters()
2524 sc->shared->isc_pause_frames = 1; in igc_update_stats_counters()
2525 sc->stats.xofftxc += IGC_READ_REG(&sc->hw, IGC_XOFFTXC); in igc_update_stats_counters()
2526 sc->stats.fcruc += IGC_READ_REG(&sc->hw, IGC_FCRUC); in igc_update_stats_counters()
2527 sc->stats.prc64 += IGC_READ_REG(&sc->hw, IGC_PRC64); in igc_update_stats_counters()
2528 sc->stats.prc127 += IGC_READ_REG(&sc->hw, IGC_PRC127); in igc_update_stats_counters()
2529 sc->stats.prc255 += IGC_READ_REG(&sc->hw, IGC_PRC255); in igc_update_stats_counters()
2530 sc->stats.prc511 += IGC_READ_REG(&sc->hw, IGC_PRC511); in igc_update_stats_counters()
2531 sc->stats.prc1023 += IGC_READ_REG(&sc->hw, IGC_PRC1023); in igc_update_stats_counters()
2532 sc->stats.prc1522 += IGC_READ_REG(&sc->hw, IGC_PRC1522); in igc_update_stats_counters()
2533 sc->stats.tlpic += IGC_READ_REG(&sc->hw, IGC_TLPIC); in igc_update_stats_counters()
2534 sc->stats.rlpic += IGC_READ_REG(&sc->hw, IGC_RLPIC); in igc_update_stats_counters()
2535 sc->stats.gprc += IGC_READ_REG(&sc->hw, IGC_GPRC); in igc_update_stats_counters()
2536 sc->stats.bprc += IGC_READ_REG(&sc->hw, IGC_BPRC); in igc_update_stats_counters()
2537 sc->stats.mprc += IGC_READ_REG(&sc->hw, IGC_MPRC); in igc_update_stats_counters()
2538 sc->stats.gptc += IGC_READ_REG(&sc->hw, IGC_GPTC); in igc_update_stats_counters()
2540 /* For the 64-bit byte counters the low dword must be read first. */ in igc_update_stats_counters()
2543 sc->stats.gorc += IGC_READ_REG(&sc->hw, IGC_GORCL) + in igc_update_stats_counters()
2544 ((u64)IGC_READ_REG(&sc->hw, IGC_GORCH) << 32); in igc_update_stats_counters()
2545 sc->stats.gotc += IGC_READ_REG(&sc->hw, IGC_GOTCL) + in igc_update_stats_counters()
2546 ((u64)IGC_READ_REG(&sc->hw, IGC_GOTCH) << 32); in igc_update_stats_counters()
2548 sc->stats.rnbc += IGC_READ_REG(&sc->hw, IGC_RNBC); in igc_update_stats_counters()
2549 sc->stats.ruc += IGC_READ_REG(&sc->hw, IGC_RUC); in igc_update_stats_counters()
2550 sc->stats.rfc += IGC_READ_REG(&sc->hw, IGC_RFC); in igc_update_stats_counters()
2551 sc->stats.roc += IGC_READ_REG(&sc->hw, IGC_ROC); in igc_update_stats_counters()
2552 sc->stats.rjc += IGC_READ_REG(&sc->hw, IGC_RJC); in igc_update_stats_counters()
2554 sc->stats.mgprc += IGC_READ_REG(&sc->hw, IGC_MGTPRC); in igc_update_stats_counters()
2555 sc->stats.mgpdc += IGC_READ_REG(&sc->hw, IGC_MGTPDC); in igc_update_stats_counters()
2556 sc->stats.mgptc += IGC_READ_REG(&sc->hw, IGC_MGTPTC); in igc_update_stats_counters()
2558 sc->stats.tor += IGC_READ_REG(&sc->hw, IGC_TORH); in igc_update_stats_counters()
2559 sc->stats.tot += IGC_READ_REG(&sc->hw, IGC_TOTH); in igc_update_stats_counters()
2561 sc->stats.tpr += IGC_READ_REG(&sc->hw, IGC_TPR); in igc_update_stats_counters()
2562 sc->stats.tpt += IGC_READ_REG(&sc->hw, IGC_TPT); in igc_update_stats_counters()
2563 sc->stats.ptc64 += IGC_READ_REG(&sc->hw, IGC_PTC64); in igc_update_stats_counters()
2564 sc->stats.ptc127 += IGC_READ_REG(&sc->hw, IGC_PTC127); in igc_update_stats_counters()
2565 sc->stats.ptc255 += IGC_READ_REG(&sc->hw, IGC_PTC255); in igc_update_stats_counters()
2566 sc->stats.ptc511 += IGC_READ_REG(&sc->hw, IGC_PTC511); in igc_update_stats_counters()
2567 sc->stats.ptc1023 += IGC_READ_REG(&sc->hw, IGC_PTC1023); in igc_update_stats_counters()
2568 sc->stats.ptc1522 += IGC_READ_REG(&sc->hw, IGC_PTC1522); in igc_update_stats_counters()
2569 sc->stats.mptc += IGC_READ_REG(&sc->hw, IGC_MPTC); in igc_update_stats_counters()
2570 sc->stats.bptc += IGC_READ_REG(&sc->hw, IGC_BPTC); in igc_update_stats_counters()
2573 sc->stats.iac += IGC_READ_REG(&sc->hw, IGC_IAC); in igc_update_stats_counters()
2574 sc->stats.rxdmtc += IGC_READ_REG(&sc->hw, IGC_RXDMTC); in igc_update_stats_counters()
2576 sc->stats.algnerrc += IGC_READ_REG(&sc->hw, IGC_ALGNERRC); in igc_update_stats_counters()
2577 sc->stats.tncrs += IGC_READ_REG(&sc->hw, IGC_TNCRS); in igc_update_stats_counters()
2578 sc->stats.htdpmc += IGC_READ_REG(&sc->hw, IGC_HTDPMC); in igc_update_stats_counters()
2579 sc->stats.tsctc += IGC_READ_REG(&sc->hw, IGC_TSCTC); in igc_update_stats_counters()
2590 return (sc->stats.colc); in igc_if_get_counter()
2592 return (sc->dropped_pkts + sc->stats.rxerrc + in igc_if_get_counter()
2593 sc->stats.crcerrs + sc->stats.algnerrc + in igc_if_get_counter()
2594 sc->stats.ruc + sc->stats.roc + in igc_if_get_counter()
2595 sc->stats.mpc + sc->stats.htdpmc); in igc_if_get_counter()
2598 sc->stats.ecol + sc->stats.latecol + sc->watchdog_events); in igc_if_get_counter()
2604 /* igc_if_needs_restart - Tell iflib when the driver needs to be reinitialized
2622 /* Export a single 32-bit register via a read-only sysctl. */
2629 sc = oidp->oid_arg1; in igc_sysctl_reg_handler()
2630 val = IGC_READ_REG(&sc->hw, oidp->oid_arg2); in igc_sysctl_reg_handler()
2644 bool tx = oidp->oid_arg2; in igc_sysctl_interrupt_rate_handler()
2647 tque = oidp->oid_arg1; in igc_sysctl_interrupt_rate_handler()
2648 hw = &tque->sc->hw; in igc_sysctl_interrupt_rate_handler()
2649 reg = IGC_READ_REG(hw, IGC_EITR(tque->me)); in igc_sysctl_interrupt_rate_handler()
2651 rque = oidp->oid_arg1; in igc_sysctl_interrupt_rate_handler()
2652 hw = &rque->sc->hw; in igc_sysctl_interrupt_rate_handler()
2653 reg = IGC_READ_REG(hw, IGC_EITR(rque->msix)); in igc_sysctl_interrupt_rate_handler()
2663 if (error || !req->newptr) in igc_sysctl_interrupt_rate_handler()
2674 device_t dev = iflib_get_dev(sc->ctx); in igc_add_hw_stats()
2675 struct igc_tx_queue *tx_que = sc->tx_queues; in igc_add_hw_stats()
2676 struct igc_rx_queue *rx_que = sc->rx_queues; in igc_add_hw_stats()
2681 struct igc_hw_stats *stats = &sc->stats; in igc_add_hw_stats()
2691 CTLFLAG_RD, &sc->dropped_pkts, in igc_add_hw_stats()
2694 CTLFLAG_RD, &sc->link_irq, in igc_add_hw_stats()
2695 "Link MSI-X IRQ Handled"); in igc_add_hw_stats()
2697 CTLFLAG_RD, &sc->rx_overruns, in igc_add_hw_stats()
2700 CTLFLAG_RD, &sc->watchdog_events, in igc_add_hw_stats()
2711 CTLFLAG_RD, &sc->hw.fc.high_water, 0, in igc_add_hw_stats()
2714 CTLFLAG_RD, &sc->hw.fc.low_water, 0, in igc_add_hw_stats()
2717 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { in igc_add_hw_stats()
2718 struct tx_ring *txr = &tx_que->txr; in igc_add_hw_stats()
2730 IGC_TDH(txr->me), igc_sysctl_reg_handler, "IU", in igc_add_hw_stats()
2734 IGC_TDT(txr->me), igc_sysctl_reg_handler, "IU", in igc_add_hw_stats()
2737 CTLFLAG_RD, &txr->tx_irq, in igc_add_hw_stats()
2738 "Queue MSI-X Transmit Interrupts"); in igc_add_hw_stats()
2741 for (int j = 0; j < sc->rx_num_queues; j++, rx_que++) { in igc_add_hw_stats()
2742 struct rx_ring *rxr = &rx_que->rxr; in igc_add_hw_stats()
2754 IGC_RDH(rxr->me), igc_sysctl_reg_handler, "IU", in igc_add_hw_stats()
2758 IGC_RDT(rxr->me), igc_sysctl_reg_handler, "IU", in igc_add_hw_stats()
2761 CTLFLAG_RD, &rxr->rx_irq, in igc_add_hw_stats()
2762 "Queue MSI-X Receive Interrupts"); in igc_add_hw_stats()
2771 CTLFLAG_RD, &stats->ecol, in igc_add_hw_stats()
2774 CTLFLAG_RD, &stats->scc, in igc_add_hw_stats()
2777 CTLFLAG_RD, &stats->mcc, in igc_add_hw_stats()
2780 CTLFLAG_RD, &stats->latecol, in igc_add_hw_stats()
2783 CTLFLAG_RD, &stats->colc, in igc_add_hw_stats()
2786 CTLFLAG_RD, &sc->stats.symerrs, in igc_add_hw_stats()
2789 CTLFLAG_RD, &sc->stats.sec, in igc_add_hw_stats()
2792 CTLFLAG_RD, &sc->stats.dc, in igc_add_hw_stats()
2795 CTLFLAG_RD, &sc->stats.mpc, in igc_add_hw_stats()
2798 CTLFLAG_RD, &sc->stats.rlec, in igc_add_hw_stats()
2801 CTLFLAG_RD, &sc->stats.rnbc, in igc_add_hw_stats()
2804 CTLFLAG_RD, &sc->stats.ruc, in igc_add_hw_stats()
2807 CTLFLAG_RD, &sc->stats.rfc, in igc_add_hw_stats()
2810 CTLFLAG_RD, &sc->stats.roc, in igc_add_hw_stats()
2813 CTLFLAG_RD, &sc->stats.rjc, in igc_add_hw_stats()
2816 CTLFLAG_RD, &sc->stats.rxerrc, in igc_add_hw_stats()
2819 CTLFLAG_RD, &sc->stats.crcerrs, in igc_add_hw_stats()
2822 CTLFLAG_RD, &sc->stats.algnerrc, in igc_add_hw_stats()
2825 CTLFLAG_RD, &sc->stats.xonrxc, in igc_add_hw_stats()
2828 CTLFLAG_RD, &sc->stats.xontxc, in igc_add_hw_stats()
2831 CTLFLAG_RD, &sc->stats.xoffrxc, in igc_add_hw_stats()
2834 CTLFLAG_RD, &sc->stats.xofftxc, in igc_add_hw_stats()
2837 CTLFLAG_RD, &sc->stats.fcruc, in igc_add_hw_stats()
2840 CTLFLAG_RD, &sc->stats.mgprc, in igc_add_hw_stats()
2843 CTLFLAG_RD, &sc->stats.mgpdc, in igc_add_hw_stats()
2846 CTLFLAG_RD, &sc->stats.mgptc, in igc_add_hw_stats()
2851 CTLFLAG_RD, &sc->stats.tpr, in igc_add_hw_stats()
2854 CTLFLAG_RD, &sc->stats.gprc, in igc_add_hw_stats()
2857 CTLFLAG_RD, &sc->stats.bprc, in igc_add_hw_stats()
2860 CTLFLAG_RD, &sc->stats.mprc, in igc_add_hw_stats()
2863 CTLFLAG_RD, &sc->stats.prc64, in igc_add_hw_stats()
2866 CTLFLAG_RD, &sc->stats.prc127, in igc_add_hw_stats()
2867 "65-127 byte frames received"); in igc_add_hw_stats()
2869 CTLFLAG_RD, &sc->stats.prc255, in igc_add_hw_stats()
2870 "128-255 byte frames received"); in igc_add_hw_stats()
2872 CTLFLAG_RD, &sc->stats.prc511, in igc_add_hw_stats()
2873 "256-511 byte frames received"); in igc_add_hw_stats()
2875 CTLFLAG_RD, &sc->stats.prc1023, in igc_add_hw_stats()
2876 "512-1023 byte frames received"); in igc_add_hw_stats()
2878 CTLFLAG_RD, &sc->stats.prc1522, in igc_add_hw_stats()
2879 "1023-1522 byte frames received"); in igc_add_hw_stats()
2881 CTLFLAG_RD, &sc->stats.gorc, in igc_add_hw_stats()
2886 CTLFLAG_RD, &sc->stats.gotc, in igc_add_hw_stats()
2889 CTLFLAG_RD, &sc->stats.tpt, in igc_add_hw_stats()
2892 CTLFLAG_RD, &sc->stats.gptc, in igc_add_hw_stats()
2895 CTLFLAG_RD, &sc->stats.bptc, in igc_add_hw_stats()
2898 CTLFLAG_RD, &sc->stats.mptc, in igc_add_hw_stats()
2901 CTLFLAG_RD, &sc->stats.ptc64, in igc_add_hw_stats()
2904 CTLFLAG_RD, &sc->stats.ptc127, in igc_add_hw_stats()
2905 "65-127 byte frames transmitted"); in igc_add_hw_stats()
2907 CTLFLAG_RD, &sc->stats.ptc255, in igc_add_hw_stats()
2908 "128-255 byte frames transmitted"); in igc_add_hw_stats()
2910 CTLFLAG_RD, &sc->stats.ptc511, in igc_add_hw_stats()
2911 "256-511 byte frames transmitted"); in igc_add_hw_stats()
2913 CTLFLAG_RD, &sc->stats.ptc1023, in igc_add_hw_stats()
2914 "512-1023 byte frames transmitted"); in igc_add_hw_stats()
2916 CTLFLAG_RD, &sc->stats.ptc1522, in igc_add_hw_stats()
2917 "1024-1522 byte frames transmitted"); in igc_add_hw_stats()
2919 CTLFLAG_RD, &sc->stats.tsctc, in igc_add_hw_stats()
2928 CTLFLAG_RD, &sc->stats.iac, in igc_add_hw_stats()
2932 CTLFLAG_RD, &sc->stats.rxdmtc, in igc_add_hw_stats()
2939 struct igc_hw *hw = &sc->hw; in igc_fw_version()
2940 struct igc_fw_version *fw_ver = &sc->fw_ver; in igc_fw_version()
2952 if (fw_ver->eep_major || fw_ver->eep_minor || fw_ver->eep_build) { in igc_sbuf_fw_version()
2953 sbuf_printf(buf, "EEPROM V%d.%d-%d", fw_ver->eep_major, in igc_sbuf_fw_version()
2954 fw_ver->eep_minor, fw_ver->eep_build); in igc_sbuf_fw_version()
2958 if (fw_ver->invm_major || fw_ver->invm_minor || in igc_sbuf_fw_version()
2959 fw_ver->invm_img_type) { in igc_sbuf_fw_version()
2961 space, fw_ver->invm_major, fw_ver->invm_minor, in igc_sbuf_fw_version()
2962 fw_ver->invm_img_type); in igc_sbuf_fw_version()
2966 if (fw_ver->or_valid) { in igc_sbuf_fw_version()
2967 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d", in igc_sbuf_fw_version()
2968 space, fw_ver->or_major, fw_ver->or_build, in igc_sbuf_fw_version()
2969 fw_ver->or_patch); in igc_sbuf_fw_version()
2973 if (fw_ver->etrack_id) in igc_sbuf_fw_version()
2974 sbuf_printf(buf, "%seTrack 0x%08x", space, fw_ver->etrack_id); in igc_sbuf_fw_version()
2980 device_t dev = sc->dev; in igc_print_fw_version()
2990 igc_sbuf_fw_version(&sc->fw_ver, buf); in igc_print_fw_version()
3005 device_t dev = sc->dev; in igc_sysctl_print_fw_version()
3015 igc_sbuf_fw_version(&sc->fw_ver, buf); in igc_sysctl_print_fw_version()
3040 result = -1; in igc_sysctl_nvm_info()
3043 if (error || !req->newptr) in igc_sysctl_nvm_info()
3048 * first 32 16-bit words of the EEPROM to in igc_sysctl_nvm_info()
3071 igc_read_nvm(&sc->hw, i, 1, &eeprom_data); in igc_print_nvm_info()
3084 sc = oidp->oid_arg1; in igc_sysctl_tso_tcp_flags_mask()
3085 switch (oidp->oid_arg2) { in igc_sysctl_tso_tcp_flags_mask()
3102 val = IGC_READ_REG(&sc->hw, reg); in igc_sysctl_tso_tcp_flags_mask()
3105 if (error != 0 || req->newptr == NULL) in igc_sysctl_tso_tcp_flags_mask()
3110 IGC_WRITE_REG(&sc->hw, reg, val); in igc_sysctl_tso_tcp_flags_mask()
3117 * 0 - off
3118 * 1 - rx pause
3119 * 2 - tx pause
3120 * 3 - full
3131 if ((error) || (req->newptr == NULL)) in igc_set_flowcntl()
3134 if (input == sc->fc) /* no change? */ in igc_set_flowcntl()
3142 sc->hw.fc.requested_mode = input; in igc_set_flowcntl()
3143 sc->fc = input; in igc_set_flowcntl()
3150 sc->hw.fc.current_mode = sc->hw.fc.requested_mode; in igc_set_flowcntl()
3151 igc_force_mac_fc(&sc->hw); in igc_set_flowcntl()
3158 * 0/1 - off/on
3160 * 250,500,1000-10000 in thousands
3168 error = sysctl_handle_int(oidp, &sc->dmac, 0, req); in igc_sysctl_dmac()
3170 if ((error) || (req->newptr == NULL)) in igc_sysctl_dmac()
3173 switch (sc->dmac) { in igc_sysctl_dmac()
3178 sc->dmac = 1000; in igc_sysctl_dmac()
3192 /* Legal values - allow */ in igc_sysctl_dmac()
3196 sc->dmac = 0; in igc_sysctl_dmac()
3200 igc_if_init(sc->ctx); in igc_sysctl_dmac()
3207 * 0/1 - enabled/disabled
3215 value = sc->hw.dev_spec._i225.eee_disable; in igc_sysctl_eee()
3217 if (error || req->newptr == NULL) in igc_sysctl_eee()
3220 sc->hw.dev_spec._i225.eee_disable = (value != 0); in igc_sysctl_eee()
3221 igc_if_init(sc->ctx); in igc_sysctl_eee()
3233 result = -1; in igc_sysctl_debug_info()
3236 if (error || !req->newptr) in igc_sysctl_debug_info()
3257 if (error || !req->newptr || result != 1) in igc_get_rs()
3272 * needed for debugging a problem. -jfv
3277 device_t dev = iflib_get_dev(sc->ctx); in igc_print_debug_info()
3278 if_t ifp = iflib_get_ifp(sc->ctx); in igc_print_debug_info()
3279 struct tx_ring *txr = &sc->tx_queues->txr; in igc_print_debug_info()
3280 struct rx_ring *rxr = &sc->rx_queues->rxr; in igc_print_debug_info()
3292 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { in igc_print_debug_info()
3293 device_printf(dev, "TX Queue %d ------\n", i); in igc_print_debug_info()
3295 IGC_READ_REG(&sc->hw, IGC_TDH(i)), in igc_print_debug_info()
3296 IGC_READ_REG(&sc->hw, IGC_TDT(i))); in igc_print_debug_info()
3299 for (int j=0; j < sc->rx_num_queues; j++, rxr++) { in igc_print_debug_info()
3300 device_printf(dev, "RX Queue %d ------\n", j); in igc_print_debug_info()
3302 IGC_READ_REG(&sc->hw, IGC_RDH(j)), in igc_print_debug_info()
3303 IGC_READ_REG(&sc->hw, IGC_RDT(j))); in igc_print_debug_info()