Lines Matching refs:pdata
120 static inline unsigned int xgbe_get_max_frame(struct xgbe_prv_data *pdata) in xgbe_get_max_frame() argument
122 return (if_getmtu(pdata->netdev) + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); in xgbe_get_max_frame()
126 xgbe_usec_to_riwt(struct xgbe_prv_data *pdata, unsigned int usec) in xgbe_usec_to_riwt() argument
131 rate = pdata->sysclk_rate; in xgbe_usec_to_riwt()
145 xgbe_riwt_to_usec(struct xgbe_prv_data *pdata, unsigned int riwt) in xgbe_riwt_to_usec() argument
150 rate = pdata->sysclk_rate; in xgbe_riwt_to_usec()
164 xgbe_config_pbl_val(struct xgbe_prv_data *pdata) in xgbe_config_pbl_val() argument
170 pbl = pdata->pbl; in xgbe_config_pbl_val()
172 if (pdata->pbl > 32) { in xgbe_config_pbl_val()
177 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_pbl_val()
178 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, PBLX8, in xgbe_config_pbl_val()
181 if (pdata->channel[i]->tx_ring) in xgbe_config_pbl_val()
182 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, in xgbe_config_pbl_val()
185 if (pdata->channel[i]->rx_ring) in xgbe_config_pbl_val()
186 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, in xgbe_config_pbl_val()
194 xgbe_config_osp_mode(struct xgbe_prv_data *pdata) in xgbe_config_osp_mode() argument
198 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_osp_mode()
199 if (!pdata->channel[i]->tx_ring) in xgbe_config_osp_mode()
202 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, OSP, in xgbe_config_osp_mode()
203 pdata->tx_osp_mode); in xgbe_config_osp_mode()
210 xgbe_config_rsf_mode(struct xgbe_prv_data *pdata, unsigned int val) in xgbe_config_rsf_mode() argument
214 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_config_rsf_mode()
215 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RSF, val); in xgbe_config_rsf_mode()
221 xgbe_config_tsf_mode(struct xgbe_prv_data *pdata, unsigned int val) in xgbe_config_tsf_mode() argument
225 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_config_tsf_mode()
226 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TSF, val); in xgbe_config_tsf_mode()
232 xgbe_config_rx_threshold(struct xgbe_prv_data *pdata, unsigned int val) in xgbe_config_rx_threshold() argument
236 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_config_rx_threshold()
237 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RTC, val); in xgbe_config_rx_threshold()
243 xgbe_config_tx_threshold(struct xgbe_prv_data *pdata, unsigned int val) in xgbe_config_tx_threshold() argument
247 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_config_tx_threshold()
248 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TTC, val); in xgbe_config_tx_threshold()
254 xgbe_config_rx_coalesce(struct xgbe_prv_data *pdata) in xgbe_config_rx_coalesce() argument
258 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_rx_coalesce()
259 if (!pdata->channel[i]->rx_ring) in xgbe_config_rx_coalesce()
262 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RIWT, RWT, in xgbe_config_rx_coalesce()
263 pdata->rx_riwt); in xgbe_config_rx_coalesce()
270 xgbe_config_tx_coalesce(struct xgbe_prv_data *pdata) in xgbe_config_tx_coalesce() argument
276 xgbe_config_rx_buffer_size(struct xgbe_prv_data *pdata) in xgbe_config_rx_buffer_size() argument
280 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_rx_buffer_size()
281 if (!pdata->channel[i]->rx_ring) in xgbe_config_rx_buffer_size()
284 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, RBSZ, in xgbe_config_rx_buffer_size()
285 pdata->rx_buf_size); in xgbe_config_rx_buffer_size()
290 xgbe_config_tso_mode(struct xgbe_prv_data *pdata) in xgbe_config_tso_mode() argument
294 int tso_enabled = (if_getcapenable(pdata->netdev) & IFCAP_TSO); in xgbe_config_tso_mode()
296 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_tso_mode()
297 if (!pdata->channel[i]->tx_ring) in xgbe_config_tso_mode()
301 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, TSE, tso_enabled ? 1 : 0); in xgbe_config_tso_mode()
306 xgbe_config_sph_mode(struct xgbe_prv_data *pdata) in xgbe_config_sph_mode() argument
309 int sph_enable_flag = XGMAC_IOREAD_BITS(pdata, MAC_HWF1R, SPHEN); in xgbe_config_sph_mode()
312 pdata->sph_enable, sph_enable_flag); in xgbe_config_sph_mode()
314 if (pdata->sph_enable && sph_enable_flag) in xgbe_config_sph_mode()
317 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_sph_mode()
318 if (!pdata->channel[i]->rx_ring) in xgbe_config_sph_mode()
320 if (pdata->sph_enable && sph_enable_flag) { in xgbe_config_sph_mode()
322 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, SPH, 1); in xgbe_config_sph_mode()
325 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, SPH, 0); in xgbe_config_sph_mode()
329 int val = XGMAC_DMA_IOREAD_BITS(pdata->channel[i], DMA_CH_CR, SPH); in xgbe_config_sph_mode()
334 if (pdata->sph_enable && sph_enable_flag) in xgbe_config_sph_mode()
335 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, HDSMS, XGBE_SPH_HDSMS_SIZE); in xgbe_config_sph_mode()
339 xgbe_write_rss_reg(struct xgbe_prv_data *pdata, unsigned int type, in xgbe_write_rss_reg() argument
345 mtx_lock(&pdata->rss_mutex); in xgbe_write_rss_reg()
347 if (XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) { in xgbe_write_rss_reg()
352 XGMAC_IOWRITE(pdata, MAC_RSSDR, val); in xgbe_write_rss_reg()
354 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, RSSIA, index); in xgbe_write_rss_reg()
355 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, ADDRT, type); in xgbe_write_rss_reg()
356 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, CT, 0); in xgbe_write_rss_reg()
357 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, OB, 1); in xgbe_write_rss_reg()
361 if (!XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) in xgbe_write_rss_reg()
370 mtx_unlock(&pdata->rss_mutex); in xgbe_write_rss_reg()
376 xgbe_write_rss_hash_key(struct xgbe_prv_data *pdata) in xgbe_write_rss_hash_key() argument
378 unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(uint32_t); in xgbe_write_rss_hash_key()
379 unsigned int *key = (unsigned int *)&pdata->rss_key; in xgbe_write_rss_hash_key()
383 ret = xgbe_write_rss_reg(pdata, XGBE_RSS_HASH_KEY_TYPE, in xgbe_write_rss_hash_key()
393 xgbe_write_rss_lookup_table(struct xgbe_prv_data *pdata) in xgbe_write_rss_lookup_table() argument
398 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) { in xgbe_write_rss_lookup_table()
399 ret = xgbe_write_rss_reg(pdata, XGBE_RSS_LOOKUP_TABLE_TYPE, i, in xgbe_write_rss_lookup_table()
400 pdata->rss_table[i]); in xgbe_write_rss_lookup_table()
409 xgbe_set_rss_hash_key(struct xgbe_prv_data *pdata, const uint8_t *key) in xgbe_set_rss_hash_key() argument
411 memcpy(pdata->rss_key, key, sizeof(pdata->rss_key)); in xgbe_set_rss_hash_key()
413 return (xgbe_write_rss_hash_key(pdata)); in xgbe_set_rss_hash_key()
417 xgbe_set_rss_lookup_table(struct xgbe_prv_data *pdata, const uint32_t *table) in xgbe_set_rss_lookup_table() argument
421 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) in xgbe_set_rss_lookup_table()
422 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, table[i]); in xgbe_set_rss_lookup_table()
424 return (xgbe_write_rss_lookup_table(pdata)); in xgbe_set_rss_lookup_table()
428 xgbe_enable_rss(struct xgbe_prv_data *pdata) in xgbe_enable_rss() argument
432 if (!pdata->hw_feat.rss) in xgbe_enable_rss()
436 ret = xgbe_write_rss_hash_key(pdata); in xgbe_enable_rss()
441 ret = xgbe_write_rss_lookup_table(pdata); in xgbe_enable_rss()
446 XGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options); in xgbe_enable_rss()
449 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 1); in xgbe_enable_rss()
457 xgbe_disable_rss(struct xgbe_prv_data *pdata) in xgbe_disable_rss() argument
459 if (!pdata->hw_feat.rss) in xgbe_disable_rss()
462 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 0); in xgbe_disable_rss()
470 xgbe_config_rss(struct xgbe_prv_data *pdata) in xgbe_config_rss() argument
474 if (!pdata->hw_feat.rss) in xgbe_config_rss()
478 if (pdata->enable_rss) in xgbe_config_rss()
479 ret = xgbe_enable_rss(pdata); in xgbe_config_rss()
481 ret = xgbe_disable_rss(pdata); in xgbe_config_rss()
488 xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata) in xgbe_disable_tx_flow_control() argument
495 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_disable_tx_flow_control()
496 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0); in xgbe_disable_tx_flow_control()
500 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count); in xgbe_disable_tx_flow_control()
503 reg_val = XGMAC_IOREAD(pdata, reg); in xgbe_disable_tx_flow_control()
505 XGMAC_IOWRITE(pdata, reg, reg_val); in xgbe_disable_tx_flow_control()
514 xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata) in xgbe_enable_tx_flow_control() argument
521 for (i = 0; i < pdata->rx_q_count; i++) { in xgbe_enable_tx_flow_control()
524 if (pdata->rx_rfd[i]) { in xgbe_enable_tx_flow_control()
530 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, ehfc); in xgbe_enable_tx_flow_control()
538 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count); in xgbe_enable_tx_flow_control()
541 reg_val = XGMAC_IOREAD(pdata, reg); in xgbe_enable_tx_flow_control()
549 XGMAC_IOWRITE(pdata, reg, reg_val); in xgbe_enable_tx_flow_control()
558 xgbe_disable_rx_flow_control(struct xgbe_prv_data *pdata) in xgbe_disable_rx_flow_control() argument
560 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 0); in xgbe_disable_rx_flow_control()
566 xgbe_enable_rx_flow_control(struct xgbe_prv_data *pdata) in xgbe_enable_rx_flow_control() argument
568 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 1); in xgbe_enable_rx_flow_control()
574 xgbe_config_tx_flow_control(struct xgbe_prv_data *pdata) in xgbe_config_tx_flow_control() argument
576 if (pdata->tx_pause) in xgbe_config_tx_flow_control()
577 xgbe_enable_tx_flow_control(pdata); in xgbe_config_tx_flow_control()
579 xgbe_disable_tx_flow_control(pdata); in xgbe_config_tx_flow_control()
585 xgbe_config_rx_flow_control(struct xgbe_prv_data *pdata) in xgbe_config_rx_flow_control() argument
587 if (pdata->rx_pause) in xgbe_config_rx_flow_control()
588 xgbe_enable_rx_flow_control(pdata); in xgbe_config_rx_flow_control()
590 xgbe_disable_rx_flow_control(pdata); in xgbe_config_rx_flow_control()
596 xgbe_config_flow_control(struct xgbe_prv_data *pdata) in xgbe_config_flow_control() argument
598 xgbe_config_tx_flow_control(pdata); in xgbe_config_flow_control()
599 xgbe_config_rx_flow_control(pdata); in xgbe_config_flow_control()
601 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0); in xgbe_config_flow_control()
605 xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata) in xgbe_enable_dma_interrupts() argument
611 if (pdata->channel_irq_mode) in xgbe_enable_dma_interrupts()
612 XGMAC_IOWRITE_BITS(pdata, DMA_MR, INTM, in xgbe_enable_dma_interrupts()
613 pdata->channel_irq_mode); in xgbe_enable_dma_interrupts()
615 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER); in xgbe_enable_dma_interrupts()
617 for (i = 0; i < pdata->channel_count; i++) { in xgbe_enable_dma_interrupts()
618 channel = pdata->channel[i]; in xgbe_enable_dma_interrupts()
647 if (!pdata->per_channel_irq || pdata->channel_irq_mode) in xgbe_enable_dma_interrupts()
659 if (!pdata->per_channel_irq || pdata->channel_irq_mode) in xgbe_enable_dma_interrupts()
669 xgbe_enable_mtl_interrupts(struct xgbe_prv_data *pdata) in xgbe_enable_mtl_interrupts() argument
674 q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt); in xgbe_enable_mtl_interrupts()
677 mtl_q_isr = XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR); in xgbe_enable_mtl_interrupts()
678 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_ISR, mtl_q_isr); in xgbe_enable_mtl_interrupts()
681 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_IER, 0); in xgbe_enable_mtl_interrupts()
686 xgbe_enable_mac_interrupts(struct xgbe_prv_data *pdata) in xgbe_enable_mac_interrupts() argument
693 XGMAC_IOWRITE(pdata, MAC_IER, mac_ier); in xgbe_enable_mac_interrupts()
696 XGMAC_IOWRITE_BITS(pdata, MMC_RIER, ALL_INTERRUPTS, 0xffffffff); in xgbe_enable_mac_interrupts()
697 XGMAC_IOWRITE_BITS(pdata, MMC_TIER, ALL_INTERRUPTS, 0xffffffff); in xgbe_enable_mac_interrupts()
700 XGMAC_IOWRITE_BITS(pdata, MAC_MDIOIER, SNGLCOMPIE, 1); in xgbe_enable_mac_interrupts()
704 xgbe_set_speed(struct xgbe_prv_data *pdata, int speed) in xgbe_set_speed() argument
722 if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) != ss) in xgbe_set_speed()
723 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, ss); in xgbe_set_speed()
729 xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data *pdata) in xgbe_enable_rx_vlan_stripping() argument
732 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLRXS, 1); in xgbe_enable_rx_vlan_stripping()
735 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, DOVLTC, 1); in xgbe_enable_rx_vlan_stripping()
738 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERSVLM, 0); in xgbe_enable_rx_vlan_stripping()
741 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ESVL, 0); in xgbe_enable_rx_vlan_stripping()
744 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0x3); in xgbe_enable_rx_vlan_stripping()
752 xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data *pdata) in xgbe_disable_rx_vlan_stripping() argument
754 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0); in xgbe_disable_rx_vlan_stripping()
762 xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data *pdata) in xgbe_enable_rx_vlan_filtering() argument
765 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1); in xgbe_enable_rx_vlan_filtering()
768 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTHM, 1); in xgbe_enable_rx_vlan_filtering()
771 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTIM, 0); in xgbe_enable_rx_vlan_filtering()
774 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ETV, 1); in xgbe_enable_rx_vlan_filtering()
782 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VL, 1); in xgbe_enable_rx_vlan_filtering()
790 xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data *pdata) in xgbe_disable_rx_vlan_filtering() argument
793 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0); in xgbe_disable_rx_vlan_filtering()
826 xgbe_update_vlan_hash_table(struct xgbe_prv_data *pdata) in xgbe_update_vlan_hash_table() argument
834 XGMAC_IOREAD(pdata, MAC_VLANHTR)); in xgbe_update_vlan_hash_table()
837 bit_foreach(pdata->active_vlans, VLAN_NVID, vid) { in xgbe_update_vlan_hash_table()
849 XGMAC_IOWRITE_BITS(pdata, MAC_VLANHTR, VLHT, vlan_hash_table); in xgbe_update_vlan_hash_table()
852 XGMAC_IOREAD(pdata, MAC_VLANHTR)); in xgbe_update_vlan_hash_table()
858 xgbe_set_promiscuous_mode(struct xgbe_prv_data *pdata, unsigned int enable) in xgbe_set_promiscuous_mode() argument
862 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == val) in xgbe_set_promiscuous_mode()
867 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, val); in xgbe_set_promiscuous_mode()
872 xgbe_disable_rx_vlan_filtering(pdata); in xgbe_set_promiscuous_mode()
874 if ((if_getcapenable(pdata->netdev) & IFCAP_VLAN_HWFILTER)) { in xgbe_set_promiscuous_mode()
876 xgbe_enable_rx_vlan_filtering(pdata); in xgbe_set_promiscuous_mode()
884 xgbe_set_all_multicast_mode(struct xgbe_prv_data *pdata, unsigned int enable) in xgbe_set_all_multicast_mode() argument
888 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PM) == val) in xgbe_set_all_multicast_mode()
892 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, val); in xgbe_set_all_multicast_mode()
898 xgbe_set_mac_reg(struct xgbe_prv_data *pdata, char *addr, unsigned int *mac_reg) in xgbe_set_mac_reg() argument
921 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_hi); in xgbe_set_mac_reg()
923 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_lo); in xgbe_set_mac_reg()
928 xgbe_set_mac_addn_addrs(struct xgbe_prv_data *pdata) in xgbe_set_mac_addn_addrs() argument
934 addn_macs = pdata->hw_feat.addn_mac; in xgbe_set_mac_addn_addrs()
936 xgbe_set_mac_reg(pdata, pdata->mac_addr, &mac_reg); in xgbe_set_mac_addn_addrs()
941 xgbe_set_mac_reg(pdata, NULL, &mac_reg); in xgbe_set_mac_addn_addrs()
945 xgbe_add_mac_addresses(struct xgbe_prv_data *pdata) in xgbe_add_mac_addresses() argument
948 xgbe_set_mac_addn_addrs(pdata); in xgbe_add_mac_addresses()
954 xgbe_set_mac_address(struct xgbe_prv_data *pdata, uint8_t *addr) in xgbe_set_mac_address() argument
962 XGMAC_IOWRITE(pdata, MAC_MACA0HR, mac_addr_hi); in xgbe_set_mac_address()
963 XGMAC_IOWRITE(pdata, MAC_MACA0LR, mac_addr_lo); in xgbe_set_mac_address()
969 xgbe_config_rx_mode(struct xgbe_prv_data *pdata) in xgbe_config_rx_mode() argument
973 pr_mode = ((if_getflags(pdata->netdev) & IFF_PROMISC) != 0); in xgbe_config_rx_mode()
974 am_mode = ((if_getflags(pdata->netdev) & IFF_ALLMULTI) != 0); in xgbe_config_rx_mode()
976 xgbe_set_promiscuous_mode(pdata, pr_mode); in xgbe_config_rx_mode()
977 xgbe_set_all_multicast_mode(pdata, am_mode); in xgbe_config_rx_mode()
979 xgbe_add_mac_addresses(pdata); in xgbe_config_rx_mode()
985 xgbe_clr_gpio(struct xgbe_prv_data *pdata, unsigned int gpio) in xgbe_clr_gpio() argument
992 reg = XGMAC_IOREAD(pdata, MAC_GPIOSR); in xgbe_clr_gpio()
995 XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg); in xgbe_clr_gpio()
1001 xgbe_set_gpio(struct xgbe_prv_data *pdata, unsigned int gpio) in xgbe_set_gpio() argument
1008 reg = XGMAC_IOREAD(pdata, MAC_GPIOSR); in xgbe_set_gpio()
1011 XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg); in xgbe_set_gpio()
1017 xgbe_read_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad, int mmd_reg) in xgbe_read_mmd_regs_v2() argument
1026 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); in xgbe_read_mmd_regs_v2()
1038 index = mmd_address & ~pdata->xpcs_window_mask; in xgbe_read_mmd_regs_v2()
1039 offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask); in xgbe_read_mmd_regs_v2()
1041 spin_lock_irqsave(&pdata->xpcs_lock, flags); in xgbe_read_mmd_regs_v2()
1042 XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index); in xgbe_read_mmd_regs_v2()
1043 mmd_data = XPCS16_IOREAD(pdata, offset); in xgbe_read_mmd_regs_v2()
1044 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); in xgbe_read_mmd_regs_v2()
1050 xgbe_write_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad, int mmd_reg, in xgbe_write_mmd_regs_v2() argument
1059 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); in xgbe_write_mmd_regs_v2()
1071 index = mmd_address & ~pdata->xpcs_window_mask; in xgbe_write_mmd_regs_v2()
1072 offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask); in xgbe_write_mmd_regs_v2()
1074 spin_lock_irqsave(&pdata->xpcs_lock, flags); in xgbe_write_mmd_regs_v2()
1075 XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index); in xgbe_write_mmd_regs_v2()
1076 XPCS16_IOWRITE(pdata, offset, mmd_data); in xgbe_write_mmd_regs_v2()
1077 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); in xgbe_write_mmd_regs_v2()
1081 xgbe_read_mmd_regs_v1(struct xgbe_prv_data *pdata, int prtad, int mmd_reg) in xgbe_read_mmd_regs_v1() argument
1090 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); in xgbe_read_mmd_regs_v1()
1101 spin_lock_irqsave(&pdata->xpcs_lock, flags); in xgbe_read_mmd_regs_v1()
1102 XPCS32_IOWRITE(pdata, PCS_V1_WINDOW_SELECT, mmd_address >> 8); in xgbe_read_mmd_regs_v1()
1103 mmd_data = XPCS32_IOREAD(pdata, (mmd_address & 0xff) << 2); in xgbe_read_mmd_regs_v1()
1104 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); in xgbe_read_mmd_regs_v1()
1110 xgbe_write_mmd_regs_v1(struct xgbe_prv_data *pdata, int prtad, int mmd_reg, in xgbe_write_mmd_regs_v1() argument
1119 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); in xgbe_write_mmd_regs_v1()
1130 spin_lock_irqsave(&pdata->xpcs_lock, flags); in xgbe_write_mmd_regs_v1()
1131 XPCS32_IOWRITE(pdata, PCS_V1_WINDOW_SELECT, mmd_address >> 8); in xgbe_write_mmd_regs_v1()
1132 XPCS32_IOWRITE(pdata, (mmd_address & 0xff) << 2, mmd_data); in xgbe_write_mmd_regs_v1()
1133 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); in xgbe_write_mmd_regs_v1()
1137 xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad, int mmd_reg) in xgbe_read_mmd_regs() argument
1139 switch (pdata->vdata->xpcs_access) { in xgbe_read_mmd_regs()
1141 return (xgbe_read_mmd_regs_v1(pdata, prtad, mmd_reg)); in xgbe_read_mmd_regs()
1145 return (xgbe_read_mmd_regs_v2(pdata, prtad, mmd_reg)); in xgbe_read_mmd_regs()
1150 xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad, int mmd_reg, in xgbe_write_mmd_regs() argument
1153 switch (pdata->vdata->xpcs_access) { in xgbe_write_mmd_regs()
1155 return (xgbe_write_mmd_regs_v1(pdata, prtad, mmd_reg, mmd_data)); in xgbe_write_mmd_regs()
1159 return (xgbe_write_mmd_regs_v2(pdata, prtad, mmd_reg, mmd_data)); in xgbe_write_mmd_regs()
1179 xgbe_write_ext_mii_regs(struct xgbe_prv_data *pdata, int addr, int reg, in xgbe_write_ext_mii_regs() argument
1184 mtx_lock_spin(&pdata->mdio_mutex); in xgbe_write_ext_mii_regs()
1187 XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca); in xgbe_write_ext_mii_regs()
1193 XGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd); in xgbe_write_ext_mii_regs()
1195 if (msleep_spin(pdata, &pdata->mdio_mutex, "mdio_xfer", hz / 8) == in xgbe_write_ext_mii_regs()
1198 mtx_unlock_spin(&pdata->mdio_mutex); in xgbe_write_ext_mii_regs()
1202 mtx_unlock_spin(&pdata->mdio_mutex); in xgbe_write_ext_mii_regs()
1207 xgbe_read_ext_mii_regs(struct xgbe_prv_data *pdata, int addr, int reg) in xgbe_read_ext_mii_regs() argument
1211 mtx_lock_spin(&pdata->mdio_mutex); in xgbe_read_ext_mii_regs()
1214 XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca); in xgbe_read_ext_mii_regs()
1219 XGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd); in xgbe_read_ext_mii_regs()
1221 if (msleep_spin(pdata, &pdata->mdio_mutex, "mdio_xfer", hz / 8) == in xgbe_read_ext_mii_regs()
1224 mtx_unlock_spin(&pdata->mdio_mutex); in xgbe_read_ext_mii_regs()
1228 mtx_unlock_spin(&pdata->mdio_mutex); in xgbe_read_ext_mii_regs()
1230 return (XGMAC_IOREAD_BITS(pdata, MAC_MDIOSCCDR, DATA)); in xgbe_read_ext_mii_regs()
1234 xgbe_set_ext_mii_mode(struct xgbe_prv_data *pdata, unsigned int port, in xgbe_set_ext_mii_mode() argument
1237 unsigned int reg_val = XGMAC_IOREAD(pdata, MAC_MDIOCL22R); in xgbe_set_ext_mii_mode()
1251 XGMAC_IOWRITE(pdata, MAC_MDIOCL22R, reg_val); in xgbe_set_ext_mii_mode()
1263 xgbe_disable_rx_csum(struct xgbe_prv_data *pdata) in xgbe_disable_rx_csum() argument
1265 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 0); in xgbe_disable_rx_csum()
1272 xgbe_enable_rx_csum(struct xgbe_prv_data *pdata) in xgbe_enable_rx_csum() argument
1274 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 1); in xgbe_enable_rx_csum()
1352 struct xgbe_prv_data *pdata = channel->pdata; in xgbe_dev_read() local
1394 pdata->ext_stats.rx_split_header_packets++; in xgbe_dev_read()
1454 (if_getcapenable(pdata->netdev) & IFCAP_VLAN_HWTAGGING)) { in xgbe_dev_read()
1472 pdata->ext_stats.rx_csum_errors++; in xgbe_dev_read()
1480 pdata->ext_stats.rx_vxlan_csum_errors++; in xgbe_dev_read()
1521 struct xgbe_prv_data *pdata = channel->pdata; in xgbe_enable_int() local
1570 struct xgbe_prv_data *pdata = channel->pdata; in xgbe_disable_int() local
1618 __xgbe_exit(struct xgbe_prv_data *pdata) in __xgbe_exit() argument
1623 XGMAC_IOWRITE_BITS(pdata, DMA_MR, SWR, 1); in __xgbe_exit()
1627 while (--count && XGMAC_IOREAD_BITS(pdata, DMA_MR, SWR)) in __xgbe_exit()
1637 xgbe_exit(struct xgbe_prv_data *pdata) in xgbe_exit() argument
1644 ret = __xgbe_exit(pdata); in xgbe_exit()
1650 return (__xgbe_exit(pdata)); in xgbe_exit()
1654 xgbe_flush_tx_queues(struct xgbe_prv_data *pdata) in xgbe_flush_tx_queues() argument
1658 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) < 0x21) in xgbe_flush_tx_queues()
1661 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_flush_tx_queues()
1662 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, FTQ, 1); in xgbe_flush_tx_queues()
1665 for (i = 0; i < pdata->tx_q_count; i++) { in xgbe_flush_tx_queues()
1667 while (--count && XGMAC_MTL_IOREAD_BITS(pdata, i, in xgbe_flush_tx_queues()
1679 xgbe_config_dma_bus(struct xgbe_prv_data *pdata) in xgbe_config_dma_bus() argument
1683 sbmr = XGMAC_IOREAD(pdata, DMA_SBMR); in xgbe_config_dma_bus()
1690 XGMAC_SET_BITS(sbmr, DMA_SBMR, BLEN, pdata->blen >> 2); in xgbe_config_dma_bus()
1691 XGMAC_SET_BITS(sbmr, DMA_SBMR, AAL, pdata->aal); in xgbe_config_dma_bus()
1692 XGMAC_SET_BITS(sbmr, DMA_SBMR, RD_OSR_LMT, pdata->rd_osr_limit - 1); in xgbe_config_dma_bus()
1693 XGMAC_SET_BITS(sbmr, DMA_SBMR, WR_OSR_LMT, pdata->wr_osr_limit - 1); in xgbe_config_dma_bus()
1695 XGMAC_IOWRITE(pdata, DMA_SBMR, sbmr); in xgbe_config_dma_bus()
1698 if (pdata->vdata->tx_desc_prefetch) in xgbe_config_dma_bus()
1699 XGMAC_IOWRITE_BITS(pdata, DMA_TXEDMACR, TDPS, in xgbe_config_dma_bus()
1700 pdata->vdata->tx_desc_prefetch); in xgbe_config_dma_bus()
1702 if (pdata->vdata->rx_desc_prefetch) in xgbe_config_dma_bus()
1703 XGMAC_IOWRITE_BITS(pdata, DMA_RXEDMACR, RDPS, in xgbe_config_dma_bus()
1704 pdata->vdata->rx_desc_prefetch); in xgbe_config_dma_bus()
1708 xgbe_config_dma_cache(struct xgbe_prv_data *pdata) in xgbe_config_dma_cache() argument
1710 XGMAC_IOWRITE(pdata, DMA_AXIARCR, pdata->arcr); in xgbe_config_dma_cache()
1711 XGMAC_IOWRITE(pdata, DMA_AXIAWCR, pdata->awcr); in xgbe_config_dma_cache()
1712 if (pdata->awarcr) in xgbe_config_dma_cache()
1713 XGMAC_IOWRITE(pdata, DMA_AXIAWARCR, pdata->awarcr); in xgbe_config_dma_cache()
1717 xgbe_config_mtl_mode(struct xgbe_prv_data *pdata) in xgbe_config_mtl_mode() argument
1722 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_WRR); in xgbe_config_mtl_mode()
1725 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) { in xgbe_config_mtl_mode()
1726 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, in xgbe_config_mtl_mode()
1728 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 1); in xgbe_config_mtl_mode()
1732 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, RAA, MTL_RAA_SP); in xgbe_config_mtl_mode()
1736 xgbe_queue_flow_control_threshold(struct xgbe_prv_data *pdata, in xgbe_queue_flow_control_threshold() argument
1742 frame_fifo_size = XGMAC_FLOW_CONTROL_ALIGN(xgbe_get_max_frame(pdata)); in xgbe_queue_flow_control_threshold()
1755 pdata->rx_rfa[queue] = 0; in xgbe_queue_flow_control_threshold()
1756 pdata->rx_rfd[queue] = 0; in xgbe_queue_flow_control_threshold()
1762 pdata->rx_rfa[queue] = 0; /* Full - 1024 bytes */ in xgbe_queue_flow_control_threshold()
1763 pdata->rx_rfd[queue] = 1; /* Full - 1536 bytes */ in xgbe_queue_flow_control_threshold()
1769 pdata->rx_rfa[queue] = 2; /* Full - 2048 bytes */ in xgbe_queue_flow_control_threshold()
1770 pdata->rx_rfd[queue] = 5; /* Full - 3584 bytes */ in xgbe_queue_flow_control_threshold()
1790 pdata->rx_rfa[queue] = XGMAC_FLOW_CONTROL_VALUE(rfa); in xgbe_queue_flow_control_threshold()
1791 pdata->rx_rfd[queue] = XGMAC_FLOW_CONTROL_VALUE(rfd); in xgbe_queue_flow_control_threshold()
1793 queue, pdata->rx_rfa[queue], pdata->rx_rfd[queue]); in xgbe_queue_flow_control_threshold()
1797 xgbe_calculate_flow_control_threshold(struct xgbe_prv_data *pdata, in xgbe_calculate_flow_control_threshold() argument
1803 for (i = 0; i < pdata->rx_q_count; i++) { in xgbe_calculate_flow_control_threshold()
1808 xgbe_queue_flow_control_threshold(pdata, i, q_fifo_size); in xgbe_calculate_flow_control_threshold()
1813 xgbe_config_flow_control_threshold(struct xgbe_prv_data *pdata) in xgbe_config_flow_control_threshold() argument
1817 for (i = 0; i < pdata->rx_q_count; i++) { in xgbe_config_flow_control_threshold()
1819 pdata->rx_rfa[i], pdata->rx_rfd[i]); in xgbe_config_flow_control_threshold()
1821 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFA, in xgbe_config_flow_control_threshold()
1822 pdata->rx_rfa[i]); in xgbe_config_flow_control_threshold()
1823 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFD, in xgbe_config_flow_control_threshold()
1824 pdata->rx_rfd[i]); in xgbe_config_flow_control_threshold()
1827 XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQFCR)); in xgbe_config_flow_control_threshold()
1832 xgbe_get_tx_fifo_size(struct xgbe_prv_data *pdata) in xgbe_get_tx_fifo_size() argument
1835 return (min_t(unsigned int, pdata->tx_max_fifo_size, in xgbe_get_tx_fifo_size()
1836 pdata->hw_feat.tx_fifo_size)); in xgbe_get_tx_fifo_size()
1840 xgbe_get_rx_fifo_size(struct xgbe_prv_data *pdata) in xgbe_get_rx_fifo_size() argument
1843 return (min_t(unsigned int, pdata->rx_max_fifo_size, in xgbe_get_rx_fifo_size()
1844 pdata->hw_feat.rx_fifo_size)); in xgbe_get_rx_fifo_size()
1894 xgbe_config_tx_fifo_size(struct xgbe_prv_data *pdata) in xgbe_config_tx_fifo_size() argument
1900 fifo_size = xgbe_get_tx_fifo_size(pdata); in xgbe_config_tx_fifo_size()
1903 xgbe_calculate_equal_fifo(fifo_size, pdata->tx_q_count, fifo); in xgbe_config_tx_fifo_size()
1905 for (i = 0; i < pdata->tx_q_count; i++) { in xgbe_config_tx_fifo_size()
1906 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo[i]); in xgbe_config_tx_fifo_size()
1908 XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQOMR)); in xgbe_config_tx_fifo_size()
1912 pdata->tx_q_count, ((fifo[0] + 1) * XGMAC_FIFO_UNIT)); in xgbe_config_tx_fifo_size()
1916 xgbe_config_rx_fifo_size(struct xgbe_prv_data *pdata) in xgbe_config_rx_fifo_size() argument
1926 fifo_size = xgbe_get_rx_fifo_size(pdata); in xgbe_config_rx_fifo_size()
1927 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); in xgbe_config_rx_fifo_size()
1929 fifo_size, pdata->rx_q_count, prio_queues); in xgbe_config_rx_fifo_size()
1932 fifo_size = xgbe_set_nonprio_fifos(fifo_size, pdata->rx_q_count, fifo); in xgbe_config_rx_fifo_size()
1936 for (i = 0; i < pdata->rx_q_count; i++) { in xgbe_config_rx_fifo_size()
1937 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo[i]); in xgbe_config_rx_fifo_size()
1939 XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQOMR)); in xgbe_config_rx_fifo_size()
1942 xgbe_calculate_flow_control_threshold(pdata, fifo); in xgbe_config_rx_fifo_size()
1943 xgbe_config_flow_control_threshold(pdata); in xgbe_config_rx_fifo_size()
1946 pdata->rx_q_count, ((fifo[0] + 1) * XGMAC_FIFO_UNIT)); in xgbe_config_rx_fifo_size()
1950 xgbe_config_queue_mapping(struct xgbe_prv_data *pdata) in xgbe_config_queue_mapping() argument
1961 qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt; in xgbe_config_queue_mapping()
1962 qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt; in xgbe_config_queue_mapping()
1964 for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) { in xgbe_config_queue_mapping()
1967 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, in xgbe_config_queue_mapping()
1969 pdata->q2tc_map[queue++] = i; in xgbe_config_queue_mapping()
1974 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, in xgbe_config_queue_mapping()
1976 pdata->q2tc_map[queue++] = i; in xgbe_config_queue_mapping()
1981 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); in xgbe_config_queue_mapping()
1992 pdata->prio2q_map[prio++] = i; in xgbe_config_queue_mapping()
1998 pdata->prio2q_map[prio++] = i; in xgbe_config_queue_mapping()
2006 XGMAC_IOWRITE(pdata, reg, reg_val); in xgbe_config_queue_mapping()
2014 for (i = 0; i < pdata->rx_q_count;) { in xgbe_config_queue_mapping()
2017 if ((i % MTL_RQDCM_Q_PER_REG) && (i != pdata->rx_q_count)) in xgbe_config_queue_mapping()
2020 XGMAC_IOWRITE(pdata, reg, reg_val); in xgbe_config_queue_mapping()
2028 xgbe_config_mac_address(struct xgbe_prv_data *pdata) in xgbe_config_mac_address() argument
2030 xgbe_set_mac_address(pdata, if_getlladdr(pdata->netdev)); in xgbe_config_mac_address()
2036 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, RA, 1); in xgbe_config_mac_address()
2039 if (pdata->hw_feat.hash_table_size) { in xgbe_config_mac_address()
2040 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1); in xgbe_config_mac_address()
2041 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1); in xgbe_config_mac_address()
2042 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HMC, 1); in xgbe_config_mac_address()
2047 xgbe_config_jumbo_enable(struct xgbe_prv_data *pdata) in xgbe_config_jumbo_enable() argument
2051 val = (if_getmtu(pdata->netdev) > XGMAC_STD_PACKET_MTU) ? 1 : 0; in xgbe_config_jumbo_enable()
2053 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val); in xgbe_config_jumbo_enable()
2057 xgbe_config_mac_speed(struct xgbe_prv_data *pdata) in xgbe_config_mac_speed() argument
2059 xgbe_set_speed(pdata, pdata->phy_speed); in xgbe_config_mac_speed()
2063 xgbe_config_checksum_offload(struct xgbe_prv_data *pdata) in xgbe_config_checksum_offload() argument
2065 if ((if_getcapenable(pdata->netdev) & IFCAP_RXCSUM)) in xgbe_config_checksum_offload()
2066 xgbe_enable_rx_csum(pdata); in xgbe_config_checksum_offload()
2068 xgbe_disable_rx_csum(pdata); in xgbe_config_checksum_offload()
2072 xgbe_config_vlan_support(struct xgbe_prv_data *pdata) in xgbe_config_vlan_support() argument
2075 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0); in xgbe_config_vlan_support()
2076 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1); in xgbe_config_vlan_support()
2079 xgbe_update_vlan_hash_table(pdata); in xgbe_config_vlan_support()
2081 if ((if_getcapenable(pdata->netdev) & IFCAP_VLAN_HWFILTER)) { in xgbe_config_vlan_support()
2083 xgbe_enable_rx_vlan_filtering(pdata); in xgbe_config_vlan_support()
2086 xgbe_disable_rx_vlan_filtering(pdata); in xgbe_config_vlan_support()
2089 if ((if_getcapenable(pdata->netdev) & IFCAP_VLAN_HWTAGGING)) { in xgbe_config_vlan_support()
2091 xgbe_enable_rx_vlan_stripping(pdata); in xgbe_config_vlan_support()
2094 xgbe_disable_rx_vlan_stripping(pdata); in xgbe_config_vlan_support()
2099 xgbe_mmc_read(struct xgbe_prv_data *pdata, unsigned int reg_lo) in xgbe_mmc_read() argument
2104 if (pdata->vdata->mmc_64bit) { in xgbe_mmc_read()
2133 val = XGMAC_IOREAD(pdata, reg_lo); in xgbe_mmc_read()
2136 val |= ((uint64_t)XGMAC_IOREAD(pdata, reg_lo + 4) << 32); in xgbe_mmc_read()
2142 xgbe_tx_mmc_int(struct xgbe_prv_data *pdata) in xgbe_tx_mmc_int() argument
2144 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; in xgbe_tx_mmc_int()
2145 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_TISR); in xgbe_tx_mmc_int()
2149 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO); in xgbe_tx_mmc_int()
2153 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO); in xgbe_tx_mmc_int()
2157 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO); in xgbe_tx_mmc_int()
2161 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO); in xgbe_tx_mmc_int()
2165 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO); in xgbe_tx_mmc_int()
2169 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO); in xgbe_tx_mmc_int()
2173 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO); in xgbe_tx_mmc_int()
2177 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO); in xgbe_tx_mmc_int()
2181 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO); in xgbe_tx_mmc_int()
2185 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); in xgbe_tx_mmc_int()
2189 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO); in xgbe_tx_mmc_int()
2193 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO); in xgbe_tx_mmc_int()
2197 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO); in xgbe_tx_mmc_int()
2201 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO); in xgbe_tx_mmc_int()
2205 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO); in xgbe_tx_mmc_int()
2209 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO); in xgbe_tx_mmc_int()
2213 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO); in xgbe_tx_mmc_int()
2217 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO); in xgbe_tx_mmc_int()
2221 xgbe_rx_mmc_int(struct xgbe_prv_data *pdata) in xgbe_rx_mmc_int() argument
2223 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; in xgbe_rx_mmc_int()
2224 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_RISR); in xgbe_rx_mmc_int()
2228 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO); in xgbe_rx_mmc_int()
2232 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO); in xgbe_rx_mmc_int()
2236 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO); in xgbe_rx_mmc_int()
2240 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO); in xgbe_rx_mmc_int()
2244 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO); in xgbe_rx_mmc_int()
2248 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO); in xgbe_rx_mmc_int()
2252 xgbe_mmc_read(pdata, MMC_RXRUNTERROR); in xgbe_rx_mmc_int()
2256 xgbe_mmc_read(pdata, MMC_RXJABBERERROR); in xgbe_rx_mmc_int()
2260 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G); in xgbe_rx_mmc_int()
2264 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G); in xgbe_rx_mmc_int()
2268 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO); in xgbe_rx_mmc_int()
2272 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO); in xgbe_rx_mmc_int()
2276 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO); in xgbe_rx_mmc_int()
2280 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO); in xgbe_rx_mmc_int()
2284 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO); in xgbe_rx_mmc_int()
2288 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); in xgbe_rx_mmc_int()
2292 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO); in xgbe_rx_mmc_int()
2296 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO); in xgbe_rx_mmc_int()
2300 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO); in xgbe_rx_mmc_int()
2304 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO); in xgbe_rx_mmc_int()
2308 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO); in xgbe_rx_mmc_int()
2312 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO); in xgbe_rx_mmc_int()
2316 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR); in xgbe_rx_mmc_int()
2320 xgbe_read_mmc_stats(struct xgbe_prv_data *pdata) in xgbe_read_mmc_stats() argument
2322 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; in xgbe_read_mmc_stats()
2325 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1); in xgbe_read_mmc_stats()
2328 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO); in xgbe_read_mmc_stats()
2331 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO); in xgbe_read_mmc_stats()
2334 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO); in xgbe_read_mmc_stats()
2337 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO); in xgbe_read_mmc_stats()
2340 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO); in xgbe_read_mmc_stats()
2343 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO); in xgbe_read_mmc_stats()
2346 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO); in xgbe_read_mmc_stats()
2349 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO); in xgbe_read_mmc_stats()
2352 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO); in xgbe_read_mmc_stats()
2355 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); in xgbe_read_mmc_stats()
2358 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO); in xgbe_read_mmc_stats()
2361 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO); in xgbe_read_mmc_stats()
2364 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO); in xgbe_read_mmc_stats()
2367 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO); in xgbe_read_mmc_stats()
2370 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO); in xgbe_read_mmc_stats()
2373 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO); in xgbe_read_mmc_stats()
2376 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO); in xgbe_read_mmc_stats()
2379 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO); in xgbe_read_mmc_stats()
2382 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO); in xgbe_read_mmc_stats()
2385 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO); in xgbe_read_mmc_stats()
2388 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO); in xgbe_read_mmc_stats()
2391 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO); in xgbe_read_mmc_stats()
2394 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO); in xgbe_read_mmc_stats()
2397 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO); in xgbe_read_mmc_stats()
2400 xgbe_mmc_read(pdata, MMC_RXRUNTERROR); in xgbe_read_mmc_stats()
2403 xgbe_mmc_read(pdata, MMC_RXJABBERERROR); in xgbe_read_mmc_stats()
2406 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G); in xgbe_read_mmc_stats()
2409 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G); in xgbe_read_mmc_stats()
2412 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO); in xgbe_read_mmc_stats()
2415 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO); in xgbe_read_mmc_stats()
2418 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO); in xgbe_read_mmc_stats()
2421 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO); in xgbe_read_mmc_stats()
2424 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO); in xgbe_read_mmc_stats()
2427 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); in xgbe_read_mmc_stats()
2430 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO); in xgbe_read_mmc_stats()
2433 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO); in xgbe_read_mmc_stats()
2436 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO); in xgbe_read_mmc_stats()
2439 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO); in xgbe_read_mmc_stats()
2442 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO); in xgbe_read_mmc_stats()
2445 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO); in xgbe_read_mmc_stats()
2448 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR); in xgbe_read_mmc_stats()
2451 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0); in xgbe_read_mmc_stats()
2455 xgbe_config_mmc(struct xgbe_prv_data *pdata) in xgbe_config_mmc() argument
2458 XGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1); in xgbe_config_mmc()
2461 XGMAC_IOWRITE_BITS(pdata, MMC_CR, CR, 1); in xgbe_config_mmc()
2465 xgbe_txq_prepare_tx_stop(struct xgbe_prv_data *pdata, unsigned int queue) in xgbe_txq_prepare_tx_stop() argument
2476 tx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_TQDR); in xgbe_txq_prepare_tx_stop()
2490 xgbe_prepare_tx_stop(struct xgbe_prv_data *pdata, unsigned int queue) in xgbe_prepare_tx_stop() argument
2496 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) > 0x20) in xgbe_prepare_tx_stop()
2497 return (xgbe_txq_prepare_tx_stop(pdata, queue)); in xgbe_prepare_tx_stop()
2517 tx_status = XGMAC_IOREAD(pdata, tx_dsr); in xgbe_prepare_tx_stop()
2532 xgbe_enable_tx(struct xgbe_prv_data *pdata) in xgbe_enable_tx() argument
2537 for (i = 0; i < pdata->channel_count; i++) { in xgbe_enable_tx()
2538 if (!pdata->channel[i]->tx_ring) in xgbe_enable_tx()
2541 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1); in xgbe_enable_tx()
2545 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_enable_tx()
2546 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, in xgbe_enable_tx()
2550 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); in xgbe_enable_tx()
2554 xgbe_disable_tx(struct xgbe_prv_data *pdata) in xgbe_disable_tx() argument
2559 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_disable_tx()
2560 xgbe_prepare_tx_stop(pdata, i); in xgbe_disable_tx()
2563 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); in xgbe_disable_tx()
2566 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_disable_tx()
2567 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 0); in xgbe_disable_tx()
2570 for (i = 0; i < pdata->channel_count; i++) { in xgbe_disable_tx()
2571 if (!pdata->channel[i]->tx_ring) in xgbe_disable_tx()
2574 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0); in xgbe_disable_tx()
2579 xgbe_prepare_rx_stop(struct xgbe_prv_data *pdata, unsigned int queue) in xgbe_prepare_rx_stop() argument
2590 rx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_RQDR); in xgbe_prepare_rx_stop()
2604 xgbe_enable_rx(struct xgbe_prv_data *pdata) in xgbe_enable_rx() argument
2609 for (i = 0; i < pdata->channel_count; i++) { in xgbe_enable_rx()
2610 if (!pdata->channel[i]->rx_ring) in xgbe_enable_rx()
2613 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1); in xgbe_enable_rx()
2618 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_enable_rx()
2620 XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val); in xgbe_enable_rx()
2623 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1); in xgbe_enable_rx()
2624 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1); in xgbe_enable_rx()
2625 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1); in xgbe_enable_rx()
2626 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1); in xgbe_enable_rx()
2630 xgbe_disable_rx(struct xgbe_prv_data *pdata) in xgbe_disable_rx() argument
2635 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0); in xgbe_disable_rx()
2636 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0); in xgbe_disable_rx()
2637 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0); in xgbe_disable_rx()
2638 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0); in xgbe_disable_rx()
2641 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_disable_rx()
2642 xgbe_prepare_rx_stop(pdata, i); in xgbe_disable_rx()
2645 XGMAC_IOWRITE(pdata, MAC_RQC0R, 0); in xgbe_disable_rx()
2648 for (i = 0; i < pdata->channel_count; i++) { in xgbe_disable_rx()
2649 if (!pdata->channel[i]->rx_ring) in xgbe_disable_rx()
2652 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0); in xgbe_disable_rx()
2657 xgbe_powerup_tx(struct xgbe_prv_data *pdata) in xgbe_powerup_tx() argument
2662 for (i = 0; i < pdata->channel_count; i++) { in xgbe_powerup_tx()
2663 if (!pdata->channel[i]->tx_ring) in xgbe_powerup_tx()
2666 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1); in xgbe_powerup_tx()
2670 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); in xgbe_powerup_tx()
2674 xgbe_powerdown_tx(struct xgbe_prv_data *pdata) in xgbe_powerdown_tx() argument
2679 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_powerdown_tx()
2680 xgbe_prepare_tx_stop(pdata, i); in xgbe_powerdown_tx()
2683 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); in xgbe_powerdown_tx()
2686 for (i = 0; i < pdata->channel_count; i++) { in xgbe_powerdown_tx()
2687 if (!pdata->channel[i]->tx_ring) in xgbe_powerdown_tx()
2690 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0); in xgbe_powerdown_tx()
2695 xgbe_powerup_rx(struct xgbe_prv_data *pdata) in xgbe_powerup_rx() argument
2700 for (i = 0; i < pdata->channel_count; i++) { in xgbe_powerup_rx()
2701 if (!pdata->channel[i]->rx_ring) in xgbe_powerup_rx()
2704 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1); in xgbe_powerup_rx()
2709 xgbe_powerdown_rx(struct xgbe_prv_data *pdata) in xgbe_powerdown_rx() argument
2714 for (i = 0; i < pdata->channel_count; i++) { in xgbe_powerdown_rx()
2715 if (!pdata->channel[i]->rx_ring) in xgbe_powerdown_rx()
2718 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0); in xgbe_powerdown_rx()
2723 xgbe_init(struct xgbe_prv_data *pdata) in xgbe_init() argument
2725 struct xgbe_desc_if *desc_if = &pdata->desc_if; in xgbe_init()
2729 ret = xgbe_flush_tx_queues(pdata); in xgbe_init()
2738 xgbe_config_dma_bus(pdata); in xgbe_init()
2739 xgbe_config_dma_cache(pdata); in xgbe_init()
2740 xgbe_config_osp_mode(pdata); in xgbe_init()
2741 xgbe_config_pbl_val(pdata); in xgbe_init()
2742 xgbe_config_rx_coalesce(pdata); in xgbe_init()
2743 xgbe_config_tx_coalesce(pdata); in xgbe_init()
2744 xgbe_config_rx_buffer_size(pdata); in xgbe_init()
2745 xgbe_config_tso_mode(pdata); in xgbe_init()
2746 xgbe_config_sph_mode(pdata); in xgbe_init()
2747 xgbe_config_rss(pdata); in xgbe_init()
2748 desc_if->wrapper_tx_desc_init(pdata); in xgbe_init()
2749 desc_if->wrapper_rx_desc_init(pdata); in xgbe_init()
2750 xgbe_enable_dma_interrupts(pdata); in xgbe_init()
2755 xgbe_config_mtl_mode(pdata); in xgbe_init()
2756 xgbe_config_queue_mapping(pdata); in xgbe_init()
2757 xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode); in xgbe_init()
2758 xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode); in xgbe_init()
2759 xgbe_config_tx_threshold(pdata, pdata->tx_threshold); in xgbe_init()
2760 xgbe_config_rx_threshold(pdata, pdata->rx_threshold); in xgbe_init()
2761 xgbe_config_tx_fifo_size(pdata); in xgbe_init()
2762 xgbe_config_rx_fifo_size(pdata); in xgbe_init()
2766 xgbe_enable_mtl_interrupts(pdata); in xgbe_init()
2771 xgbe_config_mac_address(pdata); in xgbe_init()
2772 xgbe_config_rx_mode(pdata); in xgbe_init()
2773 xgbe_config_jumbo_enable(pdata); in xgbe_init()
2774 xgbe_config_flow_control(pdata); in xgbe_init()
2775 xgbe_config_mac_speed(pdata); in xgbe_init()
2776 xgbe_config_checksum_offload(pdata); in xgbe_init()
2777 xgbe_config_vlan_support(pdata); in xgbe_init()
2778 xgbe_config_mmc(pdata); in xgbe_init()
2779 xgbe_enable_mac_interrupts(pdata); in xgbe_init()