188 #define	AE_READ_4(sc, reg) \  macro
275 	chiprev = (AE_READ_4(sc, AE_MASTER_REG) >> AE_MASTER_REVNUM_SHIFT) &  in ae_attach()
493 		if ((AE_READ_4(sc, AE_MASTER_REG) & AE_MASTER_SOFT_RESET) == 0)  in ae_reset()
506 		if (AE_READ_4(sc, AE_IDLE_REG) == 0)  in ae_reset()
628 	val = AE_READ_4(sc, AE_MASTER_REG);  in ae_init_locked()
678 	val = AE_READ_4(sc, AE_ISR_REG);  in ae_init_locked()
693 	val = AE_READ_4(sc, AE_MASTER_REG);  in ae_init_locked()
722 	val = AE_READ_4(sc, AE_MAC_REG);  in ae_init_locked()
809 		val = AE_READ_4(sc, AE_MDIO_REG);  in ae_miibus_readreg()
845 		aereg = AE_READ_4(sc, AE_MDIO_REG);  in ae_miibus_writereg()
913 	val = AE_READ_4(sc, AE_SPICTL_REG);  in ae_check_eeprom_present()
938 		val = AE_READ_4(sc, AE_VPD_CAP_REG);  in ae_vpd_read_word()
947 	*word = AE_READ_4(sc, AE_VPD_DATA_REG);  in ae_vpd_read_word()
1021 	eaddr[0] = AE_READ_4(sc, AE_EADDR0_REG);  in ae_get_reg_eaddr()
1022 	eaddr[1] = AE_READ_4(sc, AE_EADDR1_REG);  in ae_get_reg_eaddr()
1354 	val = AE_READ_4(sc, AE_PCIE_PHYMISC_REG);  in ae_pm_init()
1357 	val = AE_READ_4(sc, AE_PCIE_DLL_TX_CTRL_REG);  in ae_pm_init()
1392 	AE_READ_4(sc, AE_WOL_REG);	/* Clear WOL status. */  in ae_resume()
1605 		val = AE_READ_4(sc, AE_MAC_REG);  in ae_link_task()
1623 	val = AE_READ_4(sc, AE_MAC_REG);  in ae_stop_rxmac()
1639 		val = AE_READ_4(sc, AE_IDLE_REG);  in ae_stop_rxmac()
1659 	val = AE_READ_4(sc, AE_MAC_REG);  in ae_stop_txmac()
1675 		val = AE_READ_4(sc, AE_IDLE_REG);  in ae_stop_txmac()
1693 	val = AE_READ_4(sc, AE_MAC_REG);  in ae_mac_config()
1712 	val = AE_READ_4(sc, AE_ISR_REG);  in ae_intr()
1738 	val = AE_READ_4(sc, AE_ISR_REG);	/* Read interrupt status. */  in ae_int_task()
1998 	val = AE_READ_4(sc, AE_MAC_REG);  in ae_rxvlan()
2029 	rxcfg = AE_READ_4(sc, AE_MAC_REG);  in ae_rxfilter()
2171 		if (AE_READ_4(sc, AE_IDLE_REG) == 0)  in ae_stop()