Lines Matching refs:uint32_t
109 ((uint32_t)(TGEC_IMASK_MDIO_SCAN_EVENT | \
152 uint32_t tgec_id; /* 0x000 Controller ID */
153 uint32_t reserved001[1]; /* 0x004 */
154 uint32_t command_config; /* 0x008 Control and configuration */
155 uint32_t mac_addr_0; /* 0x00c Lower 32 bits of the MAC adr */
156 uint32_t mac_addr_1; /* 0x010 Upper 16 bits of the MAC adr */
157 uint32_t maxfrm; /* 0x014 Maximum frame length */
158 uint32_t pause_quant; /* 0x018 Pause quanta */
159 uint32_t rx_fifo_sections; /* 0x01c */
160 uint32_t tx_fifo_sections; /* 0x020 */
161 uint32_t rx_fifo_almost_f_e; /* 0x024 */
162 uint32_t tx_fifo_almost_f_e; /* 0x028 */
163 uint32_t hashtable_ctrl; /* 0x02c Hash table control*/
164 uint32_t mdio_cfg_status; /* 0x030 */
165 uint32_t mdio_command; /* 0x034 */
166 uint32_t mdio_data; /* 0x038 */
167 uint32_t mdio_regaddr; /* 0x03c */
168 uint32_t status; /* 0x040 */
169 uint32_t tx_ipg_len; /* 0x044 Transmitter inter-packet-gap */
170 uint32_t mac_addr_2; /* 0x048 Lower 32 bits of 2nd MAC adr */
171 uint32_t mac_addr_3; /* 0x04c Upper 16 bits of 2nd MAC adr */
172 uint32_t rx_fifo_ptr_rd; /* 0x050 */
173 uint32_t rx_fifo_ptr_wr; /* 0x054 */
174 uint32_t tx_fifo_ptr_rd; /* 0x058 */
175 uint32_t tx_fifo_ptr_wr; /* 0x05c */
176 uint32_t imask; /* 0x060 Interrupt mask */
177 uint32_t ievent; /* 0x064 Interrupt event */
178 uint32_t udp_port; /* 0x068 Defines a UDP Port number */
179 uint32_t type_1588v2; /* 0x06c Type field for 1588v2 */
180 uint32_t reserved070[4]; /* 0x070 */
182 uint32_t tfrm_u; /* 80 aFramesTransmittedOK */
183 uint32_t tfrm_l; /* 84 aFramesTransmittedOK */
184 uint32_t rfrm_u; /* 88 aFramesReceivedOK */
185 uint32_t rfrm_l; /* 8c aFramesReceivedOK */
186 uint32_t rfcs_u; /* 90 aFrameCheckSequenceErrors */
187 uint32_t rfcs_l; /* 94 aFrameCheckSequenceErrors */
188 uint32_t raln_u; /* 98 aAlignmentErrors */
189 uint32_t raln_l; /* 9c aAlignmentErrors */
190 uint32_t txpf_u; /* A0 aPAUSEMACCtrlFramesTransmitted */
191 uint32_t txpf_l; /* A4 aPAUSEMACCtrlFramesTransmitted */
192 uint32_t rxpf_u; /* A8 aPAUSEMACCtrlFramesReceived */
193 uint32_t rxpf_l; /* Ac aPAUSEMACCtrlFramesReceived */
194 uint32_t rlong_u; /* B0 aFrameTooLongErrors */
195 uint32_t rlong_l; /* B4 aFrameTooLongErrors */
196 uint32_t rflr_u; /* B8 aInRangeLengthErrors */
197 uint32_t rflr_l; /* Bc aInRangeLengthErrors */
198 uint32_t tvlan_u; /* C0 VLANTransmittedOK */
199 uint32_t tvlan_l; /* C4 VLANTransmittedOK */
200 uint32_t rvlan_u; /* C8 VLANReceivedOK */
201 uint32_t rvlan_l; /* Cc VLANReceivedOK */
202 uint32_t toct_u; /* D0 ifOutOctets */
203 uint32_t toct_l; /* D4 ifOutOctets */
204 uint32_t roct_u; /* D8 ifInOctets */
205 uint32_t roct_l; /* Dc ifInOctets */
206 uint32_t ruca_u; /* E0 ifInUcastPkts */
207 uint32_t ruca_l; /* E4 ifInUcastPkts */
208 uint32_t rmca_u; /* E8 ifInMulticastPkts */
209 uint32_t rmca_l; /* Ec ifInMulticastPkts */
210 uint32_t rbca_u; /* F0 ifInBroadcastPkts */
211 uint32_t rbca_l; /* F4 ifInBroadcastPkts */
212 uint32_t terr_u; /* F8 ifOutErrors */
213 uint32_t terr_l; /* Fc ifOutErrors */
214 uint32_t reserved100[2]; /* 100-108*/
215 uint32_t tuca_u; /* 108 ifOutUcastPkts */
216 uint32_t tuca_l; /* 10c ifOutUcastPkts */
217 uint32_t tmca_u; /* 110 ifOutMulticastPkts */
218 uint32_t tmca_l; /* 114 ifOutMulticastPkts */
219 uint32_t tbca_u; /* 118 ifOutBroadcastPkts */
220 uint32_t tbca_l; /* 11c ifOutBroadcastPkts */
221 uint32_t rdrp_u; /* 120 etherStatsDropEvents */
222 uint32_t rdrp_l; /* 124 etherStatsDropEvents */
223 uint32_t reoct_u; /* 128 etherStatsOctets */
224 uint32_t reoct_l; /* 12c etherStatsOctets */
225 uint32_t rpkt_u; /* 130 etherStatsPkts */
226 uint32_t rpkt_l; /* 134 etherStatsPkts */
227 uint32_t trund_u; /* 138 etherStatsUndersizePkts */
228 uint32_t trund_l; /* 13c etherStatsUndersizePkts */
229 uint32_t r64_u; /* 140 etherStatsPkts64Octets */
230 uint32_t r64_l; /* 144 etherStatsPkts64Octets */
231 uint32_t r127_u; /* 148 etherStatsPkts65to127Octets */
232 uint32_t r127_l; /* 14c etherStatsPkts65to127Octets */
233 uint32_t r255_u; /* 150 etherStatsPkts128to255Octets */
234 uint32_t r255_l; /* 154 etherStatsPkts128to255Octets */
235 uint32_t r511_u; /* 158 etherStatsPkts256to511Octets */
236 uint32_t r511_l; /* 15c etherStatsPkts256to511Octets */
237 uint32_t r1023_u; /* 160 etherStatsPkts512to1023Octets */
238 uint32_t r1023_l; /* 164 etherStatsPkts512to1023Octets */
239 uint32_t r1518_u; /* 168 etherStatsPkts1024to1518Octets */
240 uint32_t r1518_l; /* 16c etherStatsPkts1024to1518Octets */
241 uint32_t r1519x_u; /* 170 etherStatsPkts1519toX */
242 uint32_t r1519x_l; /* 174 etherStatsPkts1519toX */
243 uint32_t trovr_u; /* 178 etherStatsOversizePkts */
244 uint32_t trovr_l; /* 17c etherStatsOversizePkts */
245 uint32_t trjbr_u; /* 180 etherStatsJabbers */
246 uint32_t trjbr_l; /* 184 etherStatsJabbers */
247 uint32_t trfrg_u; /* 188 etherStatsFragments */
248 uint32_t trfrg_l; /* 18C etherStatsFragments */
249 uint32_t rerr_u; /* 190 ifInErrors */
250 uint32_t rerr_l; /* 194 ifInErrors */
349 uint32_t tx_ipg_length;
369 uint32_t exception_mask);
375 uint32_t fman_tgec_get_revision(struct tgec_regs *regs);
402 void fman_tgec_set_hash_table(struct tgec_regs *regs, uint32_t value);
436 uint32_t fman_tgec_get_event(struct tgec_regs *regs, uint32_t ev_mask);
438 void fman_tgec_ack_event(struct tgec_regs *regs, uint32_t ev_mask);
440 uint32_t fman_tgec_get_interrupt_mask(struct tgec_regs *regs);
453 void fman_tgec_enable_interrupt(struct tgec_regs *regs, uint32_t ev_mask);
455 void fman_tgec_disable_interrupt(struct tgec_regs *regs, uint32_t ev_mask);
459 void fman_tgec_set_hash_table_entry(struct tgec_regs *regs, uint32_t crc);