Lines Matching refs:OP_AddImm
17135 #define OP_AddImm 86 /* synopsis: r[P1]=r[P1]+P2 */ macro
96395 case OP_AddImm: { /* in1 */
115604 sqlite3VdbeAddOp2(v, OP_AddImm, target, 0);
118205 sqlite3VdbeAddOp2(v, OP_AddImm, r1, -2);
129885 sqlite3VdbeAddOp2(v, OP_AddImm, memCnt, 1);
135293 /* 6 */ {OP_AddImm, 0, 0, 0},
136412 sqlite3VdbeAddOp2(v, OP_AddImm, regRowCount, 1);
137152 sqlite3VdbeAddOp2(v, OP_AddImm, regTrigCnt, 1); /* incr trigger cnt */
137433 sqlite3VdbeAddOp2(v, OP_AddImm, regTrigCnt, 1); /* incr trigger cnt */
141515 sqlite3VdbeAddOp2(v, OP_AddImm, 1, -1);
142509 loopTop = sqlite3VdbeAddOp2(v, OP_AddImm, 7, 1);
142720 sqlite3VdbeAddOp2(v, OP_AddImm, 8+j, 1);/* increment entry count */
142838 { OP_AddImm, 1, 0, 0}, /* 0 */
146621 sqlite3VdbeAddOp2(v, OP_AddImm, p->iLimit, -1);
156549 sqlite3VdbeAddOp2(v, OP_AddImm, regRowCount, 1);
173863 sqlite3VdbeAddOp2(v, OP_AddImm, pWin->regApp+1, 1);
173880 sqlite3VdbeAddOp2(v, OP_AddImm, pWin->regApp+1-bInverse, 1);
174127 sqlite3VdbeAddOp2(v, OP_AddImm, tmpReg, val);
174481 sqlite3VdbeAddOp2(v, OP_AddImm, pMWin->regStartRowid, 1);
174493 sqlite3VdbeAddOp2(v, OP_AddImm, pMWin->regEndRowid, 1);