92                                          SmallVectorImpl<MachineOperand> &Cond,  in analyzeBranch()  argument
110       Cond.push_back(MachineOperand::CreateImm(true));  in analyzeBranch()
111       Cond.push_back(MI.getOperand(1));  in analyzeBranch()
118       Cond.push_back(MachineOperand::CreateImm(false));  in analyzeBranch()
119       Cond.push_back(MI.getOperand(1));  in analyzeBranch()
161     ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {  in insertBranch()  argument
164   if (Cond.empty()) {  in insertBranch()
172   assert(Cond.size() == 2 && "Expected a flag and a successor block");  in insertBranch()
174   if (Cond[0].getImm())  in insertBranch()
175     BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).add(Cond[1]);  in insertBranch()
177     BuildMI(&MBB, DL, get(WebAssembly::BR_UNLESS)).addMBB(TBB).add(Cond[1]);  in insertBranch()
186     SmallVectorImpl<MachineOperand> &Cond) const {  in reverseBranchCondition()
187   assert(Cond.size() == 2 && "Expected a flag and a condition expression");  in reverseBranchCondition()
188   Cond.front() = MachineOperand::CreateImm(!Cond.front().getImm());  in reverseBranchCondition()