32   if (SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||  in getRC32()
33       MO.getSubReg() == SystemZ::subreg_ll32 ||  in getRC32()
34       MO.getSubReg() == SystemZ::subreg_l32)  in getRC32()
35     return &SystemZ::GR32BitRegClass;  in getRC32()
36   if (SystemZ::GRH32BitRegClass.hasSubClassEq(RC) ||  in getRC32()
37       MO.getSubReg() == SystemZ::subreg_lh32 ||  in getRC32()
38       MO.getSubReg() == SystemZ::subreg_h32)  in getRC32()
39     return &SystemZ::GRH32BitRegClass;  in getRC32()
43     if (SystemZ::GR32BitRegClass.contains(PhysReg))  in getRC32()
44       return &SystemZ::GR32BitRegClass;  in getRC32()
45     assert (SystemZ::GRH32BitRegClass.contains(PhysReg) &&  in getRC32()
47     return &SystemZ::GRH32BitRegClass;  in getRC32()
50   assert (RC == &SystemZ::GRX32BitRegClass);  in getRC32()
89       if (SystemZ::getTwoOperandOpcode(Use.getOpcode()) != -1) {  in getRegAllocationHints()
131   if (MRI->getRegClass(VirtReg) == &SystemZ::GRX32BitRegClass) {  in getRegAllocationHints()
145         if (Use.getOpcode() == SystemZ::LOCRMux ||  in getRegAllocationHints()
146             Use.getOpcode() == SystemZ::SELRMux) {  in getRegAllocationHints()
152           if (Use.getOpcode() == SystemZ::SELRMux)  in getRegAllocationHints()
155           if (RC && RC != &SystemZ::GRX32BitRegClass) {  in getRegAllocationHints()
166           if (MRI->getRegClass(OtherReg) == &SystemZ::GRX32BitRegClass)  in getRegAllocationHints()
169         else if (Use.getOpcode() == SystemZ::CHIMux ||  in getRegAllocationHints()
170                  Use.getOpcode() == SystemZ::CFIMux) {  in getRegAllocationHints()
174               if (DefMI.getOpcode() != SystemZ::LMux)  in getRegAllocationHints()
177               addHints(Order, Hints, &SystemZ::GR32BitRegClass, MRI);  in getRegAllocationHints()
275   Reserved.set(SystemZ::A0);  in getReservedRegs()
276   Reserved.set(SystemZ::A1);  in getReservedRegs()
279   Reserved.set(SystemZ::FPC);  in getReservedRegs()
324     if (OpcodeForOffset == SystemZ::LE &&  in eliminateFrameIndex()
327       OpcodeForOffset = SystemZ::LDE32;  in eliminateFrameIndex()
344         MF.getRegInfo().createVirtualRegister(&SystemZ::ADDR64BitRegClass);  in eliminateFrameIndex()
357       unsigned LAOpcode = TII->getOpcodeForOffset(SystemZ::LA, HighOffset);  in eliminateFrameIndex()
365         BuildMI(MBB, MI, DL, TII->get(SystemZ::LA), ScratchReg)  in eliminateFrameIndex()
389   if (!(NewRC->hasSuperClassEq(&SystemZ::GR128BitRegClass) &&  in shouldCoalesce()
443   if (RC == &SystemZ::CCRRegClass)  in getCrossCopyRegClass()
444     return &SystemZ::GR32BitRegClass;  in getCrossCopyRegClass()