Target/AMDGPU/SIMemoryLegalizer.cpp

223   void reportUnsupported(const MachineBasicBlock::iterator &MI,
239   constructFromMIWithMMO(const MachineBasicBlock::iterator &MI) const;
248   getLoadInfo(const MachineBasicBlock::iterator &MI) const;
253   getStoreInfo(const MachineBasicBlock::iterator &MI) const;
258   getAtomicFenceInfo(const MachineBasicBlock::iterator &MI) const;
263   getAtomicCmpxchgOrRmwInfo(const MachineBasicBlock::iterator &MI) const;
284   bool enableNamedBit(const MachineBasicBlock::iterator MI,
295   virtual bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI,
302   virtual bool enableStoreCacheBypass(const MachineBasicBlock::iterator &MI,
309   virtual bool enableRMWCacheBypass(const MachineBasicBlock::iterator &MI,
316   virtual bool enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator &MI,
322   virtual bool expandSystemScopeStore(MachineBasicBlock::iterator &MI) const {  in expandSystemScopeStore()
333   virtual bool insertWait(MachineBasicBlock::iterator &MI,
345   virtual bool insertAcquire(MachineBasicBlock::iterator &MI,
356   virtual bool insertRelease(MachineBasicBlock::iterator &MI,
366                                    MachineBasicBlock::iterator &MI) const {  in tryForceStoreSC0SC1()
376   bool enableGLCBit(const MachineBasicBlock::iterator &MI) const {  in enableGLCBit()
382   bool enableSLCBit(const MachineBasicBlock::iterator &MI) const {  in enableSLCBit()
390   bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI,
394   bool enableStoreCacheBypass(const MachineBasicBlock::iterator &MI,
398   bool enableRMWCacheBypass(const MachineBasicBlock::iterator &MI,
402   bool enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator &MI,
407   bool insertWait(MachineBasicBlock::iterator &MI,
414   bool insertAcquire(MachineBasicBlock::iterator &MI,
419   bool insertRelease(MachineBasicBlock::iterator &MI,
431   bool insertAcquire(MachineBasicBlock::iterator &MI,
443   bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI,
447   bool enableStoreCacheBypass(const MachineBasicBlock::iterator &MI,
451   bool enableRMWCacheBypass(const MachineBasicBlock::iterator &MI,
455   bool enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator &MI,
460   bool insertWait(MachineBasicBlock::iterator &MI,
467   bool insertAcquire(MachineBasicBlock::iterator &MI,
472   bool insertRelease(MachineBasicBlock::iterator &MI,
484   bool enableSC0Bit(const MachineBasicBlock::iterator &MI) const {  in enableSC0Bit()
490   bool enableSC1Bit(const MachineBasicBlock::iterator &MI) const {  in enableSC1Bit()
496   bool enableNTBit(const MachineBasicBlock::iterator &MI) const {  in enableNTBit()
504   bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI,
508   bool enableStoreCacheBypass(const MachineBasicBlock::iterator &MI,
512   bool enableRMWCacheBypass(const MachineBasicBlock::iterator &MI,
516   bool enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator &MI,
521   bool insertAcquire(MachineBasicBlock::iterator &MI, SIAtomicScope Scope,
524   bool insertRelease(MachineBasicBlock::iterator &MI, SIAtomicScope Scope,
529                            MachineBasicBlock::iterator &MI) const override {  in tryForceStoreSC0SC1()
548   bool enableDLCBit(const MachineBasicBlock::iterator &MI) const {  in enableDLCBit()
556   bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI,
560   bool enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator &MI,
565   bool insertWait(MachineBasicBlock::iterator &MI,
572   bool insertAcquire(MachineBasicBlock::iterator &MI,
582   bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI,
586   bool enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator &MI,
596   bool setTH(const MachineBasicBlock::iterator MI,
600   bool setScope(const MachineBasicBlock::iterator MI,
610   insertWaitsBeforeSystemScopeStore(const MachineBasicBlock::iterator MI) const;
612   bool setAtomicScope(const MachineBasicBlock::iterator &MI,
618   bool insertWait(MachineBasicBlock::iterator &MI, SIAtomicScope Scope,
622   bool insertAcquire(MachineBasicBlock::iterator &MI, SIAtomicScope Scope,
625   bool enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator &MI,
630   bool expandSystemScopeStore(MachineBasicBlock::iterator &MI) const override;
632   bool insertRelease(MachineBasicBlock::iterator &MI, SIAtomicScope Scope,
636   bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI,  in enableLoadCacheBypass()
642   bool enableStoreCacheBypass(const MachineBasicBlock::iterator &MI,  in enableStoreCacheBypass()
648   bool enableRMWCacheBypass(const MachineBasicBlock::iterator &MI,  in enableRMWCacheBypass()
662   std::list<MachineBasicBlock::iterator> AtomicPseudoMIs;
677                   MachineBasicBlock::iterator &MI);
681                    MachineBasicBlock::iterator &MI);
685                          MachineBasicBlock::iterator &MI);
689                                 MachineBasicBlock::iterator &MI);
753 void SIMemOpAccess::reportUnsupported(const MachineBasicBlock::iterator &MI,  in reportUnsupported()
813     const MachineBasicBlock::iterator &MI) const {  in constructFromMIWithMMO()
875 SIMemOpAccess::getLoadInfo(const MachineBasicBlock::iterator &MI) const {  in getLoadInfo()
889 SIMemOpAccess::getStoreInfo(const MachineBasicBlock::iterator &MI) const {  in getStoreInfo()
903 SIMemOpAccess::getAtomicFenceInfo(const MachineBasicBlock::iterator &MI) const {  in getAtomicFenceInfo()
936     const MachineBasicBlock::iterator &MI) const {  in getAtomicCmpxchgOrRmwInfo()
955 bool SICacheControl::enableNamedBit(const MachineBasicBlock::iterator MI,  in enableNamedBit()
984     const MachineBasicBlock::iterator &MI,  in enableLoadCacheBypass()
1019     const MachineBasicBlock::iterator &MI,  in enableStoreCacheBypass()
1032     const MachineBasicBlock::iterator &MI,  in enableRMWCacheBypass()
1047     MachineBasicBlock::iterator &MI, SIAtomicAddrSpace AddrSpace, SIMemOp Op,  in enableVolatileAndOrNonTemporal()
1091 bool SIGfx6CacheControl::insertWait(MachineBasicBlock::iterator &MI,  in insertWait()
1189 bool SIGfx6CacheControl::insertAcquire(MachineBasicBlock::iterator &MI,  in insertAcquire()
1234 bool SIGfx6CacheControl::insertRelease(MachineBasicBlock::iterator &MI,  in insertRelease()
1243 bool SIGfx7CacheControl::insertAcquire(MachineBasicBlock::iterator &MI,  in insertAcquire()
1295     const MachineBasicBlock::iterator &MI,  in enableLoadCacheBypass()
1337     const MachineBasicBlock::iterator &MI,  in enableStoreCacheBypass()
1372     const MachineBasicBlock::iterator &MI,  in enableRMWCacheBypass()
1400     MachineBasicBlock::iterator &MI, SIAtomicAddrSpace AddrSpace, SIMemOp Op,  in enableVolatileAndOrNonTemporal()
1444 bool SIGfx90ACacheControl::insertWait(MachineBasicBlock::iterator &MI,  in insertWait()
1472 bool SIGfx90ACacheControl::insertAcquire(MachineBasicBlock::iterator &MI,  in insertAcquire()
1538 bool SIGfx90ACacheControl::insertRelease(MachineBasicBlock::iterator &MI,  in insertRelease()
1589     const MachineBasicBlock::iterator &MI, SIAtomicScope Scope,  in enableLoadCacheBypass()
1633     const MachineBasicBlock::iterator &MI,  in enableStoreCacheBypass()
1673     const MachineBasicBlock::iterator &MI, SIAtomicScope Scope,  in enableRMWCacheBypass()
1702     MachineBasicBlock::iterator &MI, SIAtomicAddrSpace AddrSpace, SIMemOp Op,  in enableVolatileAndOrNonTemporal()
1741 bool SIGfx940CacheControl::insertAcquire(MachineBasicBlock::iterator &MI,  in insertAcquire()
1827 bool SIGfx940CacheControl::insertRelease(MachineBasicBlock::iterator &MI,  in insertRelease()
1891     const MachineBasicBlock::iterator &MI,  in enableLoadCacheBypass()
1934     MachineBasicBlock::iterator &MI, SIAtomicAddrSpace AddrSpace, SIMemOp Op,  in enableVolatileAndOrNonTemporal()
1984 bool SIGfx10CacheControl::insertWait(MachineBasicBlock::iterator &MI,  in insertWait()
2105 bool SIGfx10CacheControl::insertAcquire(MachineBasicBlock::iterator &MI,  in insertAcquire()
2164     const MachineBasicBlock::iterator &MI, SIAtomicScope Scope,  in enableLoadCacheBypass()
2205     MachineBasicBlock::iterator &MI, SIAtomicAddrSpace AddrSpace, SIMemOp Op,  in enableVolatileAndOrNonTemporal()
2258 bool SIGfx12CacheControl::setTH(const MachineBasicBlock::iterator MI,  in setTH()
2273 bool SIGfx12CacheControl::setScope(const MachineBasicBlock::iterator MI,  in setScope()
2289     const MachineBasicBlock::iterator MI) const {  in insertWaitsBeforeSystemScopeStore()
2304 bool SIGfx12CacheControl::insertWait(MachineBasicBlock::iterator &MI,  in insertWait()
2400 bool SIGfx12CacheControl::insertAcquire(MachineBasicBlock::iterator &MI,  in insertAcquire()
2456 bool SIGfx12CacheControl::insertRelease(MachineBasicBlock::iterator &MI,  in insertRelease()
2523     MachineBasicBlock::iterator &MI, SIAtomicAddrSpace AddrSpace, SIMemOp Op,  in enableVolatileAndOrNonTemporal()
2564     MachineBasicBlock::iterator &MI) const {  in expandSystemScopeStore()
2572 bool SIGfx12CacheControl::setAtomicScope(const MachineBasicBlock::iterator &MI,  in setAtomicScope()
2622                                    MachineBasicBlock::iterator &MI) {  in expandLoad()
2668                                     MachineBasicBlock::iterator &MI) {  in expandStore()
2705                                           MachineBasicBlock::iterator &MI) {  in expandAtomicFence()
2755   MachineBasicBlock::iterator &MI) {  in expandAtomicCmpxchgOrRmw()