202   const GCNSubtarget *STM = nullptr;  member in __anon7062d5540111::SILoadStoreOptimizer
790     EltSize = AMDGPU::convertSMRDOffsetUnits(*LSO.STM, 4);  in setMI()
1120 bool SILoadStoreOptimizer::widthsFit(const GCNSubtarget &STM,  in widthsFit()  argument
1126     return (Width <= 4) && (STM.hasDwordx3LoadStores() || (Width != 3));  in widthsFit()
1138       return STM.hasScalarDwordx3Loads();  in widthsFit()
1184     if (!widthsFit(*STM, CI, Paired) || !offsetsCanBeCombined(CI, *STM, Paired))  in checkAndPrepareMerge()
1214     offsetsCanBeCombined(CI, *STM, Paired, true);  in checkAndPrepareMerge()
1276   if (STM->ldsRequiresM0Init())  in read2Opcode()
1282   if (STM->ldsRequiresM0Init())  in read2ST64Opcode()
1349   if (STM->ldsRequiresM0Init())  in write2Opcode()
1356   if (STM->ldsRequiresM0Init())  in write2ST64Opcode()
1561       getBufferFormatWithCompCount(CI.Format, CI.Width + Paired.Width, *STM);  in mergeTBufferLoadPair()
1604       getBufferFormatWithCompCount(CI.Format, CI.Width + Paired.Width, *STM);  in mergeTBufferStorePair()
1730         STM->isXNACKEnabled() && MMO->getAlign().value() < Width * 4;  in getNewOpcode()
2087   if (!STM->hasFlatInstOffsets() || !SIInstrInfo::isFLAT(MI))  in promoteConstantOffsetToImm()
2160     static_cast<const SITargetLowering *>(STM->getTargetLowering());  in promoteConstantOffsetToImm()
2466   STM = &MF.getSubtarget<GCNSubtarget>();  in runOnMachineFunction()
2467   if (!STM->loadStoreOptEnabled())  in runOnMachineFunction()
2470   TII = STM->getInstrInfo();  in runOnMachineFunction()