548   Register ScratchRsrcReg = MFI->getScratchRSrcReg();  in getEntryFunctionReservedScratchRsrcReg()  local
550   if (!ScratchRsrcReg || (!MRI.isPhysRegUsed(ScratchRsrcReg) &&  in getEntryFunctionReservedScratchRsrcReg()
555       ScratchRsrcReg != TRI->reservedPrivateSegmentBufferReg(MF))  in getEntryFunctionReservedScratchRsrcReg()
556     return ScratchRsrcReg;  in getEntryFunctionReservedScratchRsrcReg()
580       MRI.replaceRegWith(ScratchRsrcReg, Reg);  in getEntryFunctionReservedScratchRsrcReg()
587   return ScratchRsrcReg;  in getEntryFunctionReservedScratchRsrcReg()
628   Register ScratchRsrcReg;  in emitEntryFunctionPrologue()  local
630     ScratchRsrcReg = getEntryFunctionReservedScratchRsrcReg(MF);  in emitEntryFunctionPrologue()
633   if (ScratchRsrcReg) {  in emitEntryFunctionPrologue()
636         OtherBB.addLiveIn(ScratchRsrcReg);  in emitEntryFunctionPrologue()
647     if (ScratchRsrcReg && PreloadedScratchRsrcReg) {  in emitEntryFunctionPrologue()
667       TRI->isSubRegisterEq(ScratchRsrcReg, PreloadedScratchWaveOffsetReg)) {  in emitEntryFunctionPrologue()
675           !TRI->isSubRegisterEq(ScratchRsrcReg, Reg) && GITPtrLoReg != Reg) {  in emitEntryFunctionPrologue()
711   if ((NeedsFlatScratchInit || ScratchRsrcReg) &&  in emitEntryFunctionPrologue()
721   if (ScratchRsrcReg) {  in emitEntryFunctionPrologue()
724                                          ScratchRsrcReg, ScratchWaveOffsetReg);  in emitEntryFunctionPrologue()
732     Register ScratchRsrcReg, Register ScratchWaveOffsetReg) const {  in emitEntryFunctionScratchRsrcRegSetup()  argument
743     Register Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1);  in emitEntryFunctionScratchRsrcRegSetup()
744     Register Rsrc03 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3);  in emitEntryFunctionScratchRsrcRegSetup()
760     BuildMI(MBB, I, DL, LoadDwordX4, ScratchRsrcReg)  in emitEntryFunctionScratchRsrcRegSetup()
764       .addReg(ScratchRsrcReg, RegState::ImplicitDefine)  in emitEntryFunctionScratchRsrcRegSetup()
784     Register Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2);  in emitEntryFunctionScratchRsrcRegSetup()
785     Register Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3);  in emitEntryFunctionScratchRsrcRegSetup()
791       Register Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1);  in emitEntryFunctionScratchRsrcRegSetup()
798           .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchRsrcRegSetup()
813           .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchRsrcRegSetup()
819       Register Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);  in emitEntryFunctionScratchRsrcRegSetup()
820       Register Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);  in emitEntryFunctionScratchRsrcRegSetup()
824         .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchRsrcRegSetup()
828         .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchRsrcRegSetup()
833       .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchRsrcRegSetup()
837       .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchRsrcRegSetup()
841     if (ScratchRsrcReg != PreloadedScratchRsrcReg) {  in emitEntryFunctionScratchRsrcRegSetup()
842       BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), ScratchRsrcReg)  in emitEntryFunctionScratchRsrcRegSetup()
856   Register ScratchRsrcSub0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);  in emitEntryFunctionScratchRsrcRegSetup()
857   Register ScratchRsrcSub1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);  in emitEntryFunctionScratchRsrcRegSetup()
864       .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchRsrcRegSetup()
868       .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchRsrcRegSetup()