Lines Matching +full:mii +full:- +full:rt
1 //===- AMDGPUAsmParser.cpp - Parse SI asm to MCInst instructions ----------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
55 //===----------------------------------------------------------------------===//
57 //===----------------------------------------------------------------------===//
464 // TODO: Find out how SALU supports extension of 32-bit literals to 64 bits. in isSSrc_b64()
1066 // clang-format off in printImmTy()
1130 // clang-format on in printImmTy()
1159 Op->Imm.Val = Val; in CreateImm()
1160 Op->Imm.IsFPImm = IsFPImm; in CreateImm()
1161 Op->Imm.Kind = ImmKindTyNone; in CreateImm()
1162 Op->Imm.Type = Type; in CreateImm()
1163 Op->Imm.Mods = Modifiers(); in CreateImm()
1164 Op->StartLoc = Loc; in CreateImm()
1165 Op->EndLoc = Loc; in CreateImm()
1173 Res->Tok.Data = Str.data(); in CreateToken()
1174 Res->Tok.Length = Str.size(); in CreateToken()
1175 Res->StartLoc = Loc; in CreateToken()
1176 Res->EndLoc = Loc; in CreateToken()
1184 Op->Reg.RegNo = RegNo; in CreateReg()
1185 Op->Reg.Mods = Modifiers(); in CreateReg()
1186 Op->StartLoc = S; in CreateReg()
1187 Op->EndLoc = E; in CreateReg()
1194 Op->Expr = Expr; in CreateExpr()
1195 Op->StartLoc = S; in CreateExpr()
1196 Op->EndLoc = S; in CreateExpr()
1206 //===----------------------------------------------------------------------===//
1208 //===----------------------------------------------------------------------===//
1214 int SgprIndexUnusedMin = -1;
1215 int VgprIndexUnusedMin = -1;
1216 int AgprIndexUnusedMin = -1;
1225 Ctx->getOrCreateSymbol(Twine(".kernel.sgpr_count")); in usesSgprAt()
1226 Sym->setVariableValue(MCConstantExpr::create(SgprIndexUnusedMin, *Ctx)); in usesSgprAt()
1236 Ctx->getOrCreateSymbol(Twine(".kernel.vgpr_count")); in usesVgprAt()
1239 Sym->setVariableValue(MCConstantExpr::create(totalVGPR, *Ctx)); in usesVgprAt()
1253 Ctx->getOrCreateSymbol(Twine(".kernel.agpr_count")); in usesAgprAt()
1254 Sym->setVariableValue(MCConstantExpr::create(AgprIndexUnusedMin, *Ctx)); in usesAgprAt()
1258 Ctx->getOrCreateSymbol(Twine(".kernel.vgpr_count")); in usesAgprAt()
1261 vSym->setVariableValue(MCConstantExpr::create(totalVGPR, *Ctx)); in usesAgprAt()
1271 MSTI = Ctx->getSubtargetInfo(); in initialize()
1273 usesSgprAt(SgprIndexUnusedMin = -1); in initialize()
1274 usesVgprAt(VgprIndexUnusedMin = -1); in initialize()
1276 usesAgprAt(AgprIndexUnusedMin = -1); in initialize()
1284 usesSgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1); in usesRegister()
1287 usesAgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1); in usesRegister()
1290 usesVgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1); in usesRegister()
1306 /// @name Auto-generated Match Functions
1320 /// registers, and user-specified NextFreeXGPR values.
1399 const MCInstrInfo &MII, in AMDGPUAsmParser() argument
1401 : MCTargetAsmParser(Options, STI, MII), Parser(_Parser) { in AMDGPUAsmParser()
1406 copySTI().ToggleFeature("southern-islands"); in AMDGPUAsmParser()
1555 return const_cast<AMDGPUAsmParser*>(this)->getContext().getRegisterInfo(); in getMRI()
1559 return &MII; in getMII()
1704 return Error(Parser, "only " + Twine(Width) + "-bit values are legal"); in validate()
1919 // When floating-point immediate is used as operand of type i16, the 32-bit in getOpFltSemantics()
1969 //===----------------------------------------------------------------------===//
1971 //===----------------------------------------------------------------------===//
2010 // shared_base with both 32-bit and 64-bit operands. in isInlinableImm()
2012 // 32-bit operands only. in isInlinableImm()
2028 if (type == MVT::f64 || type == MVT::i64) { // Expected 64-bit operand in isInlinableImm()
2030 AsmParser->hasInv2PiInlineImm()); in isInlinableImm()
2041 llvm_unreachable("unknown 16-bit type"); in isInlinableImm()
2055 // We need to use 32-bit representation here because when a floating-point in isInlinableImm()
2056 // inline constant is used as an i16 operand, its 32-bit representation in isInlinableImm()
2057 // representation will be used. We will need the 32-bit value to check if in isInlinableImm()
2061 AsmParser->hasInv2PiInlineImm()); in isInlinableImm()
2067 AsmParser->hasInv2PiInlineImm()); in isInlinableImm()
2071 if (type == MVT::f64 || type == MVT::i64) { // Expected 64-bit operand in isInlinableImm()
2073 AsmParser->hasInv2PiInlineImm()); in isInlinableImm()
2083 type, AsmParser->hasInv2PiInlineImm()); in isInlinableImm()
2088 AsmParser->hasInv2PiInlineImm()); in isInlinableImm()
2111 // FIXME: 64-bit operands can zero extend, sign extend, or pad zeroes for FP in isLiteralImm()
2117 if (type == MVT::f64) { // Expected 64-bit fp operand in isLiteralImm()
2118 // We would set low 64-bits of literal to zeroes but we accept this literals in isLiteralImm()
2122 if (type == MVT::i64) { // Expected 64-bit int operand in isLiteralImm()
2123 // We don't allow fp literals in 64-bit integer instructions. It is in isLiteralImm()
2133 // single-precision float. This is pretty odd, but it matches SP3 and what in isLiteralImm()
2145 return isRegKind() && AsmParser->getMRI()->getRegClass(RCID).contains(getReg()); in isRegClass()
2150 // GFX90A allows DPP on 64-bit operands. in isVRegWithInputMods()
2152 AsmParser->getFeatureBits()[AMDGPU::FeatureDPALU_DPP]); in isVRegWithInputMods()
2161 if (AsmParser->isVI()) in isSDWAOperand()
2163 if (AsmParser->isGFX9Plus()) in isSDWAOperand()
2185 auto FB = AsmParser->getFeatureBits(); in isBoolReg()
2195 const uint64_t FpSignMask = (1ULL << (Size * 8 - 1)); in applyInputFPModifiers()
2213 if (AMDGPU::isSISrcOperand(AsmParser->getMII()->get(Inst.getOpcode()), in addImmOperands()
2226 const auto& InstDesc = AsmParser->getMII()->get(Inst.getOpcode()); in addLiteralImmOperand()
2248 AsmParser->hasInv2PiInlineImm())) { in addLiteralImmOperand()
2254 // Non-inlineable in addLiteralImmOperand()
2255 if (AMDGPU::isSISrcFPOperand(InstDesc, OpNum)) { // Expected 64-bit fp operand in addLiteralImmOperand()
2258 const_cast<AMDGPUAsmParser *>(AsmParser)->Warning(Inst.getLoc(), in addLiteralImmOperand()
2259 "Can't encode literal as exact 64-bit floating-point operand. " in addLiteralImmOperand()
2260 "Low 32-bits will be set to zero"); in addLiteralImmOperand()
2269 // We don't allow fp literals in 64-bit integer instructions. It is in addLiteralImmOperand()
2272 llvm_unreachable("fp literal in 64-bit integer instruction."); in addLiteralImmOperand()
2281 if (AsmParser->hasInv2PiInlineImm() && Literal == 0x3fc45f306725feed) { in addLiteralImmOperand()
2363 AsmParser->hasInv2PiInlineImm())) { in addLiteralImmOperand()
2378 if (AMDGPU::isInlinableLiteral64(Val, AsmParser->hasInv2PiInlineImm())) { in addLiteralImmOperand()
2411 AsmParser->hasInv2PiInlineImm())) { in addLiteralImmOperand()
2427 AsmParser->hasInv2PiInlineImm())) { in addLiteralImmOperand()
2448 AsmParser->hasInv2PiInlineImm())); in addLiteralImmOperand()
2458 AsmParser->hasInv2PiInlineImm())); in addLiteralImmOperand()
2478 Inst.addOperand(MCOperand::createReg(AMDGPU::getMCReg(getReg(), AsmParser->getSTI()))); in addRegOperands()
2485 //===----------------------------------------------------------------------===//
2487 //===----------------------------------------------------------------------===//
2490 // TODO: make those pre-defined variables read-only. in createConstantSymbol()
2491 // Currently there is none suitable machinery in the core llvm-mc for this. in createConstantSymbol()
2496 Sym->setVariableValue(MCConstantExpr::create(Val, Ctx)); in createConstantSymbol()
2502 default: return -1; in getRegClass()
2534 default: return -1; in getRegClass()
2548 default: return -1; in getRegClass()
2578 default: return -1; in getRegClass()
2609 return -1; in getRegClass()
2660 assert(R->isReg()); in ParseRegister()
2661 RegNo = R->getReg(); in ParseRegister()
2662 StartLoc = R->getStartLoc(); in ParseRegister()
2663 EndLoc = R->getEndLoc(); in ParseRegister()
2783 StringRef RegName = Reg->Name; in isRegister()
2827 if (RCID == -1) { in getRegularReg()
2833 const MCRegisterClass RC = TRI->getRegClass(RCID); in getRegularReg()
2842 Reg = TRI->getSubReg(Reg, SubReg); in getRegularReg()
2890 RegWidth = 32 * ((RegHi - RegLo) + 1); in ParseRegRange()
2925 RegKind = RI->Kind; in ParseRegularReg()
2926 StringRef RegSuffix = RegName.substr(RI->Name.size()); in ParseRegularReg()
2938 // Single 32-bit register: vXX. in ParseRegularReg()
2970 Error(Loc, "expected a single 32-bit register"); in ParseRegList()
2985 Error(Loc, "expected a single 32-bit register"); in ParseRegList()
3072 Sym->setVariableValue(MCConstantExpr::create(0, getContext())); in initializeGprCountSymbol()
3087 int64_t NewMax = DwordRegIndex + divideCeil(RegWidth, 32) - 1; in updateGprCountSymbols()
3090 if (!Sym->isVariable()) in updateGprCountSymbols()
3093 if (!Sym->getVariableValue(false)->evaluateAsAbsolute(OldCount)) in updateGprCountSymbols()
3099 Sym->setVariableValue(MCConstantExpr::create(NewMax + 1, getContext())); in updateGprCountSymbols()
3160 // Floating-point expressions are not supported. in parseImm()
3161 // Can only allow floating-point literals with an in parseImm()
3191 // |-1| in parseImm()
3203 if (Expr->evaluateAsAbsolute(IntVal)) { in parseImm()
3224 assert(R->isReg()); in parseReg()
3273 // -reg
3274 // -|...|
3275 // -abs(...)
3293 // 1. Before a register, e.g. "-v0", "-v[...]" or "-[v0,v1]".
3294 // 2. Before an 'abs' modifier: -abs(...)
3295 // 3. Before an SP3 'abs' modifier: -|...|
3297 // In all other cases "-" is handled as a part
3300 // Note: When "-" is followed by an integer literal,
3302 // than a floating-point NEG modifier applied to N.
3303 // Beside being contr-intuitive, such use of floating-point
3307 // v_exp_f32_e32 v5, -1 // VOP1: src0 = 0xFFFFFFFF
3308 // v_exp_f32_e64 v5, -1 // VOP3: src0 = 0x80000001
3309 // Negative fp literals with preceding "-" are
3337 // Disable ambiguous constructs like '--1' etc. Should use neg(-1) instead. in parseRegOrImmWithFPInputMods()
3372 if (Lit && !Operands.back()->isImm()) in parseRegOrImmWithFPInputMods()
3459 uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags; in checkTargetMatchPredicate()
3541 const MCInstrDesc &Desc = MII.get(Inst.getOpcode()); in findImplicitSGPRReadInVOP()
3563 const MCInstrDesc &Desc = MII.get(Inst.getOpcode()); in isInlineConstant()
3626 // 64-bit shift instructions can use only one scalar value input in getConstantBusLimit()
3658 AddMandatoryLiterals ? getNamedOperandIdx(Opcode, OpName::imm) : -1; in getSrcOperandIndices()
3663 : -1; in getSrcOperandIndices()
3695 // count as using the constant bus twice - but in this case it is allowed since
3712 const MCInstrDesc &Desc = MII.get(Opcode); in validateConstantBusLimitations()
3743 if (OpIdx == -1) in validateConstantBusLimitations()
3814 // On GFX12 if both OpX and OpY are V_MOV_B32 then OPY uses SRC2 source-cache. in validateVOPDRegBankConstraints()
3817 const auto &InstInfo = getVOPDInstInfo(Opcode, &MII); in validateVOPDRegBankConstraints()
3833 auto CompSrcIdx = CompOprIdx - VOPD::Component::DST_NUM; in validateVOPDRegBankConstraints()
3844 const MCInstrDesc &Desc = MII.get(Opc); in validateIntClampSupported()
3848 assert(ClampIdx != -1); in validateIntClampSupported()
3862 const MCInstrDesc &Desc = MII.get(Opc); in validateMIMGDataSize()
3871 if (VDataIdx == -1 && isGFX10Plus()) // no return image_sample in validateMIMGDataSize()
3874 if ((DMaskIdx == -1 || TFEIdx == -1) && isGFX10_AEncoding()) // intersect_ray in validateMIMGDataSize()
3878 unsigned TFESize = (TFEIdx != -1 && Inst.getOperand(TFEIdx).getImm()) ? 1 : 0; in validateMIMGDataSize()
3909 const MCInstrDesc &Desc = MII.get(Opc); in validateMIMGAddrSize()
3917 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); in validateMIMGAddrSize()
3925 assert(VAddr0Idx != -1); in validateMIMGAddrSize()
3926 assert(SrsrcIdx != -1); in validateMIMGAddrSize()
3929 bool IsA16 = (A16Idx != -1 && Inst.getOperand(A16Idx).getImm()); in validateMIMGAddrSize()
3930 if (BaseOpcode->BVH) { in validateMIMGAddrSize()
3931 if (IsA16 == BaseOpcode->A16) in validateMIMGAddrSize()
3939 bool IsNSA = SrsrcIdx - VAddr0Idx > 1; in validateMIMGAddrSize()
3941 IsNSA ? SrsrcIdx - VAddr0Idx in validateMIMGAddrSize()
3951 int VAddrLastIdx = SrsrcIdx - 1; in validateMIMGAddrSize()
3955 ActualAddrSize = VAddrLastIdx - VAddr0Idx + VAddrLastSize; in validateMIMGAddrSize()
3978 const MCInstrDesc &Desc = MII.get(Opc); in validateMIMGAtomicDMask()
3998 const MCInstrDesc &Desc = MII.get(Opc); in validateMIMGGatherDMask()
4016 const MCInstrDesc &Desc = MII.get(Opc); in validateMIMGMSAA()
4023 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); in validateMIMGMSAA()
4025 if (!BaseOpcode->MSAA) in validateMIMGMSAA()
4029 assert(DimIdx != -1); in validateMIMGMSAA()
4034 return DimInfo->MSAA; in validateMIMGMSAA()
4056 const MCInstrDesc &Desc = MII.get(Opc); in validateMovrels()
4062 assert(Src0Idx != -1); in validateMovrels()
4089 assert(Src0Idx != -1); in validateMAIAccWrite()
4109 const MCInstrDesc &Desc = MII.get(Opcode); in validateMAISrc2()
4116 if (Src2Idx == -1) in validateMAISrc2()
4131 const MCInstrDesc &Desc = MII.get(Opc); in validateMFMA()
4137 if (Src2Idx == -1) in validateMFMA()
4150 if (TRI->getRegClass(Desc.operands()[0].RegClass).getSizeInBits() <= 128) in validateMFMA()
4153 if (TRI->regsOverlap(Src2Reg, DstReg)) { in validateMFMA()
4193 const MCInstrDesc &Desc = MII.get(Opc); in validateMIMGD16()
4341 const MCInstrDesc &Desc = MII.get(Opcode); in validateLdsDirect()
4344 // with 9-bit operands only. Ignore encodings which do not accept these. in validateLdsDirect()
4351 if (SrcIdx == -1) in validateLdsDirect()
4383 if (OpNum == -1) in validateOffset()
4386 uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags; in validateOffset()
4399 Twine("expected a ") + Twine(OffsetSize) + "-bit signed offset"); in validateOffset()
4406 Twine("expected a ") + Twine(OffsetSize) + "-bit unsigned offset"); in validateOffset()
4415 uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags; in validateFlatOffset()
4421 assert(OpNum != -1); in validateFlatOffset()
4430 // For pre-GFX12 FLAT instructions the offset must be positive; in validateFlatOffset()
4439 (AllowNegative ? Twine(OffsetSize) + "-bit signed offset" in validateFlatOffset()
4440 : Twine(OffsetSize - 1) + "-bit unsigned offset")); in validateFlatOffset()
4462 uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags; in validateSMEMOffset()
4468 if (OpNum == -1) in validateSMEMOffset()
4482 isGFX12Plus() ? "expected a 24-bit signed offset" in validateSMEMOffset()
4483 : (isVI() || IsBuffer) ? "expected a 20-bit unsigned offset" in validateSMEMOffset()
4484 : "expected a 21-bit signed offset"); in validateSMEMOffset()
4491 const MCInstrDesc &Desc = MII.get(Opcode); in validateSOPLiteral()
4505 if (OpIdx == -1) break; in validateSOPLiteral()
4535 uint64_t TSFlags = MII.get(Opc).TSFlags; in validateOpSel()
4539 if (OpSelIdx != -1) { in validateOpSel()
4544 if (OpSelHiIdx != -1) { in validateOpSel()
4545 if (Inst.getOperand(OpSelHiIdx).getImm() != -1) in validateOpSel()
4566 uint64_t TSFlags = MII.get(Opc).TSFlags; in validateNeg()
4577 if (NegIdx == -1) in validateNeg()
4609 AMDGPU::isDPALU_DPP(MII.get(Opc))) { in validateDPP()
4653 const MCInstrDesc &Desc = MII.get(Opcode); in validateVOPLiteral()
4654 bool HasMandatoryLiteral = getNamedOperandIdx(Opcode, OpName::imm) != -1; in validateVOPLiteral()
4666 if (OpIdx == -1) in validateVOPLiteral()
4715 // Returns -1 if not a register, 0 if VGPR and 1 if AGPR.
4720 return -1; in IsAGPROperand()
4724 return -1; in IsAGPROperand()
4726 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); in IsAGPROperand()
4728 const MCRegisterClass &AGPR32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID); in IsAGPROperand()
4733 uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags; in validateAGPRLdSt()
4768 const MCRegisterClass &VGPR32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID); in validateVGPRAlign()
4769 const MCRegisterClass &AGPR32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID); in validateVGPRAlign()
4775 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); in validateVGPRAlign()
4779 if (VGPR32.contains(Sub) && ((Sub - AMDGPU::VGPR0) & 1)) in validateVGPRAlign()
4781 if (AGPR32.contains(Sub) && ((Sub - AMDGPU::AGPR0) & 1)) in validateVGPRAlign()
4801 if (BlgpIdx == -1) in validateBLGP()
4854 uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags; in validateDS()
4859 // Only validate GDS for non-GWS instructions. in validateDS()
4888 const MCRegisterClass &VGPR32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID); in validateGWS()
4891 assert(Data0Pos != -1); in validateGWS()
4893 auto RegIdx = Reg - (VGPR32.contains(Reg) ? AMDGPU::VGPR0 : AMDGPU::AGPR0); in validateGWS()
4908 if (CPolPos == -1) in validateCoherencyBits()
4916 uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags; in validateCoherencyBits()
4974 const MCInstrDesc &TID = MII.get(Opcode); in validateTHAndScopeBits()
5025 if (!Operand->isReg()) in validateExeczVcczOperands()
5027 unsigned Reg = Operand->getReg(); in validateExeczVcczOperands()
5039 const MCInstrDesc &Desc = MII.get(Inst.getOpcode()); in validateTFE()
5252 const auto &PrevOp = ((AMDGPUOperand &)*Operands[InvalidOprIdx - 1]); in isInvalidVOPDY()
5328 int64_t Tmp = -1; in ParseAsAbsoluteExpression()
5349 if (getTargetStreamer().getTargetID()->toString() != TargetIDDirective) in ParseDirectiveAMDGCNTarget()
5354 Twine(getTargetStreamer().getTargetID()->toString())).str()); in ParseDirectiveAMDGCNTarget()
5383 if (NumSGPRs->evaluateAsAbsolute(EvaluatedSGPRs) && Version.Major >= 8 && in calculateGPRBlocks()
5392 if (NumSGPRs->evaluateAsAbsolute(EvaluatedSGPRs) && in calculateGPRBlocks()
5403 // (alignTo(max(1u, NumGPR), GPREncodingGranule) / GPREncodingGranule) - 1 in calculateGPRBlocks()
5405 unsigned Granule) -> const MCExpr * { in calculateGPRBlocks()
5491 if ((EvaluatableExpr = ExprVal->evaluateAsAbsolute(IVal))) { in ParseDirectiveAMDHSAKernel()
5686 if (Val != getTargetStreamer().getTargetID()->isXnackOnOrAny()) in ParseDirectiveAMDHSAKernel()
5807 getTargetStreamer().getTargetID()->isXnackOnOrAny(), in ParseDirectiveAMDHSAKernel()
5815 VGPRBlocks->evaluateAsAbsolute(EvaluatedVGPRBlocks); in ParseDirectiveAMDHSAKernel()
5827 if (SGPRBlocks->evaluateAsAbsolute(EvaluatedSGPRBlocks) && in ParseDirectiveAMDHSAKernel()
5851 if (!KD.kernarg_size->evaluateAsAbsolute(IVal)) in ParseDirectiveAMDHSAKernel()
5863 bool AccumEvaluatable = AccumOffset->evaluateAsAbsolute(EvaluatedAccum); in ParseDirectiveAMDHSAKernel()
5871 if (NextFreeVGPR->evaluateAsAbsolute(EvaluatedNumVGPR) && in ParseDirectiveAMDHSAKernel()
6001 ".amd_amdgpu_isa directive is not available on non-amdgcn " in ParseDirectiveISAVersion()
6006 if (getTargetStreamer().getTargetID()->toString() != TargetIDDirective) in ParseDirectiveISAVersion()
6052 << getContext().getAsmInfo()->getSeparatorString(); in ParseToEndDirective()
6068 /// Parse the assembler directive for new MsgPack-format PAL metadata.
6076 if (!PALMetadata->setFromString(String)) in ParseDirectivePALMetadataBegin()
6081 /// Parse the assembler directive for old linear-format PAL metadata.
6086 "not available on non-amdpal OSes")).str()); in ParseDirectivePALMetadata()
6090 PALMetadata->setLegacy(); in ParseDirectivePALMetadata()
6105 PALMetadata->setRegister(Key, Value); in ParseDirectivePALMetadata()
6134 return Error(SizeLoc, "size must be non-negative"); in ParseDirectiveAMDGPULDS()
6148 // to make sure the alignment fits nicely into a 32-bit integer. in ParseDirectiveAMDGPULDS()
6156 Symbol->redefineIfPossible(); in ParseDirectiveAMDGPULDS()
6157 if (!Symbol->isUndefined()) in ParseDirectiveAMDGPULDS()
6190 "not available on non-amdhsa OSes")) in ParseDirective()
6242 return (isVI() || isGFX9()) && getTargetStreamer().getTargetID()->isXnackSupported(); in subtargetHasRegister()
6315 if (Operands.size() - Prefix > 1) { in parseOperand()
6336 return Name.substr(0, Name.size() - 8); in parseMnemonicSuffix()
6340 return Name.substr(0, Name.size() - 4); in parseMnemonicSuffix()
6344 return Name.substr(0, Name.size() - 4); in parseMnemonicSuffix()
6348 return Name.substr(0, Name.size() - 4); in parseMnemonicSuffix()
6352 return Name.substr(0, Name.size() - 5); in parseMnemonicSuffix()
6402 //===----------------------------------------------------------------------===//
6404 //===----------------------------------------------------------------------===//
6662 .Case("RT", AMDGPU::CPol::TH_RT) in parseTH()
6673 .Case("RT", AMDGPU::CPol::TH_RT) in parseTH()
6699 unsigned Idx = i->second; in addOptionalImmOperand()
6717 //===----------------------------------------------------------------------===//
6719 //===----------------------------------------------------------------------===//
6972 AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands[Size - 2]); in parseFORMAT()
7012 //===----------------------------------------------------------------------===//
7014 //===----------------------------------------------------------------------===//
7077 //===----------------------------------------------------------------------===//
7079 //===----------------------------------------------------------------------===//
7095 IntVal = encode(ISA, IntVal, -1); in encodeCnt()
7205 .Default(-1); in parseDelay()
7221 .Default(-1); in parseDelay()
7257 //===----------------------------------------------------------------------===//
7259 //===----------------------------------------------------------------------===//
7342 //===----------------------------------------------------------------------===//
7344 //===----------------------------------------------------------------------===//
7399 if (!isUIntN(Width, Val - 1)) in parseHwreg()
7423 return Error(Loc, "invalid immediate: only 16-bit values are legal"); in parseHwreg()
7433 //===----------------------------------------------------------------------===//
7435 //===----------------------------------------------------------------------===//
7541 return Error(Loc, "invalid immediate: only 16-bit values are legal"); in parseSendMsg()
7554 //===----------------------------------------------------------------------===//
7556 //===----------------------------------------------------------------------===//
7569 .Default(-1); in parseInterpSlot()
7571 if (Slot == -1) in parseInterpSlot()
7595 .Default(-1); in parseInterpAttr()
7596 if (AttrChan == -1) in parseInterpAttr()
7617 //===----------------------------------------------------------------------===//
7619 //===----------------------------------------------------------------------===//
7641 //===----------------------------------------------------------------------===//
7643 //===----------------------------------------------------------------------===//
7722 if (Expr->evaluateAsAbsolute(Imm)) in parseExpr()
7743 if (Expr->evaluateAsAbsolute(IntVal)) { in parseExpr()
7820 for (unsigned i = Operands.size() - 1; i > 0; --i) { in getOperandLoc()
7888 find_if(Fields, [Id](StructuredOpField *F) { return F->Id == Id; }); in parseStructuredOpFields()
7891 if ((*I)->IsDefined) in parseStructuredOpFields()
7895 (*I)->Loc = getLoc(); in parseStructuredOpFields()
7896 if (!parseExpr((*I)->Val)) in parseStructuredOpFields()
7898 (*I)->IsDefined = true; in parseStructuredOpFields()
7908 return F->validate(*this); in validateStructuredOpFields()
7912 //===----------------------------------------------------------------------===//
7914 //===----------------------------------------------------------------------===//
7970 "expected a 2-bit lane id")) { in parseSwizzleQuadPerm()
7999 0, GroupSize - 1, in parseSwizzleBroadcast()
8000 "lane id must be in the interval [0,group size - 1]", in parseSwizzleBroadcast()
8002 Imm = encodeBitmaskPerm(BITMASK_MAX - GroupSize + 1, LaneIdx, 0); in parseSwizzleBroadcast()
8026 Imm = encodeBitmaskPerm(BITMASK_MAX, 0, GroupSize - 1); in parseSwizzleReverse()
8066 Error(StrLoc, "expected a 5-character mask"); in parseSwizzleBitmaskPerm()
8075 unsigned Mask = 1 << (BITMASK_WIDTH - 1 - i); in parseSwizzleBitmaskPerm()
8108 Error(OffsetLoc, "expected a 16-bit offset"); in parseSwizzleOffset()
8170 //===----------------------------------------------------------------------===//
8172 //===----------------------------------------------------------------------===//
8233 return Error(S, "invalid immediate: only 4-bit values are legal"); in parseGPRIdxMode()
8245 //===----------------------------------------------------------------------===//
8247 //===----------------------------------------------------------------------===//
8260 AMDGPUOperand &Opr = ((AMDGPUOperand &)*Operands[Operands.size() - 1]); in parseSOPPBrTarget()
8269 Error(Loc, "expected a 16-bit signed jump offset"); in parseSOPPBrTarget()
8275 //===----------------------------------------------------------------------===//
8277 //===----------------------------------------------------------------------===//
8283 //===----------------------------------------------------------------------===//
8285 //===----------------------------------------------------------------------===//
8295 IsAtomicReturn = MII.get(Inst.getOpcode()).TSFlags & in cvtMubufImpl()
8319 // Handle tokens like 'offen' which are sometimes hard-coded into the in cvtMubufImpl()
8334 //===----------------------------------------------------------------------===//
8336 //===----------------------------------------------------------------------===//
8348 // 32-bit literals are only supported on CI and we only want to use them in isSMRDLiteralOffset()
8349 // when the offset is > 8-bits. in isSMRDLiteralOffset()
8353 //===----------------------------------------------------------------------===//
8355 //===----------------------------------------------------------------------===//
8379 // For pre-gfx11 targets, both bound_ctrl:0 and bound_ctrl:1 are encoded as 1.
8481 if (OpSelIdx == -1) in cvtVOP3DstOpSelOnly()
8496 if (DstIdx == -1) in cvtVOP3DstOpSelOnly()
8532 && Desc.operands()[OpNum + 1].RegClass != -1 in isRegOrImmWithInputMods()
8535 MCOI::OperandConstraint::TIED_TO) == -1; in isRegOrImmWithInputMods()
8544 const MCInstrDesc &Desc = MII.get(Inst.getOpcode()); in cvtVOP3Interp()
8582 const MCInstrDesc &Desc = MII.get(Inst.getOpcode()); in cvtVINTERP()
8601 if (OpSelIdx != -1) in cvtVINTERP()
8606 if (OpSelIdx == -1) in cvtVINTERP()
8620 if (OpIdx == -1) in cvtVINTERP()
8641 const MCInstrDesc &Desc = MII.get(Inst.getOpcode()); in cvtVOP3()
8696 const MCInstrDesc &Desc = MII.get(Opc); in cvtVOP3P()
8727 if (OpSelIdx != -1) { in cvtVOP3P()
8732 if (OpSelHiIdx != -1) { in cvtVOP3P()
8733 int DefaultVal = IsPacked ? -1 : 0; in cvtVOP3P()
8739 if (NegLoIdx != -1) in cvtVOP3P()
8743 if (NegHiIdx != -1) in cvtVOP3P()
8758 if (OpSelIdx != -1) in cvtVOP3P()
8761 if (OpSelHiIdx != -1) in cvtVOP3P()
8764 if (NegLoIdx != -1) in cvtVOP3P()
8767 if (NegHiIdx != -1) in cvtVOP3P()
8772 if (OpIdx == -1) in cvtVOP3P()
8777 if (ModIdx == -1) in cvtVOP3P()
8784 ->getRegClass(AMDGPU::VGPR_16RegClassID) in cvtVOP3P()
8815 if (AMDGPU::getNamedOperandIdx(Opc, OpName) != -1) in addSrcModifiersAndSrc()
8850 //===----------------------------------------------------------------------===//
8852 //===----------------------------------------------------------------------===//
8889 const auto &InstInfo = getVOPDInstInfo(Inst.getOpcode(), &MII); in cvtVOPD()
8908 //===----------------------------------------------------------------------===//
8910 //===----------------------------------------------------------------------===//
8940 //===----------------------------------------------------------------------===//
8942 //===----------------------------------------------------------------------===//
8956 //===----------------------------------------------------------------------===//
8958 //===----------------------------------------------------------------------===//
8985 Encoding = DimInfo->Encoding; in parseDimId()
9008 //===----------------------------------------------------------------------===//
9010 //===----------------------------------------------------------------------===//
9033 return Error(Loc, "expected a 3-bit value"); in parseDPP8()
9077 return -1; in parseDPPCtrlPerm()
9082 return -1; in parseDPPCtrlPerm()
9087 return -1; in parseDPPCtrlPerm()
9089 Error(Loc, "expected a 2-bit value"); in parseDPPCtrlPerm()
9090 return -1; in parseDPPCtrlPerm()
9097 return -1; in parseDPPCtrlPerm()
9112 return -1; in parseDPPCtrlSel()
9131 .Default({-1, 0, 0}); in parseDPPCtrlSel()
9134 if (Check.Ctrl == -1) { in parseDPPCtrlSel()
9144 return -1; in parseDPPCtrlSel()
9158 int64_t Val = -1; in parseDPPCtrl()
9177 if (Val == -1) in parseDPPCtrl()
9189 const MCInstrDesc &Desc = MII.get(Inst.getOpcode()); in cvtVOP3DPP()
9197 bool IsMAC = OldIdx != -1 && Src2ModIdx != -1 && in cvtVOP3DPP()
9198 Desc.getOperandConstraint(OldIdx, MCOI::TIED_TO) == -1; in cvtVOP3DPP()
9239 if (TiedTo != -1) { in cvtVOP3DPP()
9253 Desc.operands()[Inst.getNumOperands()].RegClass != -1) { in cvtVOP3DPP()
9302 const MCInstrDesc &Desc = MII.get(Inst.getOpcode()); in cvtDPP()
9311 if (TiedTo != -1) { in cvtDPP()
9366 //===----------------------------------------------------------------------===//
9368 //===----------------------------------------------------------------------===//
9457 const MCInstrDesc &Desc = MII.get(Inst.getOpcode()); in cvtSDWA()
9593 // This function should be defined after auto-generated include so that we have
9637 // Null is defined as a 32-bit register but in validateTargetOperandClass()
9638 // it should also be enabled with 64-bit operands. in validateTargetOperandClass()
9648 //===----------------------------------------------------------------------===//
9650 //===----------------------------------------------------------------------===//
9662 return Error(S, "expected a 16-bit value"); in parseEndpgm()
9671 //===----------------------------------------------------------------------===//
9673 //===----------------------------------------------------------------------===//