Lines Matching refs:VT
103 RTLIB::Libcall RTLIB::getFPLibCall(EVT VT, in getFPLibCall() argument
110 VT == MVT::f32 ? Call_F32 : in getFPLibCall()
111 VT == MVT::f64 ? Call_F64 : in getFPLibCall()
112 VT == MVT::f80 ? Call_F80 : in getFPLibCall()
113 VT == MVT::f128 ? Call_F128 : in getFPLibCall()
114 VT == MVT::ppcf128 ? Call_PPCF128 : in getFPLibCall()
447 MVT VT) { in getOUTLINE_ATOMIC() argument
448 if (!VT.isScalarInteger()) in getOUTLINE_ATOMIC()
450 uint64_t MemSize = VT.getScalarSizeInBits() / 8; in getOUTLINE_ATOMIC()
488 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) { in getSYNC() argument
491 switch (VT.SimpleTy) { \ in getSYNC()
669 for (MVT VT : {MVT::i2, MVT::i4}) in initActions()
670 OpActions[(unsigned)VT.SimpleTy][NT] = Expand; in initActions()
673 for (MVT VT : {MVT::i2, MVT::i4, MVT::v128i2, MVT::v64i4}) { in initActions()
674 setTruncStoreAction(AVT, VT, Expand); in initActions()
675 setLoadExtAction(ISD::EXTLOAD, AVT, VT, Expand); in initActions()
676 setLoadExtAction(ISD::ZEXTLOAD, AVT, VT, Expand); in initActions()
681 for (MVT VT : {MVT::i2, MVT::i4}) { in initActions()
682 setIndexedLoadAction(IM, VT, Expand); in initActions()
683 setIndexedStoreAction(IM, VT, Expand); in initActions()
684 setIndexedMaskedLoadAction(IM, VT, Expand); in initActions()
685 setIndexedMaskedStoreAction(IM, VT, Expand); in initActions()
689 for (MVT VT : MVT::fp_valuetypes()) { in initActions() local
690 MVT IntVT = MVT::getIntegerVT(VT.getFixedSizeInBits()); in initActions()
692 setOperationAction(ISD::ATOMIC_SWAP, VT, Promote); in initActions()
693 AddPromotedToType(ISD::ATOMIC_SWAP, VT, IntVT); in initActions()
698 for (MVT VT : MVT::all_valuetypes()) { in initActions() local
702 setIndexedLoadAction(IM, VT, Expand); in initActions()
703 setIndexedStoreAction(IM, VT, Expand); in initActions()
704 setIndexedMaskedLoadAction(IM, VT, Expand); in initActions()
705 setIndexedMaskedStoreAction(IM, VT, Expand); in initActions()
709 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand); in initActions()
729 VT, Expand); in initActions()
734 VT, Expand); in initActions()
739 VT, Expand); in initActions()
742 setOperationAction({ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}, VT, in initActions()
746 setOperationAction({ISD::UCMP, ISD::SCMP}, VT, Expand); in initActions()
750 {ISD::AVGFLOORS, ISD::AVGFLOORU, ISD::AVGCEILS, ISD::AVGCEILU}, VT, in initActions()
754 setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Expand); in initActions()
757 setOperationAction({ISD::CTLZ_ZERO_UNDEF, ISD::CTTZ_ZERO_UNDEF}, VT, in initActions()
760 setOperationAction({ISD::BITREVERSE, ISD::PARITY}, VT, Expand); in initActions()
763 setOperationAction({ISD::FROUND, ISD::FPOWI, ISD::FLDEXP, ISD::FFREXP}, VT, in initActions()
767 if (VT.isVector()) in initActions()
773 VT, Expand); in initActions()
777 setOperationAction(ISD::STRICT_##DAGN, VT, Expand); in initActions()
781 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, VT, Expand); in initActions()
791 VT, Expand); in initActions()
794 setOperationAction(ISD::VECTOR_SPLICE, VT, Expand); in initActions()
797 setOperationAction(ISD::VECTOR_COMPRESS, VT, Expand); in initActions()
801 setOperationAction(ISD::SDOPC, VT, Expand); in initActions()
805 setOperationAction(ISD::GET_FPENV, VT, Expand); in initActions()
806 setOperationAction(ISD::SET_FPENV, VT, Expand); in initActions()
807 setOperationAction(ISD::RESET_FPENV, VT, Expand); in initActions()
850 for (MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) { in initActions()
851 setOperationAction(ISD::GET_FPMODE, VT, Expand); in initActions()
852 setOperationAction(ISD::SET_FPMODE, VT, Expand); in initActions()
881 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const { in canOpTrap()
882 assert(isTypeLegal(VT)); in canOpTrap()
924 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const { in getTypeConversion()
926 if (VT.isSimple()) { in getTypeConversion()
927 MVT SVT = VT.getSimpleVT(); in getTypeConversion()
946 if (!VT.isVector()) { in getTypeConversion()
947 assert(VT.isInteger() && "Float types must be simple"); in getTypeConversion()
948 unsigned BitSize = VT.getSizeInBits(); in getTypeConversion()
951 EVT NVT = VT.getRoundIntegerType(Context); in getTypeConversion()
952 assert(NVT != VT && "Unable to round integer VT"); in getTypeConversion()
962 EVT::getIntegerVT(Context, VT.getSizeInBits() / 2)); in getTypeConversion()
966 ElementCount NumElts = VT.getVectorElementCount(); in getTypeConversion()
967 EVT EltVT = VT.getVectorElementType(); in getTypeConversion()
979 if (!VT.isPow2VectorType()) { in getTypeConversion()
991 if (VT.getVectorElementCount().isScalable()) in getTypeConversion()
994 VT.getHalfNumVectorElementsVT(Context)); in getTypeConversion()
1049 if (!VT.isPow2VectorType()) { in getTypeConversion()
1050 EVT NVT = VT.getPow2VectorType(Context); in getTypeConversion()
1054 if (VT.getVectorElementCount() == ElementCount::getScalable(1)) in getTypeConversion()
1059 VT.getVectorElementCount().divideCoefficientBy(2)); in getTypeConversion()
1063 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, in getVectorTypeBreakdownMVT() argument
1068 ElementCount EC = VT.getVectorElementCount(); in getVectorTypeBreakdownMVT()
1069 MVT EltTy = VT.getVectorElementType(); in getVectorTypeBreakdownMVT()
1075 if (VT.isScalableVector() && !isPowerOf2_32(EC.getKnownMinValue())) in getVectorTypeBreakdownMVT()
1225 MVT VT) const { in findRepresentativeClass()
1226 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; in findRepresentativeClass()
1379 MVT VT = (MVT::SimpleValueType) i; in computeRegisterProperties() local
1380 if (isTypeLegal(VT)) in computeRegisterProperties()
1383 MVT EltVT = VT.getVectorElementType(); in computeRegisterProperties()
1384 ElementCount EC = VT.getVectorElementCount(); in computeRegisterProperties()
1386 bool IsScalable = VT.isScalableVector(); in computeRegisterProperties()
1387 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT); in computeRegisterProperties()
1405 ValueTypeActions.setTypeAction(VT, TypePromoteInteger); in computeRegisterProperties()
1428 ValueTypeActions.setTypeAction(VT, TypeWidenVector); in computeRegisterProperties()
1437 MVT NVT = VT.getPow2VectorType(); in computeRegisterProperties()
1440 ValueTypeActions.setTypeAction(VT, TypeWidenVector); in computeRegisterProperties()
1453 unsigned NumRegisters = getVectorTypeBreakdownMVT(VT, IntermediateVT, in computeRegisterProperties()
1460 MVT NVT = VT.getPow2VectorType(); in computeRegisterProperties()
1461 if (NVT == VT) { in computeRegisterProperties()
1465 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector); in computeRegisterProperties()
1467 ValueTypeActions.setTypeAction(VT, TypeSplitVector); in computeRegisterProperties()
1469 ValueTypeActions.setTypeAction(VT, TypeSplitVector); in computeRegisterProperties()
1471 ValueTypeActions.setTypeAction(VT, EC.isScalable() in computeRegisterProperties()
1476 ValueTypeActions.setTypeAction(VT, TypeWidenVector); in computeRegisterProperties()
1500 EVT VT) const { in getSetCCResultType()
1501 assert(!VT.isVector() && "No default SetCC type for vectors!"); in getSetCCResultType()
1518 EVT VT, EVT &IntermediateVT, in getVectorTypeBreakdown() argument
1521 ElementCount EltCnt = VT.getVectorElementCount(); in getVectorTypeBreakdown()
1528 LegalizeTypeAction TA = getTypeAction(Context, VT); in getVectorTypeBreakdown()
1531 EVT RegisterEVT = getTypeToTransformTo(Context, VT); in getVectorTypeBreakdown()
1541 EVT EltTy = VT.getVectorElementType(); in getVectorTypeBreakdown()
1549 EVT PartVT = VT; in getVectorTypeBreakdown()
1562 divideCeil(VT.getVectorElementCount().getKnownMinValue(), in getVectorTypeBreakdown()
1648 EVT VT = ValueVTs[j]; in GetReturnInfo() local
1656 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) in GetReturnInfo()
1657 VT = TLI.getTypeForExtReturn(ReturnType->getContext(), VT, ExtendKind); in GetReturnInfo()
1660 TLI.getNumRegistersForCallingConv(ReturnType->getContext(), CC, VT); in GetReturnInfo()
1662 TLI.getRegisterTypeForCallingConv(ReturnType->getContext(), CC, VT); in GetReturnInfo()
1683 ISD::OutputArg(OutFlags, PartVT, VT, /*isfixed=*/true, 0, 0)); in GetReturnInfo()
1697 LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace, in allowsMemoryAccessForAlignment() argument
1704 Type *Ty = VT.getTypeForEVT(Context); in allowsMemoryAccessForAlignment()
1705 if (VT.isZeroSized() || Alignment >= DL.getABITypeAlign(Ty)) { in allowsMemoryAccessForAlignment()
1713 return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Flags, Fast); in allowsMemoryAccessForAlignment()
1717 LLVMContext &Context, const DataLayout &DL, EVT VT, in allowsMemoryAccessForAlignment() argument
1719 return allowsMemoryAccessForAlignment(Context, DL, VT, MMO.getAddrSpace(), in allowsMemoryAccessForAlignment()
1724 const DataLayout &DL, EVT VT, in allowsMemoryAccess() argument
1728 return allowsMemoryAccessForAlignment(Context, DL, VT, AddrSpace, Alignment, in allowsMemoryAccess()
1733 const DataLayout &DL, EVT VT, in allowsMemoryAccess() argument
1736 return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(), MMO.getAlign(), in allowsMemoryAccess()
1744 EVT VT = getApproximateEVTForLLT(Ty, DL, Context); in allowsMemoryAccess() local
1745 return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(), MMO.getAlign(), in allowsMemoryAccess()
2021 static std::string getReciprocalOpName(bool IsSqrt, EVT VT) { in getReciprocalOpName() argument
2022 std::string Name = VT.isVector() ? "vec-" : ""; in getReciprocalOpName()
2027 if (VT.getScalarType() == MVT::f64) { in getReciprocalOpName()
2029 } else if (VT.getScalarType() == MVT::f16) { in getReciprocalOpName()
2032 assert(VT.getScalarType() == MVT::f32 && in getReciprocalOpName()
2066 static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) { in getOpEnabled() argument
2099 std::string VTName = getReciprocalOpName(IsSqrt, VT); in getOpEnabled()
2126 static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) { in getOpRefinementSteps() argument
2154 std::string VTName = getReciprocalOpName(IsSqrt, VT); in getOpRefinementSteps()
2172 int TargetLoweringBase::getRecipEstimateSqrtEnabled(EVT VT, in getRecipEstimateSqrtEnabled() argument
2174 return getOpEnabled(true, VT, getRecipEstimateForFunc(MF)); in getRecipEstimateSqrtEnabled()
2177 int TargetLoweringBase::getRecipEstimateDivEnabled(EVT VT, in getRecipEstimateDivEnabled() argument
2179 return getOpEnabled(false, VT, getRecipEstimateForFunc(MF)); in getRecipEstimateDivEnabled()
2182 int TargetLoweringBase::getSqrtRefinementSteps(EVT VT, in getSqrtRefinementSteps() argument
2184 return getOpRefinementSteps(true, VT, getRecipEstimateForFunc(MF)); in getSqrtRefinementSteps()
2187 int TargetLoweringBase::getDivRefinementSteps(EVT VT, in getDivRefinementSteps() argument
2189 return getOpRefinementSteps(false, VT, getRecipEstimateForFunc(MF)); in getDivRefinementSteps()