51 void RegScavenger::setRegUsed(Register Reg, LaneBitmask LaneMask) {  in setRegUsed()  argument
52   LiveUnits.addRegMasked(Reg, LaneMask);  in setRegUsed()
65     SI.Reg = 0;  in init()
89       I.Reg = 0;  in backward()
95 bool RegScavenger::isRegUsed(Register Reg, bool includeReserved) const {  in isRegUsed()  argument
96   if (isReserved(Reg))  in isRegUsed()
98   return !LiveUnits.available(Reg);  in isRegUsed()
102   for (Register Reg : *RC) {  in FindUnusedReg()
103     if (!isRegUsed(Reg)) {  in FindUnusedReg()
104       LLVM_DEBUG(dbgs() << "Scavenger found unused reg: " << printReg(Reg, TRI)  in FindUnusedReg()
106       return Reg;  in FindUnusedReg()
114   for (Register Reg : *RC)  in getRegsAvailable()
115     if (!isRegUsed(Reg))  in getRegsAvailable()
116       Mask.set(Reg);  in getRegsAvailable()
152       for (MCPhysReg Reg : AllocationOrder) {  in findSurvivorBackwards()  local
153         if (!MRI.isReserved(Reg) && Used.available(Reg) &&  in findSurvivorBackwards()
154             LiveOut.available(Reg))  in findSurvivorBackwards()
155           return std::make_pair(Reg, MBB.end());  in findSurvivorBackwards()
177         for (MCPhysReg Reg : AllocationOrder) {  in findSurvivorBackwards()  local
178           if (!MRI.isReserved(Reg) && Used.available(Reg)) {  in findSurvivorBackwards()
179             AvilableReg = Reg;  in findSurvivorBackwards()
223 RegScavenger::spill(Register Reg, const TargetRegisterClass &RC, int SPAdj,  in spill()  argument
236     if (Scavenged[I].Reg != 0)  in spill()
266   Scavenged[SI].Reg = Reg;  in spill()
270   if (!TRI->saveScavengerRegister(*MBB, Before, UseMI, &RC, Reg)) {  in spill()
275                          TRI->getName(Reg) + " from class " +  in spill()
280     TII->storeRegToStackSlot(*MBB, Before, Reg, true, FI, &RC, TRI, Register());  in spill()
287     TII->loadRegFromStackSlot(*MBB, UseMI, Reg, FI, &RC, TRI, Register());  in spill()
308   MCPhysReg Reg = P.first;  in scavengeRegisterBackwards()  local
311   if (Reg != 0 && SpillBefore == MBB.end()) {  in scavengeRegisterBackwards()
312     LLVM_DEBUG(dbgs() << "Scavenged free register: " << printReg(Reg, TRI)  in scavengeRegisterBackwards()
314     return Reg;  in scavengeRegisterBackwards()
320   assert(Reg != 0 && "No register left to scavenge!");  in scavengeRegisterBackwards()
326   ScavengedInfo &Scavenged = spill(Reg, RC, SPAdj, SpillBefore, ReloadBefore);  in scavengeRegisterBackwards()
328   LiveUnits.removeReg(Reg);  in scavengeRegisterBackwards()
329   LLVM_DEBUG(dbgs() << "Scavenged register with spill: " << printReg(Reg, TRI)  in scavengeRegisterBackwards()
331   return Reg;  in scavengeRegisterBackwards()
412         Register Reg = MO.getReg();  in scavengeFrameVirtualRegsInBlock()  local
416         if (!Reg.isVirtual() ||  in scavengeFrameVirtualRegsInBlock()
417             Register::virtReg2Index(Reg) >= InitialNumVirtRegs)  in scavengeFrameVirtualRegsInBlock()
422         Register SReg = scavengeVReg(MRI, RS, Reg, true);  in scavengeFrameVirtualRegsInBlock()
434       Register Reg = MO.getReg();  in scavengeFrameVirtualRegsInBlock()  local
436       if (!Reg.isVirtual() ||  in scavengeFrameVirtualRegsInBlock()
437           Register::virtReg2Index(Reg) >= InitialNumVirtRegs)  in scavengeFrameVirtualRegsInBlock()
448         Register SReg = scavengeVReg(MRI, RS, Reg, false);  in scavengeFrameVirtualRegsInBlock()