Lines Matching refs:Reg
59 MachineRegisterInfo::setRegClass(Register Reg, const TargetRegisterClass *RC) { in setRegClass() argument
61 VRegInfo[Reg].first = RC; in setRegClass()
64 void MachineRegisterInfo::setRegBank(Register Reg, in setRegBank() argument
66 VRegInfo[Reg].first = &RegBank; in setRegBank()
70 constrainRegClass(MachineRegisterInfo &MRI, Register Reg, in constrainRegClass() argument
81 MRI.setRegClass(Reg, NewRC); in constrainRegClass()
86 Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs) { in constrainRegClass() argument
87 if (Reg.isPhysical()) in constrainRegClass()
89 return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs); in constrainRegClass()
93 MachineRegisterInfo::constrainRegAttrs(Register Reg, in constrainRegAttrs() argument
96 const LLT RegTy = getType(Reg); in constrainRegAttrs()
103 const auto &RegCB = getRegClassOrRegBank(Reg); in constrainRegAttrs()
105 setRegClassOrRegBank(Reg, ConstrainingRegCB); in constrainRegAttrs()
111 *this, Reg, cast<const TargetRegisterClass *>(RegCB), in constrainRegAttrs()
118 setType(Reg, ConstrainingRegTy); in constrainRegAttrs()
123 MachineRegisterInfo::recomputeRegClass(Register Reg) { in recomputeRegClass() argument
125 const TargetRegisterClass *OldRC = getRegClass(Reg); in recomputeRegClass()
134 for (MachineOperand &MO : reg_nodbg_operands(Reg)) { in recomputeRegClass()
143 setRegClass(Reg, NewRC); in recomputeRegClass()
148 Register Reg = Register::index2VirtReg(getNumVirtRegs()); in createIncompleteVirtualRegister() local
149 VRegInfo.grow(Reg); in createIncompleteVirtualRegister()
150 RegAllocHints.grow(Reg); in createIncompleteVirtualRegister()
151 insertVRegByName(Name, Reg); in createIncompleteVirtualRegister()
152 return Reg; in createIncompleteVirtualRegister()
166 Register Reg = createIncompleteVirtualRegister(Name); in createVirtualRegister() local
167 VRegInfo[Reg].first = RegClass; in createVirtualRegister()
168 noteNewVirtualRegister(Reg); in createVirtualRegister()
169 return Reg; in createVirtualRegister()
174 Register Reg = createIncompleteVirtualRegister(Name); in createVirtualRegister() local
175 VRegInfo[Reg].first = RegAttr.RCOrRB; in createVirtualRegister()
176 setType(Reg, RegAttr.Ty); in createVirtualRegister()
177 noteNewVirtualRegister(Reg); in createVirtualRegister()
178 return Reg; in createVirtualRegister()
183 Register Reg = createIncompleteVirtualRegister(Name); in cloneVirtualRegister() local
184 VRegInfo[Reg].first = VRegInfo[VReg].first; in cloneVirtualRegister()
185 setType(Reg, getType(VReg)); in cloneVirtualRegister()
186 noteCloneVirtualRegister(Reg, VReg); in cloneVirtualRegister()
187 return Reg; in cloneVirtualRegister()
198 Register Reg = createIncompleteVirtualRegister(Name); in createGenericVirtualRegister() local
200 VRegInfo[Reg].first = static_cast<RegisterBank *>(nullptr); in createGenericVirtualRegister()
201 setType(Reg, Ty); in createGenericVirtualRegister()
202 noteNewVirtualRegister(Reg); in createGenericVirtualRegister()
203 return Reg; in createGenericVirtualRegister()
212 Register Reg = Register::index2VirtReg(i); in clearVirtRegs() local
213 if (!VRegInfo[Reg].second) in clearVirtRegs()
215 verifyUseList(Reg); in clearVirtRegs()
217 << printReg(Reg, getTargetRegisterInfo()) << "...\n"; in clearVirtRegs()
218 for (MachineInstr &MI : reg_instructions(Reg)) in clearVirtRegs()
228 void MachineRegisterInfo::verifyUseList(Register Reg) const { in verifyUseList()
231 for (MachineOperand &M : reg_operands(Reg)) { in verifyUseList()
235 errs() << printReg(Reg, getTargetRegisterInfo()) in verifyUseList()
244 errs() << printReg(Reg, getTargetRegisterInfo()) in verifyUseList()
250 errs() << printReg(Reg, getTargetRegisterInfo()) in verifyUseList()
255 if (MO->getReg() != Reg) { in verifyUseList()
256 errs() << printReg(Reg, getTargetRegisterInfo()) in verifyUseList()
287 MO->Contents.Reg.Prev = MO; in addRegOperandToUseList()
288 MO->Contents.Reg.Next = nullptr; in addRegOperandToUseList()
295 MachineOperand *Last = Head->Contents.Reg.Prev; in addRegOperandToUseList()
298 Head->Contents.Reg.Prev = MO; in addRegOperandToUseList()
299 MO->Contents.Reg.Prev = Last; in addRegOperandToUseList()
305 MO->Contents.Reg.Next = Head; in addRegOperandToUseList()
309 MO->Contents.Reg.Next = nullptr; in addRegOperandToUseList()
310 Last->Contents.Reg.Next = MO; in addRegOperandToUseList()
322 MachineOperand *Next = MO->Contents.Reg.Next; in removeRegOperandFromUseList()
323 MachineOperand *Prev = MO->Contents.Reg.Prev; in removeRegOperandFromUseList()
329 Prev->Contents.Reg.Next = Next; in removeRegOperandFromUseList()
331 (Next ? Next : Head)->Contents.Reg.Prev = Prev; in removeRegOperandFromUseList()
333 MO->Contents.Reg.Prev = nullptr; in removeRegOperandFromUseList()
334 MO->Contents.Reg.Next = nullptr; in removeRegOperandFromUseList()
364 MachineOperand *Prev = Src->Contents.Reg.Prev; in moveOperands()
365 MachineOperand *Next = Src->Contents.Reg.Next; in moveOperands()
374 Prev->Contents.Reg.Next = Dst; in moveOperands()
378 (Next ? Next : Head)->Contents.Reg.Prev = Dst; in moveOperands()
409 MachineInstr *MachineRegisterInfo::getVRegDef(Register Reg) const { in getVRegDef()
411 def_instr_iterator I = def_instr_begin(Reg); in getVRegDef()
420 MachineInstr *MachineRegisterInfo::getUniqueVRegDef(Register Reg) const { in getUniqueVRegDef()
421 if (def_empty(Reg)) return nullptr; in getUniqueVRegDef()
422 def_instr_iterator I = def_instr_begin(Reg); in getUniqueVRegDef()
436 bool MachineRegisterInfo::hasAtMostUserInstrs(Register Reg, in hasAtMostUserInstrs() argument
438 return hasNItemsOrLess(use_instr_nodbg_begin(Reg), use_instr_nodbg_end(), in hasAtMostUserInstrs()
446 void MachineRegisterInfo::clearKillFlags(Register Reg) const { in clearKillFlags()
447 for (MachineOperand &MO : use_operands(Reg)) in clearKillFlags()
451 bool MachineRegisterInfo::isLiveIn(Register Reg) const { in isLiveIn()
453 if ((Register)LI.first == Reg || LI.second == Reg) in isLiveIn()
508 LaneBitmask MachineRegisterInfo::getMaxLaneMaskForVReg(Register Reg) const { in getMaxLaneMaskForVReg()
510 assert(Reg.isVirtual()); in getMaxLaneMaskForVReg()
511 const TargetRegisterClass &TRC = *getRegClass(Reg); in getMaxLaneMaskForVReg()
516 LLVM_DUMP_METHOD void MachineRegisterInfo::dumpUses(Register Reg) const { in dumpUses()
517 for (MachineInstr &I : use_instructions(Reg)) in dumpUses()
547 void MachineRegisterInfo::markUsesInDebugValueAsUndef(Register Reg) const { in markUsesInDebugValueAsUndef()
550 for (MachineInstr &UseMI : llvm::make_early_inc_range(use_instructions(Reg))) { in markUsesInDebugValueAsUndef()
551 if (UseMI.isDebugValue() && UseMI.hasDebugOperandForReg(Reg)) in markUsesInDebugValueAsUndef()
613 void MachineRegisterInfo::disableCalleeSavedRegister(MCRegister Reg) { in disableCalleeSavedRegister() argument
616 assert(Reg && (Reg < TRI->getNumRegs()) && in disableCalleeSavedRegister()
632 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) in disableCalleeSavedRegister()