Lines Matching refs:RevCond
1033 SmallVector<MachineOperand, 4> RevCond(BBI.BrCond.begin(), BBI.BrCond.end()); in AnalyzeBranches() local
1034 BBI.IsBrReversible = (RevCond.size() == 0) || in AnalyzeBranches()
1035 !TII->reverseBranchCondition(RevCond); in AnalyzeBranches()
1281 RevCond(BBI.BrCond.begin(), BBI.BrCond.end()); in AnalyzeBlock() local
1282 bool CanRevCond = !TII->reverseBranchCondition(RevCond); in AnalyzeBlock()
1300 bool FalseFeasible = FeasibilityAnalysis(FalseBBI, RevCond, in AnalyzeBlock()
1391 FeasibilityAnalysis(FalseBBI, RevCond, true)) { in AnalyzeBlock()
1402 FeasibilityAnalysis(FalseBBI, RevCond, true, true)) { in AnalyzeBlock()
1412 FeasibilityAnalysis(FalseBBI, RevCond)) { in AnalyzeBlock()
1690 SmallVector<MachineOperand, 4> RevCond(CvtBBI->BrCond.begin(), in IfConvertTriangle() local
1692 if (TII->reverseBranchCondition(RevCond)) in IfConvertTriangle()
1708 TII->insertBranch(*BBI.BB, CvtBBI->FalseBB, nullptr, RevCond, dl); in IfConvertTriangle()
1782 SmallVector<MachineOperand, 4> RevCond(BBI.BrCond.begin(), BBI.BrCond.end()); in IfConvertDiamondCommon() local
1783 if (TII->reverseBranchCondition(RevCond)) in IfConvertDiamondCommon()
1786 SmallVector<MachineOperand, 4> *Cond2 = &RevCond; in IfConvertDiamondCommon()