168     const MachineOperand &Def = MI.getOperand(0);  in transferUsedLanes()  local
169     Register DefReg = Def.getReg();  in transferUsedLanes()
203   const MachineOperand &Def = *MI.defs().begin();  in transferDefinedLanesStep()  local
204   Register DefReg = Def.getReg();  in transferDefinedLanesStep()
214   DefinedLanes = transferDefinedLanes(Def, OpNum, DefinedLanes);  in transferDefinedLanesStep()
227     const MachineOperand &Def, unsigned OpNum, LaneBitmask DefinedLanes) const {  in transferDefinedLanes()  argument
228   const MachineInstr &MI = *Def.getParent();  in transferDefinedLanes()
262   assert(Def.getSubReg() == 0 &&  in transferDefinedLanes()
264   DefinedLanes &= MRI->getMaxLaneMaskForVReg(Def.getReg());  in transferDefinedLanes()
274   const MachineOperand &Def = *MRI->def_begin(Reg);  in determineInitialDefinedLanes()  local
275   const MachineInstr &DefMI = *Def.getParent();  in determineInitialDefinedLanes()
283     if (Def.isDead())  in determineInitialDefinedLanes()
321       DefinedLanes |= transferDefinedLanes(Def, OpNum, MODefinedLanes);  in determineInitialDefinedLanes()
325   if (DefMI.isImplicitDef() || Def.isDead())  in determineInitialDefinedLanes()
328   assert(Def.getSubReg() == 0 &&  in determineInitialDefinedLanes()
346       const MachineOperand &Def = *UseMI.defs().begin();  in determineInitialUsedLanes()  local
347       Register DefReg = Def.getReg();  in determineInitialUsedLanes()
432   const MachineOperand &Def = MI.getOperand(0);  in isUndefInput()  local
433   Register DefReg = Def.getReg();  in isUndefInput()
474     MachineOperand &Def = *MRI->def_begin(Reg);  in computeSubRegisterLaneBitInfo()  local
475     const MachineInstr &MI = *Def.getParent();  in computeSubRegisterLaneBitInfo()