119        qtest_writel(qts, CANFD0_BASE_ADDR + R_AFMR_REGISTER0 + 8 * i,  in enable_filters()
121        qtest_writel(qts, CANFD0_BASE_ADDR + R_AFIR_REGISTER0 + 8 * i,  in enable_filters()
125        qtest_writel(qts, CANFD1_BASE_ADDR + R_AFMR_REGISTER0 + 8 * i,  in enable_filters()
127        qtest_writel(qts, CANFD1_BASE_ADDR + R_AFIR_REGISTER0 + 8 * i,  in enable_filters()
132     qtest_writel(qts, CANFD0_BASE_ADDR + R_FILTER_CONTROL_REGISTER,  in enable_filters()
134     qtest_writel(qts, CANFD1_BASE_ADDR + R_FILTER_CONTROL_REGISTER,  in enable_filters()
143     qtest_writel(qts, CANFD0_BASE_ADDR + R_SRR_OFFSET, SRR_CONFIG_MODE);  in configure_canfd()
144     qtest_writel(qts, CANFD1_BASE_ADDR + R_SRR_OFFSET, SRR_CONFIG_MODE);  in configure_canfd()
147     qtest_writel(qts, CANFD0_BASE_ADDR + R_MSR_OFFSET, mode);  in configure_canfd()
148     qtest_writel(qts, CANFD1_BASE_ADDR + R_MSR_OFFSET, mode);  in configure_canfd()
161     qtest_writel(qts, CANFD1_BASE_ADDR + R_IER_OFFSET, ENABLE_ALL_INTERRUPTS);  in configure_canfd()
162     qtest_writel(qts, CANFD1_BASE_ADDR + R_IER_OFFSET, ENABLE_ALL_INTERRUPTS);  in configure_canfd()
164     qtest_writel(qts, CANFD0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CANFD);  in configure_canfd()
165     qtest_writel(qts, CANFD1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CANFD);  in configure_canfd()
216     qtest_writel(qts, CANFD1_BASE_ADDR + R_ICR_OFFSET, ISR_RXOK);  in read_data()
223     qtest_writel(qts, can_base_addr + R_TXID_OFFSET, buf_tx[0]);  in write_data()
224     qtest_writel(qts, can_base_addr + R_TXDLC_OFFSET, buf_tx[1]);  in write_data()
228             qtest_writel(qts, can_base_addr + R_TXDATA1_OFFSET + 4 * i,  in write_data()
232         qtest_writel(qts, can_base_addr + R_TXDATA1_OFFSET, buf_tx[2]);  in write_data()
233         qtest_writel(qts, can_base_addr + R_TXDATA2_OFFSET, buf_tx[3]);  in write_data()
241     qtest_writel(qts, can_base_addr + R_TX_READY_REQ_REGISTER,  in send_data()
250     qtest_writel(qts, CANFD0_BASE_ADDR + R_ICR_OFFSET, ISR_TXOK);  in send_data()