24 #define TIMER_BASE 0x48000000
27 #define PERIPHNSPPC0 (0x50080000 + 0x70)
30 #define COUNTER_BASE 0x58100000
33 #define CNTCR 0
34 #define CNTSR 0x4
35 #define CNTCV_LO 0x8
36 #define CNTCV_HI 0xc
37 #define CNTSCR 0x10
40 #define CNTPCT_LO 0
42 #define CNTFRQ 0x10
43 #define CNTP_CVAL_LO 0x20
44 #define CNTP_CVAL_HI 0x24
45 #define CNTP_TVAL 0x28
46 #define CNTP_CTL 0x2c
47 #define CNTP_AIVAL_LO 0x40
48 #define CNTP_AIVAL_HI 0x44
49 #define CNTP_AIVAL_RELOAD 0x48
50 #define CNTP_AIVAL_CTL 0x4c
72     writel(COUNTER_BASE + CNTCR, 0);  in reset_counter_and_timer()
73     writel(TIMER_BASE + CNTP_CTL, 0);  in reset_counter_and_timer()
74     writel(TIMER_BASE + CNTP_AIVAL_CTL, 0);  in reset_counter_and_timer()
75     writel(COUNTER_BASE + CNTCV_LO, 0);  in reset_counter_and_timer()
76     writel(COUNTER_BASE + CNTCV_HI, 0);  in reset_counter_and_timer()
86     g_assert_cmpuint(readl(COUNTER_BASE + CNTCV_LO), ==, 0);  in test_counter()
87     g_assert_cmpuint(readl(COUNTER_BASE + CNTCV_HI), ==, 0);  in test_counter()
92     g_assert_cmpuint(readl(COUNTER_BASE + CNTCV_HI), ==, 0);  in test_counter()
94     writel(COUNTER_BASE + CNTCR, 0);  in test_counter()
95     writel(COUNTER_BASE + CNTSCR, 0x00100000); /* 1/16th normal speed */  in test_counter()
99     g_assert_cmpuint(readl(COUNTER_BASE + CNTCV_HI), ==, 0);  in test_counter()
111      * is on port 0 of PPC0, controlled by bit 0 of this register.  in test_timer()
117     /* Timer starts disabled and with a counter of 0 */  in test_timer()
118     g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 0);  in test_timer()
119     g_assert_cmpuint(readl(TIMER_BASE + CNTPCT_LO), ==, 0);  in test_timer()
120     g_assert_cmpuint(readl(TIMER_BASE + CNTPCT_HI), ==, 0);  in test_timer()
128     g_assert_cmpuint(readl(TIMER_BASE + CNTPCT_HI), ==, 0);  in test_timer()
132     writel(TIMER_BASE + CNTP_CVAL_HI, 0);  in test_timer()
139     g_assert_cmpuint(readl(TIMER_BASE + CNTP_TVAL), ==, 0);  in test_timer()
148     g_assert_cmpuint(readl(TIMER_BASE + CNTP_AIVAL_HI), ==, 0);  in test_timer()
160     g_assert_cmpuint(readl(TIMER_BASE + CNTP_AIVAL_HI), ==, 0);  in test_timer()
164     /* Check that writing 0 to CLR clears the interrupt */  in test_timer()
171     g_assert_cmpuint(readl(TIMER_BASE + CNTP_AIVAL_HI), ==, 0);  in test_timer()
181     writel(TIMER_BASE + CNTP_AIVAL_CTL, 0);  in test_timer()
182     clock_step_ticks(0x42ULL << 32);  in test_timer()
184     g_assert_cmphex(readl(TIMER_BASE + CNTPCT_HI), ==, 0x42);  in test_timer()
189     g_assert_cmphex(readl(TIMER_BASE + CNTP_AIVAL_HI), ==, 0x42);  in test_timer()
205     writel(TIMER_BASE + CNTP_CVAL_HI, 0);  in test_timer_scale_change()
210     writel(COUNTER_BASE + CNTCR, 0);  in test_timer_scale_change()
211     writel(COUNTER_BASE + CNTSCR, 0x00100000); /* 1/16th normal speed */  in test_timer_scale_change()