117         set_tima32(qts, i, TM_QW2_HV_POOL + TM_WORD0, 0x000000ff);  in reset_pool_threads()
140         set_tima32(qts, i, TM_QW3_HV_PHYS + TM_WORD0, 0x00ff00ff);  in reset_hw_threads()
239     reg32 = get_tima32(qts, target_pir, TM_QW3_HV_PHYS + TM_WORD0);  in test_hw_irq()
263     reg32 = get_tima32(qts, target_pir, TM_QW3_HV_PHYS + TM_WORD0);  in test_hw_irq()
298     reg32 = get_tima32(qts, target_pir, TM_QW3_HV_PHYS + TM_WORD0);  in test_pool_irq()
305     reg32 = get_tima32(qts, target_pir, TM_QW2_HV_POOL + TM_WORD0);  in test_pool_irq()
325     reg32 = get_tima32(qts, target_pir, TM_QW2_HV_POOL + TM_WORD0);  in test_pool_irq()
336     reg32 = get_tima32(qts, target_pir, TM_QW3_HV_PHYS + TM_WORD0);  in test_pool_irq()
365     qw1w0 = get_tima32(qts, target_pir, TM_QW1_OS + TM_WORD0);  in test_pull_thread_ctx_to_odd_thread_cl()
366     qw3w0 = get_tima32(qts, target_pir, TM_QW3_HV_PHYS + TM_WORD0);  in test_pull_thread_ctx_to_odd_thread_cl()
376     memcpy(&cl_word, &cl_pair[XIVE_ODD_CL + TM_QW1_OS + TM_WORD0], 4);  in test_pull_thread_ctx_to_odd_thread_cl()
378     memcpy(&cl_word, &cl_pair[XIVE_ODD_CL + TM_QW3_HV_PHYS + TM_WORD0], 4);  in test_pull_thread_ctx_to_odd_thread_cl()
425         reg32 = get_tima32(qts, chosen_one, TM_QW3_HV_PHYS + TM_WORD0);  in test_hw_group_irq()
454     reg32 = get_tima32(qts, chosen_one, TM_QW3_HV_PHYS + TM_WORD0);  in test_hw_group_irq()
501         reg32 = get_tima32(qts, i, TM_QW3_HV_PHYS + TM_WORD0);  in test_hw_group_irq_backlog()
514     reg32 = get_tima32(qts, chosen_one, TM_QW3_HV_PHYS + TM_WORD0);  in test_hw_group_irq_backlog()
538     reg32 = get_tima32(qts, chosen_one, TM_QW3_HV_PHYS + TM_WORD0);  in test_hw_group_irq_backlog()