58     if (readl(GPIO(n) + GP_N_TLOCK1) != 0) {  in gpio_unlock()
90     g_assert_cmphex(readl(GPIO(0) + GP_N_DOUT), ==, 0x12345678);  in test_dout_to_din()
91     g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0x12345678);  in test_dout_to_din()
108     g_assert_cmphex(readl(GPIO(0) + GP_N_PU), ==, 0x23456789);  in test_pullup_pulldown()
109     g_assert_cmphex(readl(GPIO(0) + GP_N_PD), ==, ~0x23456789U);  in test_pullup_pulldown()
110     g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0x23456789);  in test_pullup_pulldown()
125     g_assert_cmphex(readl(GPIO(0) + GP_N_OE), ==, 0x3456789a);  in test_output_enable()
126     g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0x3456789a);  in test_output_enable()
129     g_assert_cmphex(readl(GPIO(0) + GP_N_OE), ==, 0x34547898);  in test_output_enable()
130     g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0x34547898);  in test_output_enable()
133     g_assert_cmphex(readl(GPIO(0) + GP_N_OE), ==, 0x3454f899);  in test_output_enable()
134     g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0x3454f899);  in test_output_enable()
152     g_assert_cmphex(readl(GPIO(0) + GP_N_OTYP), ==, 0x456789ab);  in test_open_drain()
153     g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0xff900f00);  in test_open_drain()
168     g_assert_cmphex(readl(GPIO(0) + GP_N_POL), ==, 0x6789abcd);  in test_polarity()
169     g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0x56789abc);  in test_polarity()
179     g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, ~0x789abcdeU);  in test_polarity()
190     g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0xff00ffff);  in test_polarity()
202     g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0xff9a4300);  in test_input_mask()
212     g_assert_cmphex(readl(GPIO(0) + GP_N_TLOCK1), ==, 0);  in test_temp_lock()
215     g_assert_cmphex(readl(GPIO(0) + GP_N_TLOCK1), ==, 1);  in test_temp_lock()
217     g_assert_cmphex(readl(GPIO(0) + GP_N_DOUT), ==, 0x98765432);  in test_temp_lock()
220     g_assert_cmphex(readl(GPIO(0) + GP_N_TLOCK1), ==, 0);  in test_temp_lock()
222     g_assert_cmphex(readl(GPIO(0) + GP_N_DOUT), ==, 0xa9876543);  in test_temp_lock()
226     g_assert_cmphex(readl(GPIO(0) + GP_N_TLOCK1), ==, 1);  in test_temp_lock()
228     g_assert_cmphex(readl(GPIO(0) + GP_N_DOUT), ==, 0xa9876543);  in test_temp_lock()
231     g_assert_cmphex(readl(GPIO(0) + GP_N_TLOCK1), ==, 0);  in test_temp_lock()
233     g_assert_cmphex(readl(GPIO(0) + GP_N_DOUT), ==, 0x98765432);  in test_temp_lock()
245     g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0xba987654);  in test_events_level()
248     g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0xba987654);  in test_events_level()
251     g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0xba980000);  in test_events_level()
254     g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00000000);  in test_events_level()
268     g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00000000);  in test_events_rising_edge()
271     g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x0000ff00);  in test_events_rising_edge()
274     g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00ffff00);  in test_events_rising_edge()
277     g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00ff0f00);  in test_events_rising_edge()
280     g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00000000);  in test_events_rising_edge()
294     g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00000000);  in test_events_both_edges()
297     g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00ffff00);  in test_events_both_edges()
300     g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x10ffff08);  in test_events_both_edges()
303     g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x10ff0f08);  in test_events_both_edges()
306     g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00000000);  in test_events_both_edges()
323     g_assert_cmphex(readl(GPIO(n) + GP_N_EVST), ==, 0x00000000);  in test_gpion_irq()
326     g_assert_cmphex(readl(GPIO(n) + GP_N_EVST), ==, 0x00008000);  in test_gpion_irq()