287     entry->attr = pte & 0xf;  in xtensa_tlb_set_entry_mmu()
315         entry->attr = pte & 0xf;  in xtensa_tlb_set_entry()
361                 .attr = 7,  in reset_tlb_mmu_ways56()
367                 .attr = 3,  in reset_tlb_mmu_ways56()
376                 .attr = 7,  in reset_tlb_mmu_ways56()
382                 .attr = 3,  in reset_tlb_mmu_ways56()
394             entry[6][ei].attr = 3;  in reset_tlb_mmu_ways56()
408         entry[0][ei].attr = 2;  in reset_tlb_region_way0()
518         return entry->paddr | entry->attr;  in HELPER()
573  * Convert MMU ATTR to PAGE_{READ,WRITE,EXEC} mask.
576 static unsigned mmu_attr_to_access(uint32_t attr)  in mmu_attr_to_access()  argument
580     if (attr < 12) {  in mmu_attr_to_access()
582         if (attr & 0x1) {  in mmu_attr_to_access()
585         if (attr & 0x2) {  in mmu_attr_to_access()
589         switch (attr & 0xc) {  in mmu_attr_to_access()
602     } else if (attr == 13) {  in mmu_attr_to_access()
609  * Convert region protection ATTR to PAGE_{READ,WRITE,EXEC} mask.
612 static unsigned region_attr_to_access(uint32_t attr)  in region_attr_to_access()  argument
624     return access[attr & 0xf];  in region_attr_to_access()
631 static unsigned cacheattr_attr_to_access(uint32_t attr)  in cacheattr_attr_to_access()  argument
642     return access[attr & 0xf];  in cacheattr_attr_to_access()
650 static int attr_pattern_match(uint32_t attr,  in attr_pattern_match()  argument
657         if ((attr & pattern[i].mask) == pattern[i].value) {  in attr_pattern_match()
664 static unsigned mpu_attr_to_cpu_cache(uint32_t attr)  in mpu_attr_to_cpu_cache()  argument
674     if (attr_pattern_match(attr, cpu_c, ARRAY_SIZE(cpu_c))) {  in mpu_attr_to_cpu_cache()
676         if (attr & 0x10) {  in mpu_attr_to_cpu_cache()
679         if (attr & 0x20) {  in mpu_attr_to_cpu_cache()
682         if (attr & 0x40) {  in mpu_attr_to_cpu_cache()
689 static unsigned mpu_attr_to_type(uint32_t attr)  in mpu_attr_to_type()  argument
715     attr = (attr & XTENSA_MPU_MEM_TYPE_MASK) >> XTENSA_MPU_MEM_TYPE_SHIFT;  in mpu_attr_to_type()
716     if (attr_pattern_match(attr, device_type, ARRAY_SIZE(device_type))) {  in mpu_attr_to_type()
718         if (attr & 0x80) {  in mpu_attr_to_type()
722     if (attr_pattern_match(attr, sys_nc_type, ARRAY_SIZE(sys_nc_type))) {  in mpu_attr_to_type()
725     if (attr_pattern_match(attr, sys_c_type, ARRAY_SIZE(sys_c_type))) {  in mpu_attr_to_type()
727         if (attr & 0x1) {  in mpu_attr_to_type()
730         if (attr & 0x2) {  in mpu_attr_to_type()
733         if (attr & 0x4) {  in mpu_attr_to_type()
737     if (attr_pattern_match(attr, b, ARRAY_SIZE(b))) {  in mpu_attr_to_type()
740     type |= mpu_attr_to_cpu_cache(attr);  in mpu_attr_to_type()
745 static unsigned mpu_attr_to_access(uint32_t attr, unsigned ring)  in mpu_attr_to_access()  argument
776     type = mpu_attr_to_cpu_cache(attr);  in mpu_attr_to_access()
777     rv = access[ring != 0][(attr & XTENSA_MPU_ACC_RIGHTS_MASK) >>  in mpu_attr_to_access()
854     *access = mmu_attr_to_access(entry->attr) &  in get_physical_addr_mmu()
917     *access = region_attr_to_access(entry->attr);  in get_physical_addr_region()
966         env->mpu_fg[segment].attr = p & XTENSA_MPU_ATTR_MASK;  in HELPER()
989         return env->mpu_fg[segment].attr;  in HELPER()
1007         return env->mpu_fg[segment].attr | segment | XTENSA_MPU_PROBE_V;  in HELPER()
1012         return env->config->mpu_bg[bg_segment].attr | XTENSA_MPU_PROBE_B;  in HELPER()
1023     uint32_t attr;  in get_physical_addr_mpu()  local
1032         attr = env->mpu_fg[segment].attr;  in get_physical_addr_mpu()
1037         attr = env->config->mpu_bg[segment].attr;  in get_physical_addr_mpu()
1040     *access = mpu_attr_to_access(attr, mmu_idx);  in get_physical_addr_mpu()
1118                 unsigned access = attr_to_access(entry->attr);  in dump_tlb()
1125                     qemu_printf("\tVaddr       Paddr       ASID  Attr RWX Cache\n"  in dump_tlb()
1132                             entry->attr,  in dump_tlb()
1148     qemu_printf("\t%s  Vaddr       Attr        Ring0  Ring1  System Type    CPU cache\n"  in dump_mpu()
1154         uint32_t attr = entry[i].attr;  in dump_mpu()  local
1155         unsigned access0 = mpu_attr_to_access(attr, 0);  in dump_mpu()
1156         unsigned access1 = mpu_attr_to_access(attr, 1);  in dump_mpu()
1157         unsigned type = mpu_attr_to_type(attr);  in dump_mpu()
1163                     entry[i].vaddr, attr,  in dump_mpu()