xtensa/core-dsp3400/core-matmap.h

3  *	parameters (CHAL) of the Xtensa processor core configuration.
19  *	XCHAL_ICACHE_SIZE		(presence of I-cache)
20  *	XCHAL_DCACHE_SIZE		(presence of D-cache)
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54 /*  Cache Attribute encodings -- lists of access modes for each cache attribute:  */
106  *  Specific encoded cache attribute values of general interest.
108  *  one is returned instead (eg. writethru instead of writeback,
109  *  bypass instead of writethru).
127  *	ASID = address-space ID (acts as an "extension" of virtual addresses)
134  *	way  = each TLB (ITLB and DTLB) consists of a number of "ways"
135  *		that simultaneously match the virtual address of an access;
139  *		each way can be independently configured in terms of number of
141  *	set  = group of contiguous ways with exactly identical parameters
143  *		from the page table and storing it in one of the auto-refill ways;
157  *	  whose bits n*4+3 .. n*4 index the list of page sizes for way n
160  *	  ways have independent lists of supported page sizes sharing a
169 #define XCHAL_MMU_SR_BITS		0	/* number of size-restriction bits supported */
170 #define XCHAL_MMU_CA_BITS		4	/* number of bits needed to hold cache attribute encoding */
177 #define XCHAL_ITLB_WAY_BITS		0	/* number of bits holding the ways */
178 #define XCHAL_ITLB_WAYS			1	/* number of ways (n-way set-associative TLB) */
179 #define XCHAL_ITLB_ARF_WAYS		0	/* number of auto-refill ways */
180 #define XCHAL_ITLB_SETS			1	/* number of sets (groups of ways with identical settings) */
186 #define XCHAL_ITLB_ARF_SETS		0	/* number of auto-refill sets */
189 #define XCHAL_ITLB_MINWIRED_SETS	0	/* number of "min-wired" sets */
192 /*  ITLB way set 0 (group of ways 0 thru 0):  */
193 #define XCHAL_ITLB_SET0_WAY			0	/* index of first way in this way set */
194 #define XCHAL_ITLB_SET0_WAYS			1	/* number of (contiguous) ways in this way set */
195 #define XCHAL_ITLB_SET0_ENTRIES_LOG2		3	/* log2(number of entries in this way) */
196 #define XCHAL_ITLB_SET0_ENTRIES			8	/* number of entries in this way (always a power of 2) */
198 #define XCHAL_ITLB_SET0_PAGESIZES		1	/* number of supported page sizes in this way */
199 #define XCHAL_ITLB_SET0_PAGESZ_BITS		0	/* number of bits to encode the page size */
202 #define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST	29	/* list of log2(page size)s, separated by XCHAL_SEP;
212 /*  Constant VPN values for each entry of ITLB way set 0 (because VPN_CONSTMASK is non-zero):  */
221 /*  Reset PPN values for each entry of ITLB way set 0 (because SET0_PPN_RESET is non-zero):  */
230 /*  Reset CA values for each entry of ITLB way set 0 (because SET0_CA_RESET is non-zero):  */
243 #define XCHAL_DTLB_WAY_BITS		0	/* number of bits holding the ways */
244 #define XCHAL_DTLB_WAYS			1	/* number of ways (n-way set-associative TLB) */
245 #define XCHAL_DTLB_ARF_WAYS		0	/* number of auto-refill ways */
246 #define XCHAL_DTLB_SETS			1	/* number of sets (groups of ways with identical settings) */
252 #define XCHAL_DTLB_ARF_SETS		0	/* number of auto-refill sets */
255 #define XCHAL_DTLB_MINWIRED_SETS	0	/* number of "min-wired" sets */
258 /*  DTLB way set 0 (group of ways 0 thru 0):  */
259 #define XCHAL_DTLB_SET0_WAY			0	/* index of first way in this way set */
260 #define XCHAL_DTLB_SET0_WAYS			1	/* number of (contiguous) ways in this way set */
261 #define XCHAL_DTLB_SET0_ENTRIES_LOG2		3	/* log2(number of entries in this way) */
262 #define XCHAL_DTLB_SET0_ENTRIES			8	/* number of entries in this way (always a power of 2) */
264 #define XCHAL_DTLB_SET0_PAGESIZES		1	/* number of supported page sizes in this way */
265 #define XCHAL_DTLB_SET0_PAGESZ_BITS		0	/* number of bits to encode the page size */
268 #define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST	29	/* list of log2(page size)s, separated by XCHAL_SEP;
278 /*  Constant VPN values for each entry of DTLB way set 0 (because VPN_CONSTMASK is non-zero):  */
287 /*  Reset PPN values for each entry of DTLB way set 0 (because SET0_PPN_RESET is non-zero):  */
296 /*  Reset CA values for each entry of DTLB way set 0 (because SET0_CA_RESET is non-zero):  */