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39 * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
49 #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
53 #define XCHAL_HAVE_DEBUG 1 /* debug option */
54 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
55 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
56 #define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
57 #define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
58 #define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
59 #define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
60 #define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
64 #define XCHAL_HAVE_L32R 1 /* L32R instruction */
65 #define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
67 #define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
70 #define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
71 #define XCHAL_HAVE_ABS 1 /* ABS instruction */
74 #define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
75 #define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
77 #define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
78 #define XCHAL_NUM_CONTEXTS 1 /* */
81 #define XCHAL_HAVE_PRID 1 /* processor ID register */
82 #define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
85 #define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
86 #define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */
87 #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
91 #define XCHAL_HAVE_FP 1 /* floating point pkg */
117 #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
118 #define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
137 #define XCHAL_HW_VERSION_MINOR 1 /* minor ver# of targeted hw */
139 #define XCHAL_HW_REL_LX3 1
140 #define XCHAL_HW_REL_LX3_0 1
141 #define XCHAL_HW_REL_LX3_0_1 1
142 #define XCHAL_HW_CONFIGID_RELIABLE 1
145 #define XCHAL_HW_MIN_VERSION_MINOR 1 /* minor v of earliest tgt hw */
148 #define XCHAL_HW_MAX_VERSION_MINOR 1 /* minor v of latest tgt hw */
164 #define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
183 #define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
196 #define XCHAL_ICACHE_LINE_LOCKABLE 1
197 #define XCHAL_DCACHE_LINE_LOCKABLE 1
226 /* Instruction RAM 1: */
238 /* Data RAM 1: */
249 #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
250 #define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
252 #define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
260 /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
271 /* Masks of interrupts at each range 1..n of interrupt levels: */
290 #define XCHAL_INT9_LEVEL 1
293 #define XCHAL_INT12_LEVEL 1
295 #define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
329 /* (There are many interrupts each at level(s) 1, 2, 3, 4, 5.) */
342 #define XCHAL_EXTINT0_NUM 1 /* (intlevel 5) */
350 #define XCHAL_EXTINT8_NUM 9 /* (intlevel 1) */
358 number: 1 == XEA1 (old)
361 #define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
362 #define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
364 #define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
366 #define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
367 #define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
419 #define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
431 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
432 #define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
437 #define XCHAL_HAVE_XLT_CACHEATTR 1 /* region prot. w/translation */
444 #define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */