Lines Matching full:option

41  *  Note:  Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
51 #define XCHAL_HAVE_WINDOWED		1	/* windowed registers option */
55 #define XCHAL_HAVE_DEBUG		1	/* debug option */
75 #define XCHAL_HAVE_CALL4AND12		1	/* (obsolete option) */
103 #define XCHAL_HAVE_FUSION_FP		0	/* Fusion FP option */
104 #define XCHAL_HAVE_FUSION_LOW_POWER	0	/* Fusion Low Power option */
105 #define XCHAL_HAVE_FUSION_AES		0	/* Fusion BLE/Wifi AES-128 CCM option */
106 #define XCHAL_HAVE_FUSION_CONVENC	0	/* Fusion Conv Encode option */
107 #define XCHAL_HAVE_FUSION_LFSR_CRC	0	/* Fusion LFSR-CRC option */
108 #define XCHAL_HAVE_FUSION_BITOPS	0	/* Fusion Bit Operations Support option */
109 #define XCHAL_HAVE_FUSION_AVS		0	/* Fusion AVS option */
110 #define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0	/* Fusion 16-bit Baseband option */
111 #define XCHAL_HAVE_FUSION_VITERBI	0	/* Fusion Viterbi option */
112 #define XCHAL_HAVE_FUSION_SOFTDEMAP	0	/* Fusion Soft Bit Demap option */
115 #define XCHAL_HAVE_HIFI5_NN_MAC		0	/* HiFi5 Audio Engine NN-MAC option */
116 #define XCHAL_HAVE_HIFI5_VFPU		0	/* HiFi5 Audio Engine Single-Precision VFPU option */
117 #define XCHAL_HAVE_HIFI5_HP_VFPU	0	/* HiFi5 Audio Engine Half-Precision VFPU option */
119 #define XCHAL_HAVE_HIFI4_VFPU		0	/* HiFi4 Audio Engine VFPU option */
121 #define XCHAL_HAVE_HIFI3_VFPU		0	/* HiFi3 Audio Engine VFPU option */
123 #define XCHAL_HAVE_HIFI3Z_VFPU	0	/* HiFi3Z Audio Engine VFPU option */
154 #define XCHAL_HAVE_FUSIONG_SP_VFPU	0    /* sp_vfpu option on FusionG */
155 #define XCHAL_HAVE_FUSIONG_DP_VFPU	0    /* dp_vfpu option on FusionG */
160 #define XCHAL_HAVE_FUSIONJ_SP_VFPU	0    /* sp_vfpu option on FusionJ */
161 #define XCHAL_HAVE_FUSIONJ_DP_VFPU	0    /* dp_vfpu option on FusionJ */
181 #define XCHAL_HAVE_CONNX_B_SP_VFPU      0    /* Single-precision Vector Floating-point option on Co…
182 …X_B_SPX_VFPU     0    /* Single-precision Extended Vector Floating-point option on ConnX B10 & B20…
183 …NNX_B_HPX_VFPU     0    /* Half-precision Extended Vector Floating-point option on ConnX B10 & B20…
184 …X_B_32B_MAC      0    /* 32-bit vector MAC (real and complex), FIR & FFT option on ConnX B10 & B20…
185 #define XCHAL_HAVE_CONNX_B_VITERBI      0    /* Viterbi option on ConnX B10 & B20 */
186 #define XCHAL_HAVE_CONNX_B_TURBO        0    /* Turbo option on ConnX B10 & B20 */
187 #define XCHAL_HAVE_CONNX_B_LDPC         0    /* LDPC option on ConnX B10 & B20 */
189 #define XCHAL_HAVE_BBENEP_SP_VFPU	0       /* sp_vfpu option on BBE-EP */
196 #define XCHAL_HAVE_FLIX3		0	/* basic 3-way FLIX option */
198 #define XCHAL_HAVE_GRIVPEP_HISTOGRAM	0       /* Histogram option on GRIVPEP */
203 #define XCHAL_VISION_QUAD_MAC_TYPE      0     /* quad_mac option on Vision P6 */
204 #define XCHAL_HAVE_VISION_HISTOGRAM     0     /* histogram option on Vision P5/P6 */
205 #define XCHAL_HAVE_VISION_SP_VFPU       0     /* sp_vfpu option on Vision P5/P6/Q6/Q7 */
206 #define XCHAL_HAVE_VISION_SP_VFPU_2XFMAC 0     /* sp_vfpu_2xfma option on Vision Q7 */
207 #define XCHAL_HAVE_VISION_HP_VFPU       0     /* hp_vfpu option on Vision P6/Q6 */
208 #define XCHAL_HAVE_VISION_HP_VFPU_2XFMAC 0     /* hp_vfpu_2xfma option on Vision Q7 */
409 #define XCHAL_HAVE_INTERRUPTS		1	/* interrupt option */
411 #define XCHAL_HAVE_CCOUNT		1	/* CCOUNT reg. (timer option) */
597 #define XCHAL_HAVE_EXCEPTIONS		1	/* exception option */
598 #define XCHAL_HAVE_IMPRECISE_EXCEPTIONS	0	/* imprecise exception option */
600 #define XCHAL_HAVE_HALT			0	/* halt architecture option */
668 #define XCHAL_HAVE_OCD			1	/* OnChipDebug option */
671 #define XCHAL_HAVE_OCD_DIR_ARRAY	0	/* faster OCD option (to LX4) */