xtensa/core-dc232b/core-isa.h

4  * This file is subject to the terms and conditions of the GNU General Public
5  * License.  See the file "COPYING" in the main directory of this archive
19  *  Note:  Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
20  *  configured, and a value of 0 otherwise.  These macros are always defined.
30 #define XCHAL_NUM_AREGS                 32      /* num of physical addr regs */
59 #define XCHAL_NUM_MISC_REGS             2       /* num of scratch regs (0..4) */
78 #define XCHAL_NUM_WRITEBUFFER_ENTRIES   8       /* size of write buffer */
85 #define XCHAL_SW_VERSION                701001  /* sw version of this header */
100 #define XCHAL_HW_VERSION_MAJOR          2210    /* major ver# of targeted hw */
101 #define XCHAL_HW_VERSION_MINOR          1       /* minor ver# of targeted hw */
107 /*  If software targets a *range* of hardware versions, these are the bounds: */
108 #define XCHAL_HW_MIN_VERSION_MAJOR      2210    /* major v of earliest tgt hw */
109 #define XCHAL_HW_MIN_VERSION_MINOR      1       /* minor v of earliest tgt hw */
111 #define XCHAL_HW_MAX_VERSION_MAJOR      2210    /* major v of latest tgt hw */
112 #define XCHAL_HW_MAX_VERSION_MINOR      1       /* minor v of latest tgt hw */
148 /*  Number of cache sets in log2(lines per way):  */
152 /*  Cache set associativity (number of ways):  */
162 /*  Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits):  */
170 #define XCHAL_NUM_INSTROM               0       /* number of core instr. ROMs */
171 #define XCHAL_NUM_INSTRAM               0       /* number of core instr. RAMs */
172 #define XCHAL_NUM_DATAROM               0       /* number of core data ROMs */
173 #define XCHAL_NUM_DATARAM               0       /* number of core data RAMs */
174 #define XCHAL_NUM_URAM                  0       /* number of core unified RAMs*/
175 #define XCHAL_NUM_XLMI                  0       /* number of core XLMI ports */
186 #define XCHAL_NUM_TIMERS                3       /* number of CCOMPAREn regs */
187 #define XCHAL_NUM_INTERRUPTS            22      /* number of interrupts */
189 #define XCHAL_NUM_EXTINTERRUPTS         17      /* num of external interrupts */
190 #define XCHAL_NUM_INTLEVELS             6       /* number of interrupt levels
195 /*  Masks of interrupts at each interrupt level:  */
204 /*  Masks of interrupts at each range 1..n of interrupt levels:  */
213 /*  Level of each interrupt:  */
241 /*  Type of each interrupt:  */
265 /*  Masks of interrupts for each type of interrupt:  */
391 #define XCHAL_NUM_IBREAK                2       /* number of IBREAKn regs */
392 #define XCHAL_NUM_DBREAK                2       /* number of DBREAKn regs */
402 #define XCHAL_HAVE_TLBS                 1       /* inverse of HAVE_CACHEATTR */
411 /*  If none of the above last 4 are set, it's a custom TLB configuration.  */
415 #define XCHAL_MMU_ASID_BITS             8       /* number of bits in ASIDs */
416 #define XCHAL_MMU_RINGS                 4       /* number of rings (1..4) */
417 #define XCHAL_MMU_RING_BITS             2       /* num of bits in RING field */