Lines Matching +full:0 +full:x62
34 #define MASK_OP_MAJOR(op) MASK_BITS_SHIFT(op, 0, 7)
290 OPCM_16_SR_SYSTEM = 0x00,
291 OPCM_16_SR_ACCU = 0x32,
293 OPC1_16_SRC_ADD = 0xc2,
294 OPC1_16_SRC_ADD_A15 = 0x92,
295 OPC1_16_SRC_ADD_15A = 0x9a,
296 OPC1_16_SRR_ADD = 0x42,
297 OPC1_16_SRR_ADD_A15 = 0x12,
298 OPC1_16_SRR_ADD_15A = 0x1a,
299 OPC1_16_SRC_ADD_A = 0xb0,
300 OPC1_16_SRR_ADD_A = 0x30,
301 OPC1_16_SRR_ADDS = 0x22,
302 OPC1_16_SRRS_ADDSC_A = 0x10,
303 OPC1_16_SC_AND = 0x16,
304 OPC1_16_SRR_AND = 0x26,
305 OPC1_16_SC_BISR = 0xe0,
306 OPC1_16_SRC_CADD = 0x8a,
307 OPC1_16_SRC_CADDN = 0xca,
308 OPC1_16_SB_CALL = 0x5c,
309 OPC1_16_SRC_CMOV = 0xaa,
310 OPC1_16_SRR_CMOV = 0x2a,
311 OPC1_16_SRC_CMOVN = 0xea,
312 OPC1_16_SRR_CMOVN = 0x6a,
313 OPC1_16_SRC_EQ = 0xba,
314 OPC1_16_SRR_EQ = 0x3a,
315 OPC1_16_SB_J = 0x3c,
316 OPC1_16_SBC_JEQ = 0x1e,
317 OPC1_16_SBC_JEQ2 = 0x9e,
318 OPC1_16_SBR_JEQ = 0x3e,
319 OPC1_16_SBR_JEQ2 = 0xbe,
320 OPC1_16_SBR_JGEZ = 0xce,
321 OPC1_16_SBR_JGTZ = 0x4e,
322 OPC1_16_SR_JI = 0xdc,
323 OPC1_16_SBR_JLEZ = 0x8e,
324 OPC1_16_SBR_JLTZ = 0x0e,
325 OPC1_16_SBC_JNE = 0x5e,
326 OPC1_16_SBC_JNE2 = 0xde,
327 OPC1_16_SBR_JNE = 0x7e,
328 OPC1_16_SBR_JNE2 = 0xfe,
329 OPC1_16_SB_JNZ = 0xee,
330 OPC1_16_SBR_JNZ = 0xf6,
331 OPC1_16_SBR_JNZ_A = 0x7c,
332 OPC1_16_SBRN_JNZ_T = 0xae,
333 OPC1_16_SB_JZ = 0x6e,
334 OPC1_16_SBR_JZ = 0x76,
335 OPC1_16_SBR_JZ_A = 0xbc,
336 OPC1_16_SBRN_JZ_T = 0x2e,
337 OPC1_16_SC_LD_A = 0xd8,
338 OPC1_16_SLR_LD_A = 0xd4,
339 OPC1_16_SLR_LD_A_POSTINC = 0xc4,
340 OPC1_16_SLRO_LD_A = 0xc8,
341 OPC1_16_SRO_LD_A = 0xcc,
342 OPC1_16_SLR_LD_BU = 0x14,
343 OPC1_16_SLR_LD_BU_POSTINC = 0x04,
344 OPC1_16_SLRO_LD_BU = 0x08,
345 OPC1_16_SRO_LD_BU = 0x0c,
346 OPC1_16_SLR_LD_H = 0x94,
347 OPC1_16_SLR_LD_H_POSTINC = 0x84,
348 OPC1_16_SLRO_LD_H = 0x88,
349 OPC1_16_SRO_LD_H = 0x8c,
350 OPC1_16_SC_LD_W = 0x58,
351 OPC1_16_SLR_LD_W = 0x54,
352 OPC1_16_SLR_LD_W_POSTINC = 0x44,
353 OPC1_16_SLRO_LD_W = 0x48,
354 OPC1_16_SRO_LD_W = 0x4c,
355 OPC1_16_SBR_LOOP = 0xfc,
356 OPC1_16_SRC_LT = 0xfa,
357 OPC1_16_SRR_LT = 0x7a,
358 OPC1_16_SC_MOV = 0xda,
359 OPC1_16_SRC_MOV = 0x82,
360 OPC1_16_SRR_MOV = 0x02,
361 OPC1_16_SRC_MOV_E = 0xd2,/* 1.6 only */
362 OPC1_16_SRC_MOV_A = 0xa0,
363 OPC1_16_SRR_MOV_A = 0x60,
364 OPC1_16_SRR_MOV_AA = 0x40,
365 OPC1_16_SRR_MOV_D = 0x80,
366 OPC1_16_SRR_MUL = 0xe2,
367 OPC1_16_SR_NOT = 0x46,
368 OPC1_16_SC_OR = 0x96,
369 OPC1_16_SRR_OR = 0xa6,
370 OPC1_16_SRC_SH = 0x06,
371 OPC1_16_SRC_SHA = 0x86,
372 OPC1_16_SC_ST_A = 0xf8,
373 OPC1_16_SRO_ST_A = 0xec,
374 OPC1_16_SSR_ST_A = 0xf4,
375 OPC1_16_SSR_ST_A_POSTINC = 0xe4,
376 OPC1_16_SSRO_ST_A = 0xe8,
377 OPC1_16_SRO_ST_B = 0x2c,
378 OPC1_16_SSR_ST_B = 0x34,
379 OPC1_16_SSR_ST_B_POSTINC = 0x24,
380 OPC1_16_SSRO_ST_B = 0x28,
381 OPC1_16_SRO_ST_H = 0xac,
382 OPC1_16_SSR_ST_H = 0xb4,
383 OPC1_16_SSR_ST_H_POSTINC = 0xa4,
384 OPC1_16_SSRO_ST_H = 0xa8,
385 OPC1_16_SC_ST_W = 0x78,
386 OPC1_16_SRO_ST_W = 0x6c,
387 OPC1_16_SSR_ST_W = 0x74,
388 OPC1_16_SSR_ST_W_POSTINC = 0x64,
389 OPC1_16_SSRO_ST_W = 0x68,
390 OPC1_16_SRR_SUB = 0xa2,
391 OPC1_16_SRR_SUB_A15B = 0x52,
392 OPC1_16_SRR_SUB_15AB = 0x5a,
393 OPC1_16_SC_SUB_A = 0x20,
394 OPC1_16_SRR_SUBS = 0x62,
395 OPC1_16_SRR_XOR = 0xc6,
405 OPC2_16_SR_NOP = 0x00,
406 OPC2_16_SR_RET = 0x09,
407 OPC2_16_SR_RFE = 0x08,
408 OPC2_16_SR_DEBUG = 0x0a,
409 OPC2_16_SR_FRET = 0x07,
413 OPC2_16_SR_RSUB = 0x05,
414 OPC2_16_SR_SAT_B = 0x00,
415 OPC2_16_SR_SAT_BU = 0x01,
416 OPC2_16_SR_SAT_H = 0x02,
417 OPC2_16_SR_SAT_HU = 0x03,
425 OPCM_32_ABS_LDW = 0x85,
426 OPCM_32_ABS_LDB = 0x05,
427 OPCM_32_ABS_LDMST_SWAP = 0xe5,
428 OPCM_32_ABS_LDST_CONTEXT = 0x15,
429 OPCM_32_ABS_STORE = 0xa5,
430 OPCM_32_ABS_STOREB_H = 0x25,
431 OPC1_32_ABS_STOREQ = 0x65,
432 OPC1_32_ABS_LD_Q = 0x45,
433 OPCM_32_ABS_LEA_LHA = 0xc5,
435 OPC1_32_ABSB_ST_T = 0xd5,
437 OPC1_32_B_CALL = 0x6d,
438 OPC1_32_B_CALLA = 0xed,
439 OPC1_32_B_FCALL = 0x61,
440 OPC1_32_B_FCALLA = 0xe1,
441 OPC1_32_B_J = 0x1d,
442 OPC1_32_B_JA = 0x9d,
443 OPC1_32_B_JL = 0x5d,
444 OPC1_32_B_JLA = 0xdd,
446 OPCM_32_BIT_ANDACC = 0x47,
447 OPCM_32_BIT_LOGICAL_T1 = 0x87,
448 OPCM_32_BIT_INSERT = 0x67,
449 OPCM_32_BIT_LOGICAL_T2 = 0x07,
450 OPCM_32_BIT_ORAND = 0xc7,
451 OPCM_32_BIT_SH_LOGIC1 = 0x27,
452 OPCM_32_BIT_SH_LOGIC2 = 0xa7,
454 OPCM_32_BO_ADDRMODE_POST_PRE_BASE = 0x89,
455 OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR = 0xa9,
456 OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE = 0x09,
457 OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR = 0x29,
458 OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE = 0x49,
459 OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR = 0x69,
461 OPC1_32_BOL_LD_A_LONGOFF = 0x99,
462 OPC1_32_BOL_LD_W_LONGOFF = 0x19,
463 OPC1_32_BOL_LEA_LONGOFF = 0xd9,
464 OPC1_32_BOL_ST_W_LONGOFF = 0x59,
465 OPC1_32_BOL_ST_A_LONGOFF = 0xb5, /* 1.6 only */
466 OPC1_32_BOL_LD_B_LONGOFF = 0x79, /* 1.6 only */
467 OPC1_32_BOL_LD_BU_LONGOFF = 0x39, /* 1.6 only */
468 OPC1_32_BOL_LD_H_LONGOFF = 0xc9, /* 1.6 only */
469 OPC1_32_BOL_LD_HU_LONGOFF = 0xb9, /* 1.6 only */
470 OPC1_32_BOL_ST_B_LONGOFF = 0xe9, /* 1.6 only */
471 OPC1_32_BOL_ST_H_LONGOFF = 0xf9, /* 1.6 only */
473 OPCM_32_BRC_EQ_NEQ = 0xdf,
474 OPCM_32_BRC_GE = 0xff,
475 OPCM_32_BRC_JLT = 0xbf,
476 OPCM_32_BRC_JNE = 0x9f,
478 OPCM_32_BRN_JTT = 0x6f,
480 OPCM_32_BRR_EQ_NEQ = 0x5f,
481 OPCM_32_BRR_ADDR_EQ_NEQ = 0x7d,
482 OPCM_32_BRR_GE = 0x7f,
483 OPCM_32_BRR_JLT = 0x3f,
484 OPCM_32_BRR_JNE = 0x1f,
485 OPCM_32_BRR_JNZ = 0xbd,
486 OPCM_32_BRR_LOOP = 0xfd,
488 OPCM_32_RC_LOGICAL_SHIFT = 0x8f,
489 OPCM_32_RC_ACCUMULATOR = 0x8b,
490 OPCM_32_RC_SERVICEROUTINE = 0xad,
491 OPCM_32_RC_MUL = 0x53,
493 OPCM_32_RCPW_MASK_INSERT = 0xb7,
495 OPCM_32_RCR_COND_SELECT = 0xab,
496 OPCM_32_RCR_MADD = 0x13,
497 OPCM_32_RCR_MSUB = 0x33,
499 OPC1_32_RCRR_INSERT = 0x97,
501 OPCM_32_RCRW_MASK_INSERT = 0xd7,
503 OPC1_32_RLC_ADDI = 0x1b,
504 OPC1_32_RLC_ADDIH = 0x9b,
505 OPC1_32_RLC_ADDIH_A = 0x11,
506 OPC1_32_RLC_MFCR = 0x4d,
507 OPC1_32_RLC_MOV = 0x3b,
508 OPC1_32_RLC_MOV_64 = 0xfb, /* 1.6 only */
509 OPC1_32_RLC_MOV_U = 0xbb,
510 OPC1_32_RLC_MOV_H = 0x7b,
511 OPC1_32_RLC_MOVH_A = 0x91,
512 OPC1_32_RLC_MTCR = 0xcd,
514 OPCM_32_RR_LOGICAL_SHIFT = 0x0f,
515 OPCM_32_RR_ACCUMULATOR = 0x0b,
516 OPCM_32_RR_ADDRESS = 0x01,
517 OPCM_32_RR_DIVIDE = 0x4b,
518 OPCM_32_RR_IDIRECT = 0x2d,
520 OPCM_32_RR1_MUL = 0xb3,
521 OPCM_32_RR1_MULQ = 0x93,
523 OPCM_32_RR2_MUL = 0x73,
525 OPCM_32_RRPW_EXTRACT_INSERT = 0x37,
526 OPC1_32_RRPW_DEXTR = 0x77,
528 OPCM_32_RRR_COND_SELECT = 0x2b,
529 OPCM_32_RRR_DIVIDE = 0x6b,
531 OPCM_32_RRR1_MADD = 0x83,
532 OPCM_32_RRR1_MADDQ_H = 0x43,
533 OPCM_32_RRR1_MADDSU_H = 0xc3,
534 OPCM_32_RRR1_MSUB_H = 0xa3,
535 OPCM_32_RRR1_MSUB_Q = 0x63,
536 OPCM_32_RRR1_MSUBAD_H = 0xe3,
538 OPCM_32_RRR2_MADD = 0x03,
539 OPCM_32_RRR2_MSUB = 0x23,
541 OPCM_32_RRRR_EXTRACT_INSERT = 0x17,
543 OPCM_32_RRRW_EXTRACT_INSERT = 0x57,
545 OPCM_32_SYS_INTERRUPTS = 0x0d,
546 OPC1_32_SYS_RSTV = 0x2f,
558 OPC2_32_ABS_LD_A = 0x02,
559 OPC2_32_ABS_LD_D = 0x01,
560 OPC2_32_ABS_LD_DA = 0x03,
561 OPC2_32_ABS_LD_W = 0x00,
566 OPC2_32_ABS_LD_B = 0x00,
567 OPC2_32_ABS_LD_BU = 0x01,
568 OPC2_32_ABS_LD_H = 0x02,
569 OPC2_32_ABS_LD_HU = 0x03,
573 OPC2_32_ABS_LDMST = 0x01,
574 OPC2_32_ABS_SWAP_W = 0x00,
578 OPC2_32_ABS_LDLCX = 0x02,
579 OPC2_32_ABS_LDUCX = 0x03,
580 OPC2_32_ABS_STLCX = 0x00,
581 OPC2_32_ABS_STUCX = 0x01,
585 OPC2_32_ABS_ST_A = 0x02,
586 OPC2_32_ABS_ST_D = 0x01,
587 OPC2_32_ABS_ST_DA = 0x03,
588 OPC2_32_ABS_ST_W = 0x00,
592 OPC2_32_ABS_ST_B = 0x00,
593 OPC2_32_ABS_ST_H = 0x02,
598 OPC2_32_ABS_LEA = 0x00,
599 OPC2_32_ABS_LHA = 0x01,
607 OPC2_32_BIT_AND_AND_T = 0x00,
608 OPC2_32_BIT_AND_ANDN_T = 0x03,
609 OPC2_32_BIT_AND_NOR_T = 0x02,
610 OPC2_32_BIT_AND_OR_T = 0x01,
614 OPC2_32_BIT_AND_T = 0x00,
615 OPC2_32_BIT_ANDN_T = 0x03,
616 OPC2_32_BIT_NOR_T = 0x02,
617 OPC2_32_BIT_OR_T = 0x01,
621 OPC2_32_BIT_INS_T = 0x00,
622 OPC2_32_BIT_INSN_T = 0x01,
626 OPC2_32_BIT_NAND_T = 0x00,
627 OPC2_32_BIT_ORN_T = 0x01,
628 OPC2_32_BIT_XNOR_T = 0x02,
629 OPC2_32_BIT_XOR_T = 0x03,
633 OPC2_32_BIT_OR_AND_T = 0x00,
634 OPC2_32_BIT_OR_ANDN_T = 0x03,
635 OPC2_32_BIT_OR_NOR_T = 0x02,
636 OPC2_32_BIT_OR_OR_T = 0x01,
640 OPC2_32_BIT_SH_AND_T = 0x00,
641 OPC2_32_BIT_SH_ANDN_T = 0x03,
642 OPC2_32_BIT_SH_NOR_T = 0x02,
643 OPC2_32_BIT_SH_OR_T = 0x01,
647 OPC2_32_BIT_SH_NAND_T = 0x00,
648 OPC2_32_BIT_SH_ORN_T = 0x01,
649 OPC2_32_BIT_SH_XNOR_T = 0x02,
650 OPC2_32_BIT_SH_XOR_T = 0x03,
657 OPC2_32_BO_CACHEA_I_SHORTOFF = 0x2e,
658 OPC2_32_BO_CACHEA_I_POSTINC = 0x0e,
659 OPC2_32_BO_CACHEA_I_PREINC = 0x1e,
660 OPC2_32_BO_CACHEA_W_SHORTOFF = 0x2c,
661 OPC2_32_BO_CACHEA_W_POSTINC = 0x0c,
662 OPC2_32_BO_CACHEA_W_PREINC = 0x1c,
663 OPC2_32_BO_CACHEA_WI_SHORTOFF = 0x2d,
664 OPC2_32_BO_CACHEA_WI_POSTINC = 0x0d,
665 OPC2_32_BO_CACHEA_WI_PREINC = 0x1d,
667 OPC2_32_BO_CACHEI_W_SHORTOFF = 0x2b,
668 OPC2_32_BO_CACHEI_W_POSTINC = 0x0b,
669 OPC2_32_BO_CACHEI_W_PREINC = 0x1b,
670 OPC2_32_BO_CACHEI_WI_SHORTOFF = 0x2f,
671 OPC2_32_BO_CACHEI_WI_POSTINC = 0x0f,
672 OPC2_32_BO_CACHEI_WI_PREINC = 0x1f,
674 OPC2_32_BO_ST_A_SHORTOFF = 0x26,
675 OPC2_32_BO_ST_A_POSTINC = 0x06,
676 OPC2_32_BO_ST_A_PREINC = 0x16,
677 OPC2_32_BO_ST_B_SHORTOFF = 0x20,
678 OPC2_32_BO_ST_B_POSTINC = 0x00,
679 OPC2_32_BO_ST_B_PREINC = 0x10,
680 OPC2_32_BO_ST_D_SHORTOFF = 0x25,
681 OPC2_32_BO_ST_D_POSTINC = 0x05,
682 OPC2_32_BO_ST_D_PREINC = 0x15,
683 OPC2_32_BO_ST_DA_SHORTOFF = 0x27,
684 OPC2_32_BO_ST_DA_POSTINC = 0x07,
685 OPC2_32_BO_ST_DA_PREINC = 0x17,
686 OPC2_32_BO_ST_H_SHORTOFF = 0x22,
687 OPC2_32_BO_ST_H_POSTINC = 0x02,
688 OPC2_32_BO_ST_H_PREINC = 0x12,
689 OPC2_32_BO_ST_Q_SHORTOFF = 0x28,
690 OPC2_32_BO_ST_Q_POSTINC = 0x08,
691 OPC2_32_BO_ST_Q_PREINC = 0x18,
692 OPC2_32_BO_ST_W_SHORTOFF = 0x24,
693 OPC2_32_BO_ST_W_POSTINC = 0x04,
694 OPC2_32_BO_ST_W_PREINC = 0x14,
698 OPC2_32_BO_CACHEA_I_BR = 0x0e,
699 OPC2_32_BO_CACHEA_I_CIRC = 0x1e,
700 OPC2_32_BO_CACHEA_W_BR = 0x0c,
701 OPC2_32_BO_CACHEA_W_CIRC = 0x1c,
702 OPC2_32_BO_CACHEA_WI_BR = 0x0d,
703 OPC2_32_BO_CACHEA_WI_CIRC = 0x1d,
704 OPC2_32_BO_ST_A_BR = 0x06,
705 OPC2_32_BO_ST_A_CIRC = 0x16,
706 OPC2_32_BO_ST_B_BR = 0x00,
707 OPC2_32_BO_ST_B_CIRC = 0x10,
708 OPC2_32_BO_ST_D_BR = 0x05,
709 OPC2_32_BO_ST_D_CIRC = 0x15,
710 OPC2_32_BO_ST_DA_BR = 0x07,
711 OPC2_32_BO_ST_DA_CIRC = 0x17,
712 OPC2_32_BO_ST_H_BR = 0x02,
713 OPC2_32_BO_ST_H_CIRC = 0x12,
714 OPC2_32_BO_ST_Q_BR = 0x08,
715 OPC2_32_BO_ST_Q_CIRC = 0x18,
716 OPC2_32_BO_ST_W_BR = 0x04,
717 OPC2_32_BO_ST_W_CIRC = 0x14,
721 OPC2_32_BO_LD_A_SHORTOFF = 0x26,
722 OPC2_32_BO_LD_A_POSTINC = 0x06,
723 OPC2_32_BO_LD_A_PREINC = 0x16,
724 OPC2_32_BO_LD_B_SHORTOFF = 0x20,
725 OPC2_32_BO_LD_B_POSTINC = 0x00,
726 OPC2_32_BO_LD_B_PREINC = 0x10,
727 OPC2_32_BO_LD_BU_SHORTOFF = 0x21,
728 OPC2_32_BO_LD_BU_POSTINC = 0x01,
729 OPC2_32_BO_LD_BU_PREINC = 0x11,
730 OPC2_32_BO_LD_D_SHORTOFF = 0x25,
731 OPC2_32_BO_LD_D_POSTINC = 0x05,
732 OPC2_32_BO_LD_D_PREINC = 0x15,
733 OPC2_32_BO_LD_DA_SHORTOFF = 0x27,
734 OPC2_32_BO_LD_DA_POSTINC = 0x07,
735 OPC2_32_BO_LD_DA_PREINC = 0x17,
736 OPC2_32_BO_LD_H_SHORTOFF = 0x22,
737 OPC2_32_BO_LD_H_POSTINC = 0x02,
738 OPC2_32_BO_LD_H_PREINC = 0x12,
739 OPC2_32_BO_LD_HU_SHORTOFF = 0x23,
740 OPC2_32_BO_LD_HU_POSTINC = 0x03,
741 OPC2_32_BO_LD_HU_PREINC = 0x13,
742 OPC2_32_BO_LD_Q_SHORTOFF = 0x28,
743 OPC2_32_BO_LD_Q_POSTINC = 0x08,
744 OPC2_32_BO_LD_Q_PREINC = 0x18,
745 OPC2_32_BO_LD_W_SHORTOFF = 0x24,
746 OPC2_32_BO_LD_W_POSTINC = 0x04,
747 OPC2_32_BO_LD_W_PREINC = 0x14,
751 OPC2_32_BO_LD_A_BR = 0x06,
752 OPC2_32_BO_LD_A_CIRC = 0x16,
753 OPC2_32_BO_LD_B_BR = 0x00,
754 OPC2_32_BO_LD_B_CIRC = 0x10,
755 OPC2_32_BO_LD_BU_BR = 0x01,
756 OPC2_32_BO_LD_BU_CIRC = 0x11,
757 OPC2_32_BO_LD_D_BR = 0x05,
758 OPC2_32_BO_LD_D_CIRC = 0x15,
759 OPC2_32_BO_LD_DA_BR = 0x07,
760 OPC2_32_BO_LD_DA_CIRC = 0x17,
761 OPC2_32_BO_LD_H_BR = 0x02,
762 OPC2_32_BO_LD_H_CIRC = 0x12,
763 OPC2_32_BO_LD_HU_BR = 0x03,
764 OPC2_32_BO_LD_HU_CIRC = 0x13,
765 OPC2_32_BO_LD_Q_BR = 0x08,
766 OPC2_32_BO_LD_Q_CIRC = 0x18,
767 OPC2_32_BO_LD_W_BR = 0x04,
768 OPC2_32_BO_LD_W_CIRC = 0x14,
772 OPC2_32_BO_LDLCX_SHORTOFF = 0x24,
773 OPC2_32_BO_LDMST_SHORTOFF = 0x21,
774 OPC2_32_BO_LDMST_POSTINC = 0x01,
775 OPC2_32_BO_LDMST_PREINC = 0x11,
776 OPC2_32_BO_LDUCX_SHORTOFF = 0x25,
777 OPC2_32_BO_LEA_SHORTOFF = 0x28,
778 OPC2_32_BO_STLCX_SHORTOFF = 0x26,
779 OPC2_32_BO_STUCX_SHORTOFF = 0x27,
780 OPC2_32_BO_SWAP_W_SHORTOFF = 0x20,
781 OPC2_32_BO_SWAP_W_POSTINC = 0x00,
782 OPC2_32_BO_SWAP_W_PREINC = 0x10,
783 OPC2_32_BO_CMPSWAP_W_SHORTOFF = 0x23,
784 OPC2_32_BO_CMPSWAP_W_POSTINC = 0x03,
785 OPC2_32_BO_CMPSWAP_W_PREINC = 0x13,
786 OPC2_32_BO_SWAPMSK_W_SHORTOFF = 0x22,
787 OPC2_32_BO_SWAPMSK_W_POSTINC = 0x02,
788 OPC2_32_BO_SWAPMSK_W_PREINC = 0x12,
792 OPC2_32_BO_LDMST_BR = 0x01,
793 OPC2_32_BO_LDMST_CIRC = 0x11,
794 OPC2_32_BO_SWAP_W_BR = 0x00,
795 OPC2_32_BO_SWAP_W_CIRC = 0x10,
796 OPC2_32_BO_CMPSWAP_W_BR = 0x03,
797 OPC2_32_BO_CMPSWAP_W_CIRC = 0x13,
798 OPC2_32_BO_SWAPMSK_W_BR = 0x02,
799 OPC2_32_BO_SWAPMSK_W_CIRC = 0x12,
806 OPC2_32_BRC_JEQ = 0x00,
807 OPC2_32_BRC_JNE = 0x01,
811 OP2_32_BRC_JGE = 0x00,
812 OPC_32_BRC_JGE_U = 0x01,
816 OPC2_32_BRC_JLT = 0x00,
817 OPC2_32_BRC_JLT_U = 0x01,
821 OPC2_32_BRC_JNED = 0x01,
822 OPC2_32_BRC_JNEI = 0x00,
829 OPC2_32_BRN_JNZ_T = 0x01,
830 OPC2_32_BRN_JZ_T = 0x00,
837 OPC2_32_BRR_JEQ = 0x00,
838 OPC2_32_BRR_JNE = 0x01,
842 OPC2_32_BRR_JEQ_A = 0x00,
843 OPC2_32_BRR_JNE_A = 0x01,
847 OPC2_32_BRR_JGE = 0x00,
848 OPC2_32_BRR_JGE_U = 0x01,
852 OPC2_32_BRR_JLT = 0x00,
853 OPC2_32_BRR_JLT_U = 0x01,
857 OPC2_32_BRR_JNED = 0x01,
858 OPC2_32_BRR_JNEI = 0x00,
862 OPC2_32_BRR_JNZ_A = 0x01,
863 OPC2_32_BRR_JZ_A = 0x00,
867 OPC2_32_BRR_LOOP = 0x00,
868 OPC2_32_BRR_LOOPU = 0x01,
875 OPC2_32_RC_AND = 0x08,
876 OPC2_32_RC_ANDN = 0x0e,
877 OPC2_32_RC_NAND = 0x09,
878 OPC2_32_RC_NOR = 0x0b,
879 OPC2_32_RC_OR = 0x0a,
880 OPC2_32_RC_ORN = 0x0f,
881 OPC2_32_RC_SH = 0x00,
882 OPC2_32_RC_SH_H = 0x40,
883 OPC2_32_RC_SHA = 0x01,
884 OPC2_32_RC_SHA_H = 0x41,
885 OPC2_32_RC_SHAS = 0x02,
886 OPC2_32_RC_XNOR = 0x0d,
887 OPC2_32_RC_XOR = 0x0c,
888 OPC2_32_RC_SHUFFLE = 0x07, /* v1.6.2 only */
892 OPC2_32_RC_ABSDIF = 0x0e,
893 OPC2_32_RC_ABSDIFS = 0x0f,
894 OPC2_32_RC_ADD = 0x00,
895 OPC2_32_RC_ADDC = 0x05,
896 OPC2_32_RC_ADDS = 0x02,
897 OPC2_32_RC_ADDS_U = 0x03,
898 OPC2_32_RC_ADDX = 0x04,
899 OPC2_32_RC_AND_EQ = 0x20,
900 OPC2_32_RC_AND_GE = 0x24,
901 OPC2_32_RC_AND_GE_U = 0x25,
902 OPC2_32_RC_AND_LT = 0x22,
903 OPC2_32_RC_AND_LT_U = 0x23,
904 OPC2_32_RC_AND_NE = 0x21,
905 OPC2_32_RC_EQ = 0x10,
906 OPC2_32_RC_EQANY_B = 0x56,
907 OPC2_32_RC_EQANY_H = 0x76,
908 OPC2_32_RC_GE = 0x14,
909 OPC2_32_RC_GE_U = 0x15,
910 OPC2_32_RC_LT = 0x12,
911 OPC2_32_RC_LT_U = 0x13,
912 OPC2_32_RC_MAX = 0x1a,
913 OPC2_32_RC_MAX_U = 0x1b,
914 OPC2_32_RC_MIN = 0x18,
915 OPC2_32_RC_MIN_U = 0x19,
916 OPC2_32_RC_NE = 0x11,
917 OPC2_32_RC_OR_EQ = 0x27,
918 OPC2_32_RC_OR_GE = 0x2b,
919 OPC2_32_RC_OR_GE_U = 0x2c,
920 OPC2_32_RC_OR_LT = 0x29,
921 OPC2_32_RC_OR_LT_U = 0x2a,
922 OPC2_32_RC_OR_NE = 0x28,
923 OPC2_32_RC_RSUB = 0x08,
924 OPC2_32_RC_RSUBS = 0x0a,
925 OPC2_32_RC_RSUBS_U = 0x0b,
926 OPC2_32_RC_SH_EQ = 0x37,
927 OPC2_32_RC_SH_GE = 0x3b,
928 OPC2_32_RC_SH_GE_U = 0x3c,
929 OPC2_32_RC_SH_LT = 0x39,
930 OPC2_32_RC_SH_LT_U = 0x3a,
931 OPC2_32_RC_SH_NE = 0x38,
932 OPC2_32_RC_XOR_EQ = 0x2f,
933 OPC2_32_RC_XOR_GE = 0x33,
934 OPC2_32_RC_XOR_GE_U = 0x34,
935 OPC2_32_RC_XOR_LT = 0x31,
936 OPC2_32_RC_XOR_LT_U = 0x32,
937 OPC2_32_RC_XOR_NE = 0x30,
941 OPC2_32_RC_BISR = 0x00,
942 OPC2_32_RC_SYSCALL = 0x04,
946 OPC2_32_RC_MUL_32 = 0x01,
947 OPC2_32_RC_MUL_64 = 0x03,
948 OPC2_32_RC_MULS_32 = 0x05,
949 OPC2_32_RC_MUL_U_64 = 0x02,
950 OPC2_32_RC_MULS_U_32 = 0x04,
957 OPC2_32_RCPW_IMASK = 0x01,
958 OPC2_32_RCPW_INSERT = 0x00,
965 OPC2_32_RCR_CADD = 0x00,
966 OPC2_32_RCR_CADDN = 0x01,
967 OPC2_32_RCR_SEL = 0x04,
968 OPC2_32_RCR_SELN = 0x05,
972 OPC2_32_RCR_MADD_32 = 0x01,
973 OPC2_32_RCR_MADD_64 = 0x03,
974 OPC2_32_RCR_MADDS_32 = 0x05,
975 OPC2_32_RCR_MADDS_64 = 0x07,
976 OPC2_32_RCR_MADD_U_64 = 0x02,
977 OPC2_32_RCR_MADDS_U_32 = 0x04,
978 OPC2_32_RCR_MADDS_U_64 = 0x06,
982 OPC2_32_RCR_MSUB_32 = 0x01,
983 OPC2_32_RCR_MSUB_64 = 0x03,
984 OPC2_32_RCR_MSUBS_32 = 0x05,
985 OPC2_32_RCR_MSUBS_64 = 0x07,
986 OPC2_32_RCR_MSUB_U_64 = 0x02,
987 OPC2_32_RCR_MSUBS_U_32 = 0x04,
988 OPC2_32_RCR_MSUBS_U_64 = 0x06,
995 OPC2_32_RCRW_IMASK = 0x01,
996 OPC2_32_RCRW_INSERT = 0x00,
1004 OPC2_32_RR_AND = 0x08,
1005 OPC2_32_RR_ANDN = 0x0e,
1006 OPC2_32_RR_CLO = 0x1c,
1007 OPC2_32_RR_CLO_H = 0x7d,
1008 OPC2_32_RR_CLS = 0x1d,
1009 OPC2_32_RR_CLS_H = 0x7e,
1010 OPC2_32_RR_CLZ = 0x1b,
1011 OPC2_32_RR_CLZ_H = 0x7c,
1012 OPC2_32_RR_NAND = 0x09,
1013 OPC2_32_RR_NOR = 0x0b,
1014 OPC2_32_RR_OR = 0x0a,
1015 OPC2_32_RR_ORN = 0x0f,
1016 OPC2_32_RR_SH = 0x00,
1017 OPC2_32_RR_SH_H = 0x40,
1018 OPC2_32_RR_SHA = 0x01,
1019 OPC2_32_RR_SHA_H = 0x41,
1020 OPC2_32_RR_SHAS = 0x02,
1021 OPC2_32_RR_XNOR = 0x0d,
1022 OPC2_32_RR_XOR = 0x0c,
1026 OPC2_32_RR_ABS = 0x1c,
1027 OPC2_32_RR_ABS_B = 0x5c,
1028 OPC2_32_RR_ABS_H = 0x7c,
1029 OPC2_32_RR_ABSDIF = 0x0e,
1030 OPC2_32_RR_ABSDIF_B = 0x4e,
1031 OPC2_32_RR_ABSDIF_H = 0x6e,
1032 OPC2_32_RR_ABSDIFS = 0x0f,
1033 OPC2_32_RR_ABSDIFS_H = 0x6f,
1034 OPC2_32_RR_ABSS = 0x1d,
1035 OPC2_32_RR_ABSS_H = 0x7d,
1036 OPC2_32_RR_ADD = 0x00,
1037 OPC2_32_RR_ADD_B = 0x40,
1038 OPC2_32_RR_ADD_H = 0x60,
1039 OPC2_32_RR_ADDC = 0x05,
1040 OPC2_32_RR_ADDS = 0x02,
1041 OPC2_32_RR_ADDS_H = 0x62,
1042 OPC2_32_RR_ADDS_HU = 0x63,
1043 OPC2_32_RR_ADDS_U = 0x03,
1044 OPC2_32_RR_ADDX = 0x04,
1045 OPC2_32_RR_AND_EQ = 0x20,
1046 OPC2_32_RR_AND_GE = 0x24,
1047 OPC2_32_RR_AND_GE_U = 0x25,
1048 OPC2_32_RR_AND_LT = 0x22,
1049 OPC2_32_RR_AND_LT_U = 0x23,
1050 OPC2_32_RR_AND_NE = 0x21,
1051 OPC2_32_RR_EQ = 0x10,
1052 OPC2_32_RR_EQ_B = 0x50,
1053 OPC2_32_RR_EQ_H = 0x70,
1054 OPC2_32_RR_EQ_W = 0x90,
1055 OPC2_32_RR_EQANY_B = 0x56,
1056 OPC2_32_RR_EQANY_H = 0x76,
1057 OPC2_32_RR_GE = 0x14,
1058 OPC2_32_RR_GE_U = 0x15,
1059 OPC2_32_RR_LT = 0x12,
1060 OPC2_32_RR_LT_U = 0x13,
1061 OPC2_32_RR_LT_B = 0x52,
1062 OPC2_32_RR_LT_BU = 0x53,
1063 OPC2_32_RR_LT_H = 0x72,
1064 OPC2_32_RR_LT_HU = 0x73,
1065 OPC2_32_RR_LT_W = 0x92,
1066 OPC2_32_RR_LT_WU = 0x93,
1067 OPC2_32_RR_MAX = 0x1a,
1068 OPC2_32_RR_MAX_U = 0x1b,
1069 OPC2_32_RR_MAX_B = 0x5a,
1070 OPC2_32_RR_MAX_BU = 0x5b,
1071 OPC2_32_RR_MAX_H = 0x7a,
1072 OPC2_32_RR_MAX_HU = 0x7b,
1073 OPC2_32_RR_MIN = 0x18,
1074 OPC2_32_RR_MIN_U = 0x19,
1075 OPC2_32_RR_MIN_B = 0x58,
1076 OPC2_32_RR_MIN_BU = 0x59,
1077 OPC2_32_RR_MIN_H = 0x78,
1078 OPC2_32_RR_MIN_HU = 0x79,
1079 OPC2_32_RR_MOV = 0x1f,
1080 OPC2_32_RR_MOVS_64 = 0x80,
1081 OPC2_32_RR_MOV_64 = 0x81,
1082 OPC2_32_RR_NE = 0x11,
1083 OPC2_32_RR_OR_EQ = 0x27,
1084 OPC2_32_RR_OR_GE = 0x2b,
1085 OPC2_32_RR_OR_GE_U = 0x2c,
1086 OPC2_32_RR_OR_LT = 0x29,
1087 OPC2_32_RR_OR_LT_U = 0x2a,
1088 OPC2_32_RR_OR_NE = 0x28,
1089 OPC2_32_RR_SAT_B = 0x5e,
1090 OPC2_32_RR_SAT_BU = 0x5f,
1091 OPC2_32_RR_SAT_H = 0x7e,
1092 OPC2_32_RR_SAT_HU = 0x7f,
1093 OPC2_32_RR_SH_EQ = 0x37,
1094 OPC2_32_RR_SH_GE = 0x3b,
1095 OPC2_32_RR_SH_GE_U = 0x3c,
1096 OPC2_32_RR_SH_LT = 0x39,
1097 OPC2_32_RR_SH_LT_U = 0x3a,
1098 OPC2_32_RR_SH_NE = 0x38,
1099 OPC2_32_RR_SUB = 0x08,
1100 OPC2_32_RR_SUB_B = 0x48,
1101 OPC2_32_RR_SUB_H = 0x68,
1102 OPC2_32_RR_SUBC = 0x0d,
1103 OPC2_32_RR_SUBS = 0x0a,
1104 OPC2_32_RR_SUBS_U = 0x0b,
1105 OPC2_32_RR_SUBS_H = 0x6a,
1106 OPC2_32_RR_SUBS_HU = 0x6b,
1107 OPC2_32_RR_SUBX = 0x0c,
1108 OPC2_32_RR_XOR_EQ = 0x2f,
1109 OPC2_32_RR_XOR_GE = 0x33,
1110 OPC2_32_RR_XOR_GE_U = 0x34,
1111 OPC2_32_RR_XOR_LT = 0x31,
1112 OPC2_32_RR_XOR_LT_U = 0x32,
1113 OPC2_32_RR_XOR_NE = 0x30,
1117 OPC2_32_RR_ADD_A = 0x01,
1118 OPC2_32_RR_ADDSC_A = 0x60,
1119 OPC2_32_RR_ADDSC_AT = 0x62,
1120 OPC2_32_RR_EQ_A = 0x40,
1121 OPC2_32_RR_EQZ = 0x48,
1122 OPC2_32_RR_GE_A = 0x43,
1123 OPC2_32_RR_LT_A = 0x42,
1124 OPC2_32_RR_MOV_A = 0x63,
1125 OPC2_32_RR_MOV_AA = 0x00,
1126 OPC2_32_RR_MOV_D = 0x4c,
1127 OPC2_32_RR_NE_A = 0x41,
1128 OPC2_32_RR_NEZ_A = 0x49,
1129 OPC2_32_RR_SUB_A = 0x02,
1133 OPC2_32_RR_BMERGE = 0x01,
1134 OPC2_32_RR_BSPLIT = 0x09,
1135 OPC2_32_RR_DVINIT_B = 0x5a,
1136 OPC2_32_RR_DVINIT_BU = 0x4a,
1137 OPC2_32_RR_DVINIT_H = 0x3a,
1138 OPC2_32_RR_DVINIT_HU = 0x2a,
1139 OPC2_32_RR_DVINIT = 0x1a,
1140 OPC2_32_RR_DVINIT_U = 0x0a,
1141 OPC2_32_RR_PARITY = 0x02,
1142 OPC2_32_RR_UNPACK = 0x08,
1143 OPC2_32_RR_CRC32 = 0x03, /* CRC32B.W in 1.6.2 */
1144 OPC2_32_RR_CRC32_B = 0x06, /* 1.6.2 only */
1145 OPC2_32_RR_CRC32L_W = 0x07, /* 1.6.2 only */
1146 OPC2_32_RR_POPCNT_W = 0x22, /* 1.6.2 only */
1147 OPC2_32_RR_DIV = 0x20,
1148 OPC2_32_RR_DIV_U = 0x21,
1149 OPC2_32_RR_MUL_F = 0x04,
1150 OPC2_32_RR_DIV_F = 0x05,
1151 OPC2_32_RR_FTOI = 0x10,
1152 OPC2_32_RR_ITOF = 0x14,
1153 OPC2_32_RR_CMP_F = 0x00,
1154 OPC2_32_RR_FTOIZ = 0x13,
1155 OPC2_32_RR_FTOHP = 0x25, /* 1.6.2 only */
1156 OPC2_32_RR_HPTOF = 0x24, /* 1.6.2 only */
1157 OPC2_32_RR_FTOQ31 = 0x11,
1158 OPC2_32_RR_FTOQ31Z = 0x18,
1159 OPC2_32_RR_FTOU = 0x12,
1160 OPC2_32_RR_FTOUZ = 0x17,
1161 OPC2_32_RR_Q31TOF = 0x15,
1162 OPC2_32_RR_QSEED_F = 0x19,
1163 OPC2_32_RR_UPDFL = 0x0c,
1164 OPC2_32_RR_UTOF = 0x16,
1168 OPC2_32_RR_JI = 0x03,
1169 OPC2_32_RR_JLI = 0x02,
1170 OPC2_32_RR_CALLI = 0x00,
1171 OPC2_32_RR_FCALLI = 0x01,
1178 OPC2_32_RR1_MUL_H_32_LL = 0x1a,
1179 OPC2_32_RR1_MUL_H_32_LU = 0x19,
1180 OPC2_32_RR1_MUL_H_32_UL = 0x18,
1181 OPC2_32_RR1_MUL_H_32_UU = 0x1b,
1182 OPC2_32_RR1_MULM_H_64_LL = 0x1e,
1183 OPC2_32_RR1_MULM_H_64_LU = 0x1d,
1184 OPC2_32_RR1_MULM_H_64_UL = 0x1c,
1185 OPC2_32_RR1_MULM_H_64_UU = 0x1f,
1186 OPC2_32_RR1_MULR_H_16_LL = 0x0e,
1187 OPC2_32_RR1_MULR_H_16_LU = 0x0d,
1188 OPC2_32_RR1_MULR_H_16_UL = 0x0c,
1189 OPC2_32_RR1_MULR_H_16_UU = 0x0f,
1193 OPC2_32_RR1_MUL_Q_32 = 0x02,
1194 OPC2_32_RR1_MUL_Q_64 = 0x1b,
1195 OPC2_32_RR1_MUL_Q_32_L = 0x01,
1196 OPC2_32_RR1_MUL_Q_64_L = 0x19,
1197 OPC2_32_RR1_MUL_Q_32_U = 0x00,
1198 OPC2_32_RR1_MUL_Q_64_U = 0x18,
1199 OPC2_32_RR1_MUL_Q_32_LL = 0x05,
1200 OPC2_32_RR1_MUL_Q_32_UU = 0x04,
1201 OPC2_32_RR1_MULR_Q_32_L = 0x07,
1202 OPC2_32_RR1_MULR_Q_32_U = 0x06,
1209 OPC2_32_RR2_MUL_32 = 0x0a,
1210 OPC2_32_RR2_MUL_64 = 0x6a,
1211 OPC2_32_RR2_MULS_32 = 0x8a,
1212 OPC2_32_RR2_MUL_U_64 = 0x68,
1213 OPC2_32_RR2_MULS_U_32 = 0x88,
1221 OPC2_32_RRPW_EXTR = 0x02,
1222 OPC2_32_RRPW_EXTR_U = 0x03,
1223 OPC2_32_RRPW_IMASK = 0x01,
1224 OPC2_32_RRPW_INSERT = 0x00,
1231 OPC2_32_RRR_CADD = 0x00,
1232 OPC2_32_RRR_CADDN = 0x01,
1233 OPC2_32_RRR_CSUB = 0x02,
1234 OPC2_32_RRR_CSUBN = 0x03,
1235 OPC2_32_RRR_SEL = 0x04,
1236 OPC2_32_RRR_SELN = 0x05,
1240 OPC2_32_RRR_DVADJ = 0x0d,
1241 OPC2_32_RRR_DVSTEP = 0x0f,
1242 OPC2_32_RRR_DVSTEP_U = 0x0e,
1243 OPC2_32_RRR_IXMAX = 0x0a,
1244 OPC2_32_RRR_IXMAX_U = 0x0b,
1245 OPC2_32_RRR_IXMIN = 0x08,
1246 OPC2_32_RRR_IXMIN_U = 0x09,
1247 OPC2_32_RRR_PACK = 0x00,
1248 OPC2_32_RRR_ADD_F = 0x02,
1249 OPC2_32_RRR_SUB_F = 0x03,
1250 OPC2_32_RRR_MADD_F = 0x06,
1251 OPC2_32_RRR_MSUB_F = 0x07,
1252 OPC2_32_RRR_CRCN = 0x01, /* 1.6.2 up */
1259 OPC2_32_RRR1_MADD_H_LL = 0x1a,
1260 OPC2_32_RRR1_MADD_H_LU = 0x19,
1261 OPC2_32_RRR1_MADD_H_UL = 0x18,
1262 OPC2_32_RRR1_MADD_H_UU = 0x1b,
1263 OPC2_32_RRR1_MADDS_H_LL = 0x3a,
1264 OPC2_32_RRR1_MADDS_H_LU = 0x39,
1265 OPC2_32_RRR1_MADDS_H_UL = 0x38,
1266 OPC2_32_RRR1_MADDS_H_UU = 0x3b,
1267 OPC2_32_RRR1_MADDM_H_LL = 0x1e,
1268 OPC2_32_RRR1_MADDM_H_LU = 0x1d,
1269 OPC2_32_RRR1_MADDM_H_UL = 0x1c,
1270 OPC2_32_RRR1_MADDM_H_UU = 0x1f,
1271 OPC2_32_RRR1_MADDMS_H_LL = 0x3e,
1272 OPC2_32_RRR1_MADDMS_H_LU = 0x3d,
1273 OPC2_32_RRR1_MADDMS_H_UL = 0x3c,
1274 OPC2_32_RRR1_MADDMS_H_UU = 0x3f,
1275 OPC2_32_RRR1_MADDR_H_LL = 0x0e,
1276 OPC2_32_RRR1_MADDR_H_LU = 0x0d,
1277 OPC2_32_RRR1_MADDR_H_UL = 0x0c,
1278 OPC2_32_RRR1_MADDR_H_UU = 0x0f,
1279 OPC2_32_RRR1_MADDRS_H_LL = 0x2e,
1280 OPC2_32_RRR1_MADDRS_H_LU = 0x2d,
1281 OPC2_32_RRR1_MADDRS_H_UL = 0x2c,
1282 OPC2_32_RRR1_MADDRS_H_UU = 0x2f,
1286 OPC2_32_RRR1_MADD_Q_32 = 0x02,
1287 OPC2_32_RRR1_MADD_Q_64 = 0x1b,
1288 OPC2_32_RRR1_MADD_Q_32_L = 0x01,
1289 OPC2_32_RRR1_MADD_Q_64_L = 0x19,
1290 OPC2_32_RRR1_MADD_Q_32_U = 0x00,
1291 OPC2_32_RRR1_MADD_Q_64_U = 0x18,
1292 OPC2_32_RRR1_MADD_Q_32_LL = 0x05,
1293 OPC2_32_RRR1_MADD_Q_64_LL = 0x1d,
1294 OPC2_32_RRR1_MADD_Q_32_UU = 0x04,
1295 OPC2_32_RRR1_MADD_Q_64_UU = 0x1c,
1296 OPC2_32_RRR1_MADDS_Q_32 = 0x22,
1297 OPC2_32_RRR1_MADDS_Q_64 = 0x3b,
1298 OPC2_32_RRR1_MADDS_Q_32_L = 0x21,
1299 OPC2_32_RRR1_MADDS_Q_64_L = 0x39,
1300 OPC2_32_RRR1_MADDS_Q_32_U = 0x20,
1301 OPC2_32_RRR1_MADDS_Q_64_U = 0x38,
1302 OPC2_32_RRR1_MADDS_Q_32_LL = 0x25,
1303 OPC2_32_RRR1_MADDS_Q_64_LL = 0x3d,
1304 OPC2_32_RRR1_MADDS_Q_32_UU = 0x24,
1305 OPC2_32_RRR1_MADDS_Q_64_UU = 0x3c,
1306 OPC2_32_RRR1_MADDR_H_64_UL = 0x1e,
1307 OPC2_32_RRR1_MADDRS_H_64_UL = 0x3e,
1308 OPC2_32_RRR1_MADDR_Q_32_LL = 0x07,
1309 OPC2_32_RRR1_MADDR_Q_32_UU = 0x06,
1310 OPC2_32_RRR1_MADDRS_Q_32_LL = 0x27,
1311 OPC2_32_RRR1_MADDRS_Q_32_UU = 0x26,
1315 OPC2_32_RRR1_MADDSU_H_32_LL = 0x1a,
1316 OPC2_32_RRR1_MADDSU_H_32_LU = 0x19,
1317 OPC2_32_RRR1_MADDSU_H_32_UL = 0x18,
1318 OPC2_32_RRR1_MADDSU_H_32_UU = 0x1b,
1319 OPC2_32_RRR1_MADDSUS_H_32_LL = 0x3a,
1320 OPC2_32_RRR1_MADDSUS_H_32_LU = 0x39,
1321 OPC2_32_RRR1_MADDSUS_H_32_UL = 0x38,
1322 OPC2_32_RRR1_MADDSUS_H_32_UU = 0x3b,
1323 OPC2_32_RRR1_MADDSUM_H_64_LL = 0x1e,
1324 OPC2_32_RRR1_MADDSUM_H_64_LU = 0x1d,
1325 OPC2_32_RRR1_MADDSUM_H_64_UL = 0x1c,
1326 OPC2_32_RRR1_MADDSUM_H_64_UU = 0x1f,
1327 OPC2_32_RRR1_MADDSUMS_H_64_LL = 0x3e,
1328 OPC2_32_RRR1_MADDSUMS_H_64_LU = 0x3d,
1329 OPC2_32_RRR1_MADDSUMS_H_64_UL = 0x3c,
1330 OPC2_32_RRR1_MADDSUMS_H_64_UU = 0x3f,
1331 OPC2_32_RRR1_MADDSUR_H_16_LL = 0x0e,
1332 OPC2_32_RRR1_MADDSUR_H_16_LU = 0x0d,
1333 OPC2_32_RRR1_MADDSUR_H_16_UL = 0x0c,
1334 OPC2_32_RRR1_MADDSUR_H_16_UU = 0x0f,
1335 OPC2_32_RRR1_MADDSURS_H_16_LL = 0x2e,
1336 OPC2_32_RRR1_MADDSURS_H_16_LU = 0x2d,
1337 OPC2_32_RRR1_MADDSURS_H_16_UL = 0x2c,
1338 OPC2_32_RRR1_MADDSURS_H_16_UU = 0x2f,
1342 OPC2_32_RRR1_MSUB_H_LL = 0x1a,
1343 OPC2_32_RRR1_MSUB_H_LU = 0x19,
1344 OPC2_32_RRR1_MSUB_H_UL = 0x18,
1345 OPC2_32_RRR1_MSUB_H_UU = 0x1b,
1346 OPC2_32_RRR1_MSUBS_H_LL = 0x3a,
1347 OPC2_32_RRR1_MSUBS_H_LU = 0x39,
1348 OPC2_32_RRR1_MSUBS_H_UL = 0x38,
1349 OPC2_32_RRR1_MSUBS_H_UU = 0x3b,
1350 OPC2_32_RRR1_MSUBM_H_LL = 0x1e,
1351 OPC2_32_RRR1_MSUBM_H_LU = 0x1d,
1352 OPC2_32_RRR1_MSUBM_H_UL = 0x1c,
1353 OPC2_32_RRR1_MSUBM_H_UU = 0x1f,
1354 OPC2_32_RRR1_MSUBMS_H_LL = 0x3e,
1355 OPC2_32_RRR1_MSUBMS_H_LU = 0x3d,
1356 OPC2_32_RRR1_MSUBMS_H_UL = 0x3c,
1357 OPC2_32_RRR1_MSUBMS_H_UU = 0x3f,
1358 OPC2_32_RRR1_MSUBR_H_LL = 0x0e,
1359 OPC2_32_RRR1_MSUBR_H_LU = 0x0d,
1360 OPC2_32_RRR1_MSUBR_H_UL = 0x0c,
1361 OPC2_32_RRR1_MSUBR_H_UU = 0x0f,
1362 OPC2_32_RRR1_MSUBRS_H_LL = 0x2e,
1363 OPC2_32_RRR1_MSUBRS_H_LU = 0x2d,
1364 OPC2_32_RRR1_MSUBRS_H_UL = 0x2c,
1365 OPC2_32_RRR1_MSUBRS_H_UU = 0x2f,
1369 OPC2_32_RRR1_MSUB_Q_32 = 0x02,
1370 OPC2_32_RRR1_MSUB_Q_64 = 0x1b,
1371 OPC2_32_RRR1_MSUB_Q_32_L = 0x01,
1372 OPC2_32_RRR1_MSUB_Q_64_L = 0x19,
1373 OPC2_32_RRR1_MSUB_Q_32_U = 0x00,
1374 OPC2_32_RRR1_MSUB_Q_64_U = 0x18,
1375 OPC2_32_RRR1_MSUB_Q_32_LL = 0x05,
1376 OPC2_32_RRR1_MSUB_Q_64_LL = 0x1d,
1377 OPC2_32_RRR1_MSUB_Q_32_UU = 0x04,
1378 OPC2_32_RRR1_MSUB_Q_64_UU = 0x1c,
1379 OPC2_32_RRR1_MSUBS_Q_32 = 0x22,
1380 OPC2_32_RRR1_MSUBS_Q_64 = 0x3b,
1381 OPC2_32_RRR1_MSUBS_Q_32_L = 0x21,
1382 OPC2_32_RRR1_MSUBS_Q_64_L = 0x39,
1383 OPC2_32_RRR1_MSUBS_Q_32_U = 0x20,
1384 OPC2_32_RRR1_MSUBS_Q_64_U = 0x38,
1385 OPC2_32_RRR1_MSUBS_Q_32_LL = 0x25,
1386 OPC2_32_RRR1_MSUBS_Q_64_LL = 0x3d,
1387 OPC2_32_RRR1_MSUBS_Q_32_UU = 0x24,
1388 OPC2_32_RRR1_MSUBS_Q_64_UU = 0x3c,
1389 OPC2_32_RRR1_MSUBR_H_64_UL = 0x1e,
1390 OPC2_32_RRR1_MSUBRS_H_64_UL = 0x3e,
1391 OPC2_32_RRR1_MSUBR_Q_32_LL = 0x07,
1392 OPC2_32_RRR1_MSUBR_Q_32_UU = 0x06,
1393 OPC2_32_RRR1_MSUBRS_Q_32_LL = 0x27,
1394 OPC2_32_RRR1_MSUBRS_Q_32_UU = 0x26,
1398 OPC2_32_RRR1_MSUBAD_H_32_LL = 0x1a,
1399 OPC2_32_RRR1_MSUBAD_H_32_LU = 0x19,
1400 OPC2_32_RRR1_MSUBAD_H_32_UL = 0x18,
1401 OPC2_32_RRR1_MSUBAD_H_32_UU = 0x1b,
1402 OPC2_32_RRR1_MSUBADS_H_32_LL = 0x3a,
1403 OPC2_32_RRR1_MSUBADS_H_32_LU = 0x39,
1404 OPC2_32_RRR1_MSUBADS_H_32_UL = 0x38,
1405 OPC2_32_RRR1_MSUBADS_H_32_UU = 0x3b,
1406 OPC2_32_RRR1_MSUBADM_H_64_LL = 0x1e,
1407 OPC2_32_RRR1_MSUBADM_H_64_LU = 0x1d,
1408 OPC2_32_RRR1_MSUBADM_H_64_UL = 0x1c,
1409 OPC2_32_RRR1_MSUBADM_H_64_UU = 0x1f,
1410 OPC2_32_RRR1_MSUBADMS_H_64_LL = 0x3e,
1411 OPC2_32_RRR1_MSUBADMS_H_64_LU = 0x3d,
1412 OPC2_32_RRR1_MSUBADMS_H_64_UL = 0x3c,
1413 OPC2_32_RRR1_MSUBADMS_H_64_UU = 0x3f,
1414 OPC2_32_RRR1_MSUBADR_H_16_LL = 0x0e,
1415 OPC2_32_RRR1_MSUBADR_H_16_LU = 0x0d,
1416 OPC2_32_RRR1_MSUBADR_H_16_UL = 0x0c,
1417 OPC2_32_RRR1_MSUBADR_H_16_UU = 0x0f,
1418 OPC2_32_RRR1_MSUBADRS_H_16_LL = 0x2e,
1419 OPC2_32_RRR1_MSUBADRS_H_16_LU = 0x2d,
1420 OPC2_32_RRR1_MSUBADRS_H_16_UL = 0x2c,
1421 OPC2_32_RRR1_MSUBADRS_H_16_UU = 0x2f,
1428 OPC2_32_RRR2_MADD_32 = 0x0a,
1429 OPC2_32_RRR2_MADD_64 = 0x6a,
1430 OPC2_32_RRR2_MADDS_32 = 0x8a,
1431 OPC2_32_RRR2_MADDS_64 = 0xea,
1432 OPC2_32_RRR2_MADD_U_64 = 0x68,
1433 OPC2_32_RRR2_MADDS_U_32 = 0x88,
1434 OPC2_32_RRR2_MADDS_U_64 = 0xe8,
1438 OPC2_32_RRR2_MSUB_32 = 0x0a,
1439 OPC2_32_RRR2_MSUB_64 = 0x6a,
1440 OPC2_32_RRR2_MSUBS_32 = 0x8a,
1441 OPC2_32_RRR2_MSUBS_64 = 0xea,
1442 OPC2_32_RRR2_MSUB_U_64 = 0x68,
1443 OPC2_32_RRR2_MSUBS_U_32 = 0x88,
1444 OPC2_32_RRR2_MSUBS_U_64 = 0xe8,
1451 OPC2_32_RRRR_DEXTR = 0x04,
1452 OPC2_32_RRRR_EXTR = 0x02,
1453 OPC2_32_RRRR_EXTR_U = 0x03,
1454 OPC2_32_RRRR_INSERT = 0x00,
1461 OPC2_32_RRRW_EXTR = 0x02,
1462 OPC2_32_RRRW_EXTR_U = 0x03,
1463 OPC2_32_RRRW_IMASK = 0x01,
1464 OPC2_32_RRRW_INSERT = 0x00,
1471 OPC2_32_SYS_DEBUG = 0x04,
1472 OPC2_32_SYS_DISABLE = 0x0d,
1473 OPC2_32_SYS_DISABLE_D = 0x0f, /* 1.6 up */
1474 OPC2_32_SYS_DSYNC = 0x12,
1475 OPC2_32_SYS_ENABLE = 0x0c,
1476 OPC2_32_SYS_ISYNC = 0x13,
1477 OPC2_32_SYS_NOP = 0x00,
1478 OPC2_32_SYS_RET = 0x06,
1479 OPC2_32_SYS_RFE = 0x07,
1480 OPC2_32_SYS_RFM = 0x05,
1481 OPC2_32_SYS_RSLCX = 0x09,
1482 OPC2_32_SYS_SVLCX = 0x08,
1483 OPC2_32_SYS_TRAPSV = 0x15,
1484 OPC2_32_SYS_TRAPV = 0x14,
1485 OPC2_32_SYS_RESTORE = 0x0e,
1486 OPC2_32_SYS_FRET = 0x03,