Lines Matching full:r1
212 static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2, in gen_offset_ld() argument
217 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop); in gen_offset_ld()
220 static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2, in gen_offset_st() argument
225 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop); in gen_offset_st()
261 static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off, in gen_st_preincr() argument
266 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop); in gen_st_preincr()
270 static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off, in gen_ld_preincr() argument
275 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop); in gen_ld_preincr()
368 tcg_gen_st_tl(r1, tcg_env, offsetof(CPUTriCoreState, REG)); \
376 static inline void gen_mtcr(DisasContext *ctx, TCGv r1, in gen_mtcr() argument
382 gen_helper_psw_write(tcg_env, r1); in gen_mtcr()
396 static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2) in gen_add_d() argument
401 tcg_gen_add_tl(result, r1, r2); in gen_add_d()
403 tcg_gen_xor_tl(cpu_PSW_V, result, r1); in gen_add_d()
404 tcg_gen_xor_tl(t0, r1, r2); in gen_add_d()
418 gen_add64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2) in gen_add64_d() argument
425 tcg_gen_add_i64(result, r1, r2); in gen_add64_d()
427 tcg_gen_xor_i64(t1, result, r1); in gen_add64_d()
428 tcg_gen_xor_i64(t0, r1, r2); in gen_add64_d()
489 /* ret = r2 + (r1 * r3); */
490 static inline void gen_madd32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3) in gen_madd32_d() argument
496 tcg_gen_ext_i32_i64(t1, r1); in gen_madd32_d()
521 static inline void gen_maddi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con) in gen_maddi32_d() argument
524 gen_madd32_d(ret, r1, r2, temp); in gen_maddi32_d()
528 gen_madd64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, in gen_madd64_d() argument
536 tcg_gen_muls2_tl(t1, t2, r1, r3); in gen_madd64_d()
556 gen_maddu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, in gen_maddu64_d() argument
563 tcg_gen_extu_i32_i64(t1, r1); in gen_maddu64_d()
586 gen_maddi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, in gen_maddi64_d() argument
590 gen_madd64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); in gen_maddi64_d()
594 gen_maddui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, in gen_maddui64_d() argument
598 gen_maddu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); in gen_maddui64_d()
688 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2);
725 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2);
873 gen_maddr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) in gen_maddr32_h() argument
878 tcg_gen_andi_tl(temp2, r1, 0xffff0000); in gen_maddr32_h()
879 tcg_gen_shli_tl(temp, r1, 16); in gen_maddr32_h()
884 gen_maddsur32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) in gen_maddsur32_h() argument
904 tcg_gen_andi_tl(temp2, r1, 0xffff0000); in gen_maddsur32_h()
905 tcg_gen_shli_tl(temp, r1, 16); in gen_maddsur32_h()
934 gen_maddr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) in gen_maddr32s_h() argument
939 tcg_gen_andi_tl(temp2, r1, 0xffff0000); in gen_maddr32s_h()
940 tcg_gen_shli_tl(temp, r1, 16); in gen_maddr32s_h()
945 gen_maddsur32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) in gen_maddsur32s_h() argument
965 tcg_gen_andi_tl(temp2, r1, 0xffff0000); in gen_maddsur32s_h()
966 tcg_gen_shli_tl(temp, r1, 16); in gen_maddsur32s_h()
971 gen_maddr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) in gen_maddr_q() argument
974 gen_helper_maddr_q(ret, tcg_env, r1, r2, r3, t_n); in gen_maddr_q()
978 gen_maddrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) in gen_maddrs_q() argument
981 gen_helper_maddr_q_ssov(ret, tcg_env, r1, r2, r3, t_n); in gen_maddrs_q()
1044 /* catch special case r1 = r2 = 0x8000 */ in gen_m16add32_q()
1061 /* catch special case r1 = r2 = 0x8000 */ in gen_m16adds32_q()
1083 /* catch special case r1 = r2 = 0x8000 */ in gen_m16add64_q()
1109 /* catch special case r1 = r2 = 0x8000 */ in gen_m16adds64_q()
1191 TCGv_i64 r1 = tcg_temp_new_i64(); in gen_madds64_q() local
1194 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high); in gen_madds64_q()
1195 gen_helper_madd64_q_ssov(r1, tcg_env, r1, arg2, arg3, t_n); in gen_madds64_q()
1196 tcg_gen_extr_i64_i32(rl, rh, r1); in gen_madds64_q()
1199 /* ret = r2 - (r1 * r3); */
1200 static inline void gen_msub32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3) in gen_msub32_d() argument
1206 tcg_gen_ext_i32_i64(t1, r1); in gen_msub32_d()
1232 static inline void gen_msubi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con) in gen_msubi32_d() argument
1235 gen_msub32_d(ret, r1, r2, temp); in gen_msubi32_d()
1239 gen_msub64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, in gen_msub64_d() argument
1247 tcg_gen_muls2_tl(t1, t2, r1, r3); in gen_msub64_d()
1267 gen_msubi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, in gen_msubi64_d() argument
1271 gen_msub64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); in gen_msubi64_d()
1275 gen_msubu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, in gen_msubu64_d() argument
1282 tcg_gen_extu_i32_i64(t1, r1); in gen_msubu64_d()
1303 gen_msubui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, in gen_msubui64_d() argument
1307 gen_msubu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); in gen_msubui64_d()
1310 static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2) in gen_addi_d() argument
1313 gen_add_d(ret, r1, temp); in gen_addi_d()
1317 static inline void gen_add_CC(TCGv ret, TCGv r1, TCGv r2) in gen_add_CC() argument
1324 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, r2, t0); in gen_add_CC()
1326 tcg_gen_xor_tl(cpu_PSW_V, result, r1); in gen_add_CC()
1327 tcg_gen_xor_tl(t0, r1, r2); in gen_add_CC()
1340 static inline void gen_addi_CC(TCGv ret, TCGv r1, int32_t con) in gen_addi_CC() argument
1343 gen_add_CC(ret, r1, temp); in gen_addi_CC()
1346 static inline void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2) in gen_addc_CC() argument
1352 tcg_gen_addcio_i32(result, cpu_PSW_C, r1, r2, cpu_PSW_C); in gen_addc_CC()
1354 tcg_gen_xor_tl(cpu_PSW_V, result, r1); in gen_addc_CC()
1355 tcg_gen_xor_tl(t0, r1, r2); in gen_addc_CC()
1368 static inline void gen_addci_CC(TCGv ret, TCGv r1, int32_t con) in gen_addci_CC() argument
1371 gen_addc_CC(ret, r1, temp); in gen_addci_CC()
1374 static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, in gen_cond_add() argument
1387 tcg_gen_add_tl(result, r1, r2); in gen_cond_add()
1389 tcg_gen_xor_tl(temp, result, r1); in gen_cond_add()
1390 tcg_gen_xor_tl(temp2, r1, r2); in gen_cond_add()
1404 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1); in gen_cond_add()
1407 static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2, in gen_condi_add() argument
1411 gen_cond_add(cond, r1, temp, r3, r4); in gen_condi_add()
1414 static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv r2) in gen_sub_d() argument
1419 tcg_gen_sub_tl(result, r1, r2); in gen_sub_d()
1421 tcg_gen_xor_tl(cpu_PSW_V, result, r1); in gen_sub_d()
1422 tcg_gen_xor_tl(temp, r1, r2); in gen_sub_d()
1436 gen_sub64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2) in gen_sub64_d() argument
1443 tcg_gen_sub_i64(result, r1, r2); in gen_sub64_d()
1445 tcg_gen_xor_i64(t1, result, r1); in gen_sub64_d()
1446 tcg_gen_xor_i64(t0, r1, r2); in gen_sub64_d()
1461 static inline void gen_sub_CC(TCGv ret, TCGv r1, TCGv r2) in gen_sub_CC() argument
1466 tcg_gen_sub_tl(result, r1, r2); in gen_sub_CC()
1468 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_PSW_C, r1, r2); in gen_sub_CC()
1470 tcg_gen_xor_tl(cpu_PSW_V, result, r1); in gen_sub_CC()
1471 tcg_gen_xor_tl(temp, r1, r2); in gen_sub_CC()
1484 static inline void gen_subc_CC(TCGv ret, TCGv r1, TCGv r2) in gen_subc_CC() argument
1488 gen_addc_CC(ret, r1, temp); in gen_subc_CC()
1491 static inline void gen_cond_sub(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, in gen_cond_sub() argument
1504 tcg_gen_sub_tl(result, r1, r2); in gen_cond_sub()
1506 tcg_gen_xor_tl(temp, result, r1); in gen_cond_sub()
1507 tcg_gen_xor_tl(temp2, r1, r2); in gen_cond_sub()
1521 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1); in gen_cond_sub()
1664 gen_msubr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) in gen_msubr32_h() argument
1669 tcg_gen_andi_tl(temp2, r1, 0xffff0000); in gen_msubr32_h()
1670 tcg_gen_shli_tl(temp, r1, 16); in gen_msubr32_h()
1698 gen_msubr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) in gen_msubr32s_h() argument
1703 tcg_gen_andi_tl(temp2, r1, 0xffff0000); in gen_msubr32s_h()
1704 tcg_gen_shli_tl(temp, r1, 16); in gen_msubr32s_h()
1709 gen_msubr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) in gen_msubr_q() argument
1712 gen_helper_msubr_q(ret, tcg_env, r1, r2, r3, temp); in gen_msubr_q()
1716 gen_msubrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) in gen_msubrs_q() argument
1719 gen_helper_msubr_q_ssov(ret, tcg_env, r1, r2, r3, temp); in gen_msubrs_q()
1773 /* catch special case r1 = r2 = 0x8000 */ in gen_m16sub32_q()
1790 /* catch special case r1 = r2 = 0x8000 */ in gen_m16subs32_q()
1812 /* catch special case r1 = r2 = 0x8000 */ in gen_m16sub64_q()
1838 /* catch special case r1 = r2 = 0x8000 */ in gen_m16subs64_q()
1925 TCGv_i64 r1 = tcg_temp_new_i64(); in gen_msubs64_q() local
1928 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high); in gen_msubs64_q()
1929 gen_helper_msub64_q_ssov(r1, tcg_env, r1, arg2, arg3, t_n); in gen_msubs64_q()
1930 tcg_gen_extr_i64_i32(rl, rh, r1); in gen_msubs64_q()
1994 gen_msubadr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) in gen_msubadr32_h() argument
2014 tcg_gen_andi_tl(temp2, r1, 0xffff0000); in gen_msubadr32_h()
2015 tcg_gen_shli_tl(temp, r1, 16); in gen_msubadr32_h()
2087 gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) in gen_msubadr32s_h() argument
2107 tcg_gen_andi_tl(temp2, r1, 0xffff0000); in gen_msubadr32s_h()
2108 tcg_gen_shli_tl(temp, r1, 16); in gen_msubadr32s_h()
2112 static inline void gen_abs(TCGv ret, TCGv r1) in gen_abs() argument
2114 tcg_gen_abs_tl(ret, r1); in gen_abs()
2115 /* overflow can only happen, if r1 = 0x80000000 */ in gen_abs()
2116 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, r1, 0x80000000); in gen_abs()
2127 static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2) in gen_absdif() argument
2132 tcg_gen_sub_tl(result, r1, r2); in gen_absdif()
2133 tcg_gen_sub_tl(temp, r2, r1); in gen_absdif()
2134 tcg_gen_movcond_tl(TCG_COND_GT, result, r1, r2, result, temp); in gen_absdif()
2137 tcg_gen_xor_tl(cpu_PSW_V, result, r1); in gen_absdif()
2139 tcg_gen_movcond_tl(TCG_COND_GT, cpu_PSW_V, r1, r2, cpu_PSW_V, temp); in gen_absdif()
2140 tcg_gen_xor_tl(temp, r1, r2); in gen_absdif()
2153 static inline void gen_absdifi(TCGv ret, TCGv r1, int32_t con) in gen_absdifi() argument
2156 gen_absdif(ret, r1, temp); in gen_absdifi()
2159 static inline void gen_absdifsi(TCGv ret, TCGv r1, int32_t con) in gen_absdifsi() argument
2162 gen_helper_absdif_ssov(ret, tcg_env, r1, temp); in gen_absdifsi()
2165 static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2) in gen_mul_i32s() argument
2170 tcg_gen_muls2_tl(low, high, r1, r2); in gen_mul_i32s()
2185 static inline void gen_muli_i32s(TCGv ret, TCGv r1, int32_t con) in gen_muli_i32s() argument
2188 gen_mul_i32s(ret, r1, temp); in gen_muli_i32s()
2191 static inline void gen_mul_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2) in gen_mul_i64s() argument
2193 tcg_gen_muls2_tl(ret_low, ret_high, r1, r2); in gen_mul_i64s()
2205 static inline void gen_muli_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, in gen_muli_i64s() argument
2209 gen_mul_i64s(ret_low, ret_high, r1, temp); in gen_muli_i64s()
2212 static inline void gen_mul_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2) in gen_mul_i64u() argument
2214 tcg_gen_mulu2_tl(ret_low, ret_high, r1, r2); in gen_mul_i64u()
2226 static inline void gen_muli_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, in gen_muli_i64u() argument
2230 gen_mul_i64u(ret_low, ret_high, r1, temp); in gen_muli_i64u()
2233 static inline void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con) in gen_mulsi_i32() argument
2236 gen_helper_mul_ssov(ret, tcg_env, r1, temp); in gen_mulsi_i32()
2239 static inline void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con) in gen_mulsui_i32() argument
2242 gen_helper_mul_suov(ret, tcg_env, r1, temp); in gen_mulsui_i32()
2245 /* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */
2246 static inline void gen_maddsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) in gen_maddsi_32() argument
2249 gen_helper_madd32_ssov(ret, tcg_env, r1, r2, temp); in gen_maddsi_32()
2252 static inline void gen_maddsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) in gen_maddsui_32() argument
2255 gen_helper_madd32_suov(ret, tcg_env, r1, r2, temp); in gen_maddsui_32()
2291 /* overflow only occurs if r1 = r2 = 0x8000 */ in gen_mul_q()
2324 /* catch special case r1 = r2 = 0x8000 */ in gen_mul_q_16()
2347 /* catch special case r1 = r2 = 0x8000 */ in gen_mulr_q()
2364 gen_madds_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, in gen_madds_64() argument
2369 gen_helper_madd64_ssov(temp64, tcg_env, r1, temp64, r3); in gen_madds_64()
2374 gen_maddsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, in gen_maddsi_64() argument
2378 gen_madds_64(ret_low, ret_high, r1, r2_low, r2_high, temp); in gen_maddsi_64()
2382 gen_maddsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, in gen_maddsu_64() argument
2387 gen_helper_madd64_suov(temp64, tcg_env, r1, temp64, r3); in gen_maddsu_64()
2392 gen_maddsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, in gen_maddsui_64() argument
2396 gen_maddsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp); in gen_maddsui_64()
2399 static inline void gen_msubsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) in gen_msubsi_32() argument
2402 gen_helper_msub32_ssov(ret, tcg_env, r1, r2, temp); in gen_msubsi_32()
2405 static inline void gen_msubsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) in gen_msubsui_32() argument
2408 gen_helper_msub32_suov(ret, tcg_env, r1, r2, temp); in gen_msubsui_32()
2412 gen_msubs_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, in gen_msubs_64() argument
2417 gen_helper_msub64_ssov(temp64, tcg_env, r1, temp64, r3); in gen_msubs_64()
2422 gen_msubsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, in gen_msubsi_64() argument
2426 gen_msubs_64(ret_low, ret_high, r1, r2_low, r2_high, temp); in gen_msubsi_64()
2430 gen_msubsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, in gen_msubsu_64() argument
2435 gen_helper_msub64_suov(temp64, tcg_env, r1, temp64, r3); in gen_msubsu_64()
2440 gen_msubsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, in gen_msubsui_64() argument
2444 gen_msubsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp); in gen_msubsui_64()
2458 static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count) in gen_shi() argument
2463 tcg_gen_shli_tl(ret, r1, shift_count); in gen_shi()
2465 tcg_gen_shri_tl(ret, r1, -shift_count); in gen_shi()
2469 static void gen_sh_hi(TCGv ret, TCGv r1, int32_t shiftcount) in gen_sh_hi() argument
2479 tcg_gen_andi_tl(temp_low, r1, 0xffff); in gen_sh_hi()
2480 tcg_gen_andi_tl(temp_high, r1, 0xffff0000); in gen_sh_hi()
2487 static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count) in gen_shaci() argument
2497 tcg_gen_mov_tl(ret, r1); in gen_shaci()
2500 tcg_gen_mov_tl(cpu_PSW_C, r1); in gen_shaci()
2502 tcg_gen_sari_tl(ret, r1, 31); in gen_shaci()
2512 tcg_gen_andi_tl(cpu_PSW_C, r1, msk); in gen_shaci()
2514 tcg_gen_setcond_tl(TCG_COND_GT, temp, r1, t_max); in gen_shaci()
2515 tcg_gen_setcond_tl(TCG_COND_LT, temp2, r1, t_min); in gen_shaci()
2521 tcg_gen_shli_tl(ret, r1, shift_count); in gen_shaci()
2527 tcg_gen_andi_tl(cpu_PSW_C, r1, msk); in gen_shaci()
2529 tcg_gen_sari_tl(ret, r1, -shift_count); in gen_shaci()
2538 static void gen_shas(TCGv ret, TCGv r1, TCGv r2) in gen_shas() argument
2540 gen_helper_sha_ssov(ret, tcg_env, r1, r2); in gen_shas()
2543 static void gen_shasi(TCGv ret, TCGv r1, int32_t con) in gen_shasi() argument
2546 gen_shas(ret, r1, temp); in gen_shasi()
2549 static void gen_sha_hi(TCGv ret, TCGv r1, int32_t shift_count) in gen_sha_hi() argument
2554 tcg_gen_mov_tl(ret, r1); in gen_sha_hi()
2559 tcg_gen_andi_tl(high, r1, 0xffff0000); in gen_sha_hi()
2560 tcg_gen_shli_tl(low, r1, shift_count); in gen_sha_hi()
2567 tcg_gen_ext16s_tl(low, r1); in gen_sha_hi()
2569 tcg_gen_sari_tl(ret, r1, -shift_count); in gen_sha_hi()
2574 /* ret = {ret[30:0], (r1 cond r2)}; */
2575 static void gen_sh_cond(int cond, TCGv ret, TCGv r1, TCGv r2) in gen_sh_cond() argument
2581 tcg_gen_setcond_tl(cond, temp2, r1, r2); in gen_sh_cond()
2585 static void gen_sh_condi(int cond, TCGv ret, TCGv r1, int32_t con) in gen_sh_condi() argument
2588 gen_sh_cond(cond, ret, r1, temp); in gen_sh_condi()
2591 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2) in gen_adds() argument
2593 gen_helper_add_ssov(ret, tcg_env, r1, r2); in gen_adds()
2596 static inline void gen_addsi(TCGv ret, TCGv r1, int32_t con) in gen_addsi() argument
2599 gen_helper_add_ssov(ret, tcg_env, r1, temp); in gen_addsi()
2602 static inline void gen_addsui(TCGv ret, TCGv r1, int32_t con) in gen_addsui() argument
2605 gen_helper_add_suov(ret, tcg_env, r1, temp); in gen_addsui()
2608 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2) in gen_subs() argument
2610 gen_helper_sub_ssov(ret, tcg_env, r1, r2); in gen_subs()
2613 static inline void gen_subsu(TCGv ret, TCGv r1, TCGv r2) in gen_subsu() argument
2615 gen_helper_sub_suov(ret, tcg_env, r1, r2); in gen_subsu()
2618 static inline void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2, in gen_bit_2op() argument
2629 tcg_gen_shri_tl(temp1, r1, pos1); in gen_bit_2op()
2637 /* ret = r1[pos1] op1 r2[pos2]; */
2638 static inline void gen_bit_1op(TCGv ret, TCGv r1, TCGv r2, in gen_bit_1op() argument
2648 tcg_gen_shri_tl(temp1, r1, pos1); in gen_bit_1op()
2655 static inline void gen_accumulating_cond(int cond, TCGv ret, TCGv r1, TCGv r2, in gen_accumulating_cond() argument
2661 tcg_gen_setcond_tl(cond, temp, r1, r2); in gen_accumulating_cond()
2671 gen_accumulating_condi(int cond, TCGv ret, TCGv r1, int32_t con, in gen_accumulating_condi() argument
2675 gen_accumulating_cond(cond, ret, r1, temp, op); in gen_accumulating_condi()
2678 static inline void gen_eqany_bi(TCGv ret, TCGv r1, int32_t con) in gen_eqany_bi() argument
2686 tcg_gen_andi_tl(b0, r1, 0xff); in gen_eqany_bi()
2690 tcg_gen_andi_tl(b1, r1, 0xff00); in gen_eqany_bi()
2694 tcg_gen_andi_tl(b2, r1, 0xff0000); in gen_eqany_bi()
2698 tcg_gen_andi_tl(b3, r1, 0xff000000); in gen_eqany_bi()
2707 static inline void gen_eqany_hi(TCGv ret, TCGv r1, int32_t con) in gen_eqany_hi() argument
2713 tcg_gen_andi_tl(h0, r1, 0xffff); in gen_eqany_hi()
2717 tcg_gen_andi_tl(h1, r1, 0xffff0000); in gen_eqany_hi()
2725 ret = (r1 & ~mask) | (r2 << pos) & mask); */
2726 static inline void gen_insert(TCGv ret, TCGv r1, TCGv r2, TCGv width, TCGv pos) in gen_insert() argument
2738 tcg_gen_andc_tl(temp2, r1, mask); in gen_insert()
2742 static inline void gen_bsplit(TCGv rl, TCGv rh, TCGv r1) in gen_bsplit() argument
2746 gen_helper_bsplit(temp, r1); in gen_bsplit()
2750 static inline void gen_unpack(TCGv rl, TCGv rh, TCGv r1) in gen_unpack() argument
2754 gen_helper_unpack(temp, r1); in gen_unpack()
2759 gen_dvinit_b(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2) in gen_dvinit_b() argument
2764 gen_helper_dvinit_b_13(ret, tcg_env, r1, r2); in gen_dvinit_b()
2766 gen_helper_dvinit_b_131(ret, tcg_env, r1, r2); in gen_dvinit_b()
2772 gen_dvinit_h(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2) in gen_dvinit_h() argument
2777 gen_helper_dvinit_h_13(ret, tcg_env, r1, r2); in gen_dvinit_h()
2779 gen_helper_dvinit_h_131(ret, tcg_env, r1, r2); in gen_dvinit_h()
2842 static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1, in gen_branch_cond() argument
2846 tcg_gen_brcond_tl(cond, r1, r2, jumpLabel); in gen_branch_cond()
2854 static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1, in gen_branch_condi() argument
2858 gen_branch_cond(ctx, cond, r1, temp, address); in gen_branch_condi()
2861 static void gen_loop(DisasContext *ctx, int r1, int32_t offset) in gen_loop() argument
2865 tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1); in gen_loop()
2866 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1); in gen_loop()
2893 static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, in gen_compute_branch() argument
2944 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], in gen_compute_branch()
2948 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], in gen_compute_branch()
2952 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], in gen_compute_branch()
2956 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], in gen_compute_branch()
2960 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset); in gen_compute_branch()
2963 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset); in gen_compute_branch()
2966 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], 0, offset); in gen_compute_branch()
2969 gen_branch_condi(ctx, TCG_COND_GT, cpu_gpr_d[r1], 0, offset); in gen_compute_branch()
2972 gen_branch_condi(ctx, TCG_COND_LE, cpu_gpr_d[r1], 0, offset); in gen_compute_branch()
2975 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], 0, offset); in gen_compute_branch()
2978 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], 0, offset); in gen_compute_branch()
2981 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset); in gen_compute_branch()
2984 gen_loop(ctx, r1, offset * 2 - 32); in gen_compute_branch()
2988 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], 0xfffffffe); in gen_compute_branch()
3022 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], constant, offset); in gen_compute_branch()
3024 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], constant, offset); in gen_compute_branch()
3029 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], constant, offset); in gen_compute_branch()
3032 gen_branch_condi(ctx, TCG_COND_GEU, cpu_gpr_d[r1], constant, in gen_compute_branch()
3038 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], constant, offset); in gen_compute_branch()
3041 gen_branch_condi(ctx, TCG_COND_LTU, cpu_gpr_d[r1], constant, in gen_compute_branch()
3048 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); in gen_compute_branch()
3050 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); in gen_compute_branch()
3053 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); in gen_compute_branch()
3055 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); in gen_compute_branch()
3064 tcg_gen_andi_tl(temp, cpu_gpr_d[r1], (1 << n)); in gen_compute_branch()
3075 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], in gen_compute_branch()
3078 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], in gen_compute_branch()
3084 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_a[r1], cpu_gpr_a[r2], in gen_compute_branch()
3087 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_a[r1], cpu_gpr_a[r2], in gen_compute_branch()
3093 gen_branch_cond(ctx, TCG_COND_GE, cpu_gpr_d[r1], cpu_gpr_d[r2], in gen_compute_branch()
3096 gen_branch_cond(ctx, TCG_COND_GEU, cpu_gpr_d[r1], cpu_gpr_d[r2], in gen_compute_branch()
3102 gen_branch_cond(ctx, TCG_COND_LT, cpu_gpr_d[r1], cpu_gpr_d[r2], in gen_compute_branch()
3105 gen_branch_cond(ctx, TCG_COND_LTU, cpu_gpr_d[r1], cpu_gpr_d[r2], in gen_compute_branch()
3121 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); in gen_compute_branch()
3122 /* also save r2, in case of r1 == r2, so r2 is not decremented */ in gen_compute_branch()
3125 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); in gen_compute_branch()
3128 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); in gen_compute_branch()
3129 /* also save r2, in case of r1 == r2, so r2 is not decremented */ in gen_compute_branch()
3132 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); in gen_compute_branch()
3138 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset); in gen_compute_branch()
3140 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset); in gen_compute_branch()
3155 int r1; in decode_src_opc() local
3159 r1 = MASK_OP_SRC_S1D(ctx->opcode); in decode_src_opc()
3164 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); in decode_src_opc()
3167 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[15], const4); in decode_src_opc()
3170 gen_addi_d(cpu_gpr_d[15], cpu_gpr_d[r1], const4); in decode_src_opc()
3173 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], const4); in decode_src_opc()
3176 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const4, cpu_gpr_d[r1], in decode_src_opc()
3180 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const4, cpu_gpr_d[r1], in decode_src_opc()
3186 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp, in decode_src_opc()
3187 temp2, cpu_gpr_d[r1]); in decode_src_opc()
3192 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp, in decode_src_opc()
3193 temp2, cpu_gpr_d[r1]); in decode_src_opc()
3196 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1], in decode_src_opc()
3200 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1], in decode_src_opc()
3204 tcg_gen_movi_tl(cpu_gpr_d[r1], const4); in decode_src_opc()
3208 tcg_gen_movi_tl(cpu_gpr_a[r1], const4); in decode_src_opc()
3212 CHECK_REG_PAIR(r1); in decode_src_opc()
3213 tcg_gen_movi_tl(cpu_gpr_d[r1], const4); in decode_src_opc()
3214 tcg_gen_sari_tl(cpu_gpr_d[r1+1], cpu_gpr_d[r1], 31); in decode_src_opc()
3220 gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); in decode_src_opc()
3223 gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); in decode_src_opc()
3232 int r1, r2; in decode_srr_opc() local
3235 r1 = MASK_OP_SRR_S1D(ctx->opcode); in decode_srr_opc()
3240 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_srr_opc()
3243 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]); in decode_srr_opc()
3246 gen_add_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_srr_opc()
3249 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], cpu_gpr_a[r2]); in decode_srr_opc()
3252 gen_adds(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_srr_opc()
3255 tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_srr_opc()
3259 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp, in decode_srr_opc()
3260 cpu_gpr_d[r2], cpu_gpr_d[r1]); in decode_srr_opc()
3264 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp, in decode_srr_opc()
3265 cpu_gpr_d[r2], cpu_gpr_d[r1]); in decode_srr_opc()
3268 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1], in decode_srr_opc()
3272 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1], in decode_srr_opc()
3276 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_srr_opc()
3279 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_d[r2]); in decode_srr_opc()
3282 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_a[r2]); in decode_srr_opc()
3285 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_a[r2]); in decode_srr_opc()
3288 gen_mul_i32s(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_srr_opc()
3291 tcg_gen_or_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_srr_opc()
3294 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_srr_opc()
3297 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]); in decode_srr_opc()
3300 gen_sub_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_srr_opc()
3303 gen_subs(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_srr_opc()
3306 tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_srr_opc()
3315 int r1, r2; in decode_ssr_opc() local
3317 r1 = MASK_OP_SSR_S1(ctx->opcode); in decode_ssr_opc()
3322 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); in decode_ssr_opc()
3325 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); in decode_ssr_opc()
3329 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); in decode_ssr_opc()
3332 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); in decode_ssr_opc()
3336 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW); in decode_ssr_opc()
3339 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW); in decode_ssr_opc()
3343 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); in decode_ssr_opc()
3346 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); in decode_ssr_opc()
3399 int r1, r2; in decode_slr_opc() local
3401 r1 = MASK_OP_SLR_D(ctx->opcode); in decode_slr_opc()
3407 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); in decode_slr_opc()
3410 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); in decode_slr_opc()
3414 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); in decode_slr_opc()
3417 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); in decode_slr_opc()
3421 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW); in decode_slr_opc()
3424 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW); in decode_slr_opc()
3428 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); in decode_slr_opc()
3431 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); in decode_slr_opc()
3507 uint32_t r1; in decode_sr_accu() local
3509 r1 = MASK_OP_SR_S1D(ctx->opcode); in decode_sr_accu()
3514 /* calc V bit -- overflow only if r1 = -0x80000000 */ in decode_sr_accu()
3515 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], -0x80000000); in decode_sr_accu()
3520 tcg_gen_neg_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]); in decode_sr_accu()
3522 tcg_gen_add_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_gpr_d[r1]); in decode_sr_accu()
3523 tcg_gen_xor_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_PSW_AV); in decode_sr_accu()
3528 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7f, -0x80); in decode_sr_accu()
3531 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xff); in decode_sr_accu()
3534 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7fff, -0x8000); in decode_sr_accu()
3537 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xffff); in decode_sr_accu()
3547 int r1, r2; in decode_16Bit_opc() local
3615 r1 = MASK_OP_SRRS_S1D(ctx->opcode); in decode_16Bit_opc()
3619 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp); in decode_16Bit_opc()
3623 r1 = MASK_OP_SLRO_D(ctx->opcode); in decode_16Bit_opc()
3625 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); in decode_16Bit_opc()
3628 r1 = MASK_OP_SLRO_D(ctx->opcode); in decode_16Bit_opc()
3630 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB); in decode_16Bit_opc()
3633 r1 = MASK_OP_SLRO_D(ctx->opcode); in decode_16Bit_opc()
3635 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW); in decode_16Bit_opc()
3638 r1 = MASK_OP_SLRO_D(ctx->opcode); in decode_16Bit_opc()
3640 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); in decode_16Bit_opc()
3678 r1 = MASK_OP_SBR_S2(ctx->opcode); in decode_16Bit_opc()
3680 gen_compute_branch(ctx, op1, r1, 0, 0, address); in decode_16Bit_opc()
3696 r1 = MASK_OP_SBR_S2(ctx->opcode); in decode_16Bit_opc()
3698 gen_compute_branch(ctx, op1, r1, 0, 0, address); in decode_16Bit_opc()
3736 r1 = MASK_OP_SSRO_S1(ctx->opcode); in decode_16Bit_opc()
3738 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); in decode_16Bit_opc()
3741 r1 = MASK_OP_SSRO_S1(ctx->opcode); in decode_16Bit_opc()
3743 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB); in decode_16Bit_opc()
3746 r1 = MASK_OP_SSRO_S1(ctx->opcode); in decode_16Bit_opc()
3748 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW); in decode_16Bit_opc()
3751 r1 = MASK_OP_SSRO_S1(ctx->opcode); in decode_16Bit_opc()
3753 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); in decode_16Bit_opc()
3763 r1 = MASK_OP_SR_S1D(ctx->opcode); in decode_16Bit_opc()
3764 gen_compute_branch(ctx, op1, r1, 0, 0, 0); in decode_16Bit_opc()
3767 r1 = MASK_OP_SR_S1D(ctx->opcode); in decode_16Bit_opc()
3768 tcg_gen_not_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]); in decode_16Bit_opc()
3783 int32_t r1; in decode_abs_ldw() local
3787 r1 = MASK_OP_ABS_S1D(ctx->opcode); in decode_abs_ldw()
3795 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL); in decode_abs_ldw()
3798 CHECK_REG_PAIR(r1); in decode_abs_ldw()
3799 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); in decode_abs_ldw()
3802 CHECK_REG_PAIR(r1); in decode_abs_ldw()
3803 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); in decode_abs_ldw()
3806 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL); in decode_abs_ldw()
3816 int32_t r1; in decode_abs_ldb() local
3820 r1 = MASK_OP_ABS_S1D(ctx->opcode); in decode_abs_ldb()
3828 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_SB); in decode_abs_ldb()
3831 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB); in decode_abs_ldb()
3834 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESW); in decode_abs_ldb()
3837 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); in decode_abs_ldb()
3847 int32_t r1; in decode_abs_ldst_swap() local
3851 r1 = MASK_OP_ABS_S1D(ctx->opcode); in decode_abs_ldst_swap()
3859 gen_ldmst(ctx, r1, temp); in decode_abs_ldst_swap()
3862 gen_swap(ctx, r1, temp); in decode_abs_ldst_swap()
3898 int32_t r1; in decode_abs_store() local
3902 r1 = MASK_OP_ABS_S1D(ctx->opcode); in decode_abs_store()
3910 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL); in decode_abs_store()
3913 CHECK_REG_PAIR(r1); in decode_abs_store()
3914 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); in decode_abs_store()
3917 CHECK_REG_PAIR(r1); in decode_abs_store()
3918 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); in decode_abs_store()
3921 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL); in decode_abs_store()
3931 int32_t r1; in decode_abs_storeb_h() local
3935 r1 = MASK_OP_ABS_S1D(ctx->opcode); in decode_abs_storeb_h()
3943 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB); in decode_abs_storeb_h()
3946 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); in decode_abs_storeb_h()
3958 int r1, r2, r3; in decode_bit_andacc() local
3961 r1 = MASK_OP_BIT_S1(ctx->opcode); in decode_bit_andacc()
3971 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_bit_andacc()
3975 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_bit_andacc()
3980 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_bit_andacc()
3983 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_bit_andacc()
3988 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_bit_andacc()
3999 int r1, r2, r3; in decode_bit_logical_t() local
4001 r1 = MASK_OP_BIT_S1(ctx->opcode); in decode_bit_logical_t()
4010 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_bit_logical_t()
4014 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_bit_logical_t()
4018 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_bit_logical_t()
4022 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_bit_logical_t()
4033 int r1, r2, r3; in decode_bit_insert() local
4037 r1 = MASK_OP_BIT_S1(ctx->opcode); in decode_bit_insert()
4049 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, pos1, 1); in decode_bit_insert()
4056 int r1, r2, r3; in decode_bit_logical_t2() local
4060 r1 = MASK_OP_BIT_S1(ctx->opcode); in decode_bit_logical_t2()
4068 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_bit_logical_t2()
4072 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_bit_logical_t2()
4076 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_bit_logical_t2()
4080 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_bit_logical_t2()
4092 int r1, r2, r3; in decode_bit_orand() local
4096 r1 = MASK_OP_BIT_S1(ctx->opcode); in decode_bit_orand()
4104 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_bit_orand()
4108 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_bit_orand()
4113 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_bit_orand()
4116 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_bit_orand()
4121 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_bit_orand()
4132 int r1, r2, r3; in decode_bit_sh_logic1() local
4137 r1 = MASK_OP_BIT_S1(ctx->opcode); in decode_bit_sh_logic1()
4147 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_bit_sh_logic1()
4151 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_bit_sh_logic1()
4155 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_bit_sh_logic1()
4159 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_bit_sh_logic1()
4172 int r1, r2, r3; in decode_bit_sh_logic2() local
4177 r1 = MASK_OP_BIT_S1(ctx->opcode); in decode_bit_sh_logic2()
4187 gen_bit_1op(temp, cpu_gpr_d[r1] , cpu_gpr_d[r2] , in decode_bit_sh_logic2()
4191 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_bit_sh_logic2()
4195 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_bit_sh_logic2()
4199 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_bit_sh_logic2()
4216 int32_t r1, r2; in decode_bo_addrmode_post_pre_base() local
4219 r1 = MASK_OP_BO_S1D(ctx->opcode); in decode_bo_addrmode_post_pre_base()
4267 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL); in decode_bo_addrmode_post_pre_base()
4270 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, in decode_bo_addrmode_post_pre_base()
4275 gen_st_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL); in decode_bo_addrmode_post_pre_base()
4278 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); in decode_bo_addrmode_post_pre_base()
4281 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, in decode_bo_addrmode_post_pre_base()
4286 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); in decode_bo_addrmode_post_pre_base()
4289 CHECK_REG_PAIR(r1); in decode_bo_addrmode_post_pre_base()
4290 gen_offset_st_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], in decode_bo_addrmode_post_pre_base()
4294 CHECK_REG_PAIR(r1); in decode_bo_addrmode_post_pre_base()
4295 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx); in decode_bo_addrmode_post_pre_base()
4299 CHECK_REG_PAIR(r1); in decode_bo_addrmode_post_pre_base()
4302 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); in decode_bo_addrmode_post_pre_base()
4306 CHECK_REG_PAIR(r1); in decode_bo_addrmode_post_pre_base()
4307 gen_offset_st_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], in decode_bo_addrmode_post_pre_base()
4311 CHECK_REG_PAIR(r1); in decode_bo_addrmode_post_pre_base()
4312 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx); in decode_bo_addrmode_post_pre_base()
4316 CHECK_REG_PAIR(r1); in decode_bo_addrmode_post_pre_base()
4319 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); in decode_bo_addrmode_post_pre_base()
4323 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); in decode_bo_addrmode_post_pre_base()
4326 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, in decode_bo_addrmode_post_pre_base()
4331 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); in decode_bo_addrmode_post_pre_base()
4335 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); in decode_bo_addrmode_post_pre_base()
4340 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); in decode_bo_addrmode_post_pre_base()
4347 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); in decode_bo_addrmode_post_pre_base()
4351 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); in decode_bo_addrmode_post_pre_base()
4354 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, in decode_bo_addrmode_post_pre_base()
4359 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); in decode_bo_addrmode_post_pre_base()
4370 int32_t r1, r2; in decode_bo_addrmode_bitreverse_circular() local
4373 r1 = MASK_OP_BO_S1D(ctx->opcode); in decode_bo_addrmode_bitreverse_circular()
4397 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); in decode_bo_addrmode_bitreverse_circular()
4401 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); in decode_bo_addrmode_bitreverse_circular()
4405 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); in decode_bo_addrmode_bitreverse_circular()
4409 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); in decode_bo_addrmode_bitreverse_circular()
4413 CHECK_REG_PAIR(r1); in decode_bo_addrmode_bitreverse_circular()
4414 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx); in decode_bo_addrmode_bitreverse_circular()
4418 CHECK_REG_PAIR(r1); in decode_bo_addrmode_bitreverse_circular()
4419 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); in decode_bo_addrmode_bitreverse_circular()
4424 tcg_gen_qemu_st_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL); in decode_bo_addrmode_bitreverse_circular()
4428 CHECK_REG_PAIR(r1); in decode_bo_addrmode_bitreverse_circular()
4429 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx); in decode_bo_addrmode_bitreverse_circular()
4433 CHECK_REG_PAIR(r1); in decode_bo_addrmode_bitreverse_circular()
4434 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); in decode_bo_addrmode_bitreverse_circular()
4439 tcg_gen_qemu_st_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL); in decode_bo_addrmode_bitreverse_circular()
4443 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); in decode_bo_addrmode_bitreverse_circular()
4447 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); in decode_bo_addrmode_bitreverse_circular()
4451 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); in decode_bo_addrmode_bitreverse_circular()
4456 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); in decode_bo_addrmode_bitreverse_circular()
4461 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); in decode_bo_addrmode_bitreverse_circular()
4465 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); in decode_bo_addrmode_bitreverse_circular()
4477 int32_t r1, r2; in decode_bo_addrmode_ld_post_pre_base() local
4480 r1 = MASK_OP_BO_S1D(ctx->opcode); in decode_bo_addrmode_ld_post_pre_base()
4487 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL); in decode_bo_addrmode_ld_post_pre_base()
4490 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, in decode_bo_addrmode_ld_post_pre_base()
4495 gen_ld_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL); in decode_bo_addrmode_ld_post_pre_base()
4498 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB); in decode_bo_addrmode_ld_post_pre_base()
4501 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, in decode_bo_addrmode_ld_post_pre_base()
4506 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB); in decode_bo_addrmode_ld_post_pre_base()
4509 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); in decode_bo_addrmode_ld_post_pre_base()
4512 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, in decode_bo_addrmode_ld_post_pre_base()
4517 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); in decode_bo_addrmode_ld_post_pre_base()
4520 CHECK_REG_PAIR(r1); in decode_bo_addrmode_ld_post_pre_base()
4521 gen_offset_ld_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], in decode_bo_addrmode_ld_post_pre_base()
4525 CHECK_REG_PAIR(r1); in decode_bo_addrmode_ld_post_pre_base()
4526 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx); in decode_bo_addrmode_ld_post_pre_base()
4530 CHECK_REG_PAIR(r1); in decode_bo_addrmode_ld_post_pre_base()
4533 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); in decode_bo_addrmode_ld_post_pre_base()
4537 CHECK_REG_PAIR(r1); in decode_bo_addrmode_ld_post_pre_base()
4538 gen_offset_ld_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], in decode_bo_addrmode_ld_post_pre_base()
4542 CHECK_REG_PAIR(r1); in decode_bo_addrmode_ld_post_pre_base()
4543 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx); in decode_bo_addrmode_ld_post_pre_base()
4547 CHECK_REG_PAIR(r1); in decode_bo_addrmode_ld_post_pre_base()
4550 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); in decode_bo_addrmode_ld_post_pre_base()
4554 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW); in decode_bo_addrmode_ld_post_pre_base()
4557 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, in decode_bo_addrmode_ld_post_pre_base()
4562 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW); in decode_bo_addrmode_ld_post_pre_base()
4565 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); in decode_bo_addrmode_ld_post_pre_base()
4568 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, in decode_bo_addrmode_ld_post_pre_base()
4573 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); in decode_bo_addrmode_ld_post_pre_base()
4576 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); in decode_bo_addrmode_ld_post_pre_base()
4577 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); in decode_bo_addrmode_ld_post_pre_base()
4580 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, in decode_bo_addrmode_ld_post_pre_base()
4582 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); in decode_bo_addrmode_ld_post_pre_base()
4586 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); in decode_bo_addrmode_ld_post_pre_base()
4587 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); in decode_bo_addrmode_ld_post_pre_base()
4590 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); in decode_bo_addrmode_ld_post_pre_base()
4593 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, in decode_bo_addrmode_ld_post_pre_base()
4598 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); in decode_bo_addrmode_ld_post_pre_base()
4609 int r1, r2; in decode_bo_addrmode_ld_bitreverse_circular() local
4612 r1 = MASK_OP_BO_S1D(ctx->opcode); in decode_bo_addrmode_ld_bitreverse_circular()
4627 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); in decode_bo_addrmode_ld_bitreverse_circular()
4631 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); in decode_bo_addrmode_ld_bitreverse_circular()
4635 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB); in decode_bo_addrmode_ld_bitreverse_circular()
4639 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB); in decode_bo_addrmode_ld_bitreverse_circular()
4643 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); in decode_bo_addrmode_ld_bitreverse_circular()
4647 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); in decode_bo_addrmode_ld_bitreverse_circular()
4651 CHECK_REG_PAIR(r1); in decode_bo_addrmode_ld_bitreverse_circular()
4652 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx); in decode_bo_addrmode_ld_bitreverse_circular()
4656 CHECK_REG_PAIR(r1); in decode_bo_addrmode_ld_bitreverse_circular()
4657 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); in decode_bo_addrmode_ld_bitreverse_circular()
4662 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL); in decode_bo_addrmode_ld_bitreverse_circular()
4666 CHECK_REG_PAIR(r1); in decode_bo_addrmode_ld_bitreverse_circular()
4667 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx); in decode_bo_addrmode_ld_bitreverse_circular()
4671 CHECK_REG_PAIR(r1); in decode_bo_addrmode_ld_bitreverse_circular()
4672 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); in decode_bo_addrmode_ld_bitreverse_circular()
4677 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL); in decode_bo_addrmode_ld_bitreverse_circular()
4681 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW); in decode_bo_addrmode_ld_bitreverse_circular()
4685 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW); in decode_bo_addrmode_ld_bitreverse_circular()
4689 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); in decode_bo_addrmode_ld_bitreverse_circular()
4693 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); in decode_bo_addrmode_ld_bitreverse_circular()
4697 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); in decode_bo_addrmode_ld_bitreverse_circular()
4698 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); in decode_bo_addrmode_ld_bitreverse_circular()
4702 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); in decode_bo_addrmode_ld_bitreverse_circular()
4703 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); in decode_bo_addrmode_ld_bitreverse_circular()
4707 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); in decode_bo_addrmode_ld_bitreverse_circular()
4711 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); in decode_bo_addrmode_ld_bitreverse_circular()
4723 int r1, r2; in decode_bo_addrmode_stctx_post_pre_base() local
4727 r1 = MASK_OP_BO_S1D(ctx->opcode); in decode_bo_addrmode_stctx_post_pre_base()
4742 gen_ldmst(ctx, r1, temp); in decode_bo_addrmode_stctx_post_pre_base()
4745 gen_ldmst(ctx, r1, cpu_gpr_a[r2]); in decode_bo_addrmode_stctx_post_pre_base()
4750 gen_ldmst(ctx, r1, cpu_gpr_a[r2]); in decode_bo_addrmode_stctx_post_pre_base()
4757 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], off10); in decode_bo_addrmode_stctx_post_pre_base()
4769 gen_swap(ctx, r1, temp); in decode_bo_addrmode_stctx_post_pre_base()
4772 gen_swap(ctx, r1, cpu_gpr_a[r2]); in decode_bo_addrmode_stctx_post_pre_base()
4777 gen_swap(ctx, r1, cpu_gpr_a[r2]); in decode_bo_addrmode_stctx_post_pre_base()
4781 gen_cmpswap(ctx, r1, temp); in decode_bo_addrmode_stctx_post_pre_base()
4784 gen_cmpswap(ctx, r1, cpu_gpr_a[r2]); in decode_bo_addrmode_stctx_post_pre_base()
4789 gen_cmpswap(ctx, r1, cpu_gpr_a[r2]); in decode_bo_addrmode_stctx_post_pre_base()
4793 gen_swapmsk(ctx, r1, temp); in decode_bo_addrmode_stctx_post_pre_base()
4796 gen_swapmsk(ctx, r1, cpu_gpr_a[r2]); in decode_bo_addrmode_stctx_post_pre_base()
4801 gen_swapmsk(ctx, r1, cpu_gpr_a[r2]); in decode_bo_addrmode_stctx_post_pre_base()
4812 int r1, r2; in decode_bo_addrmode_ldmst_bitreverse_circular() local
4815 r1 = MASK_OP_BO_S1D(ctx->opcode); in decode_bo_addrmode_ldmst_bitreverse_circular()
4829 gen_ldmst(ctx, r1, temp2); in decode_bo_addrmode_ldmst_bitreverse_circular()
4833 gen_ldmst(ctx, r1, temp2); in decode_bo_addrmode_ldmst_bitreverse_circular()
4837 gen_swap(ctx, r1, temp2); in decode_bo_addrmode_ldmst_bitreverse_circular()
4841 gen_swap(ctx, r1, temp2); in decode_bo_addrmode_ldmst_bitreverse_circular()
4845 gen_cmpswap(ctx, r1, temp2); in decode_bo_addrmode_ldmst_bitreverse_circular()
4849 gen_cmpswap(ctx, r1, temp2); in decode_bo_addrmode_ldmst_bitreverse_circular()
4853 gen_swapmsk(ctx, r1, temp2); in decode_bo_addrmode_ldmst_bitreverse_circular()
4857 gen_swapmsk(ctx, r1, temp2); in decode_bo_addrmode_ldmst_bitreverse_circular()
4867 int r1, r2; in decode_bol_opc() local
4871 r1 = MASK_OP_BOL_S1D(ctx->opcode); in decode_bol_opc()
4879 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LEUL); in decode_bol_opc()
4884 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUL); in decode_bol_opc()
4887 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], address); in decode_bol_opc()
4891 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], address, MO_LEUL); in decode_bol_opc()
4897 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUL); in decode_bol_opc()
4901 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB); in decode_bol_opc()
4908 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_UB); in decode_bol_opc()
4915 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW); in decode_bol_opc()
4922 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUW); in decode_bol_opc()
4929 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB); in decode_bol_opc()
4936 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW); in decode_bol_opc()
4950 int r1, r2; in decode_rc_logical_shift() local
4955 r1 = MASK_OP_RC_S1(ctx->opcode); in decode_rc_logical_shift()
4961 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); in decode_rc_logical_shift()
4964 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9); in decode_rc_logical_shift()
4969 tcg_gen_nand_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp); in decode_rc_logical_shift()
4974 tcg_gen_nor_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp); in decode_rc_logical_shift()
4977 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); in decode_rc_logical_shift()
4980 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9); in decode_rc_logical_shift()
4984 gen_shi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); in decode_rc_logical_shift()
4988 gen_sh_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); in decode_rc_logical_shift()
4992 gen_shaci(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); in decode_rc_logical_shift()
4996 gen_sha_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); in decode_rc_logical_shift()
4999 gen_shasi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); in decode_rc_logical_shift()
5002 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); in decode_rc_logical_shift()
5006 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); in decode_rc_logical_shift()
5011 gen_helper_shuffle(cpu_gpr_d[r2], cpu_gpr_d[r1], temp); in decode_rc_logical_shift()
5024 int r1, r2; in decode_rc_accumulator() local
5030 r1 = MASK_OP_RC_S1(ctx->opcode); in decode_rc_accumulator()
5039 gen_absdifi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); in decode_rc_accumulator()
5042 gen_absdifsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); in decode_rc_accumulator()
5045 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); in decode_rc_accumulator()
5048 gen_addci_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); in decode_rc_accumulator()
5051 gen_addsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); in decode_rc_accumulator()
5054 gen_addsui(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); in decode_rc_accumulator()
5057 gen_addi_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); in decode_rc_accumulator()
5060 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], in decode_rc_accumulator()
5064 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], in decode_rc_accumulator()
5069 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], in decode_rc_accumulator()
5073 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], in decode_rc_accumulator()
5078 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], in decode_rc_accumulator()
5082 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], in decode_rc_accumulator()
5086 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); in decode_rc_accumulator()
5089 gen_eqany_bi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); in decode_rc_accumulator()
5092 gen_eqany_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); in decode_rc_accumulator()
5095 tcg_gen_setcondi_tl(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); in decode_rc_accumulator()
5099 tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); in decode_rc_accumulator()
5102 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); in decode_rc_accumulator()
5106 tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); in decode_rc_accumulator()
5110 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, in decode_rc_accumulator()
5111 cpu_gpr_d[r1], temp); in decode_rc_accumulator()
5115 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, in decode_rc_accumulator()
5116 cpu_gpr_d[r1], temp); in decode_rc_accumulator()
5120 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, in decode_rc_accumulator()
5121 cpu_gpr_d[r1], temp); in decode_rc_accumulator()
5125 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, in decode_rc_accumulator()
5126 cpu_gpr_d[r1], temp); in decode_rc_accumulator()
5129 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); in decode_rc_accumulator()
5132 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], in decode_rc_accumulator()
5136 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], in decode_rc_accumulator()
5141 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], in decode_rc_accumulator()
5145 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], in decode_rc_accumulator()
5150 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], in decode_rc_accumulator()
5154 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], in decode_rc_accumulator()
5159 gen_sub_d(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); in decode_rc_accumulator()
5163 gen_subs(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); in decode_rc_accumulator()
5167 gen_subsu(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); in decode_rc_accumulator()
5170 gen_sh_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); in decode_rc_accumulator()
5173 gen_sh_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); in decode_rc_accumulator()
5177 gen_sh_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); in decode_rc_accumulator()
5180 gen_sh_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); in decode_rc_accumulator()
5184 gen_sh_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); in decode_rc_accumulator()
5187 gen_sh_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); in decode_rc_accumulator()
5190 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], in decode_rc_accumulator()
5194 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], in decode_rc_accumulator()
5199 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], in decode_rc_accumulator()
5203 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], in decode_rc_accumulator()
5208 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], in decode_rc_accumulator()
5212 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], in decode_rc_accumulator()
5247 int r1, r2; in decode_rc_mul() local
5251 r1 = MASK_OP_RC_S1(ctx->opcode); in decode_rc_mul()
5258 gen_muli_i32s(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); in decode_rc_mul()
5262 gen_muli_i64s(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9); in decode_rc_mul()
5265 gen_mulsi_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); in decode_rc_mul()
5270 gen_muli_i64u(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9); in decode_rc_mul()
5274 gen_mulsui_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); in decode_rc_mul()
5285 int r1, r2; in decode_rcpw_insert() local
5291 r1 = MASK_OP_RCPW_S1(ctx->opcode); in decode_rcpw_insert()
5309 tcg_gen_mov_tl(cpu_gpr_d[r2], cpu_gpr_d[r1]); in decode_rcpw_insert()
5313 tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width); in decode_rcpw_insert()
5326 int r1, r3, r4; in decode_rcrw_insert() local
5332 r1 = MASK_OP_RCRW_S1(ctx->opcode); in decode_rcrw_insert()
5356 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], temp2, temp, temp3); in decode_rcrw_insert()
5368 int r1, r3, r4; in decode_rcr_cond_select() local
5374 r1 = MASK_OP_RCR_S1(ctx->opcode); in decode_rcr_cond_select()
5381 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const9, cpu_gpr_d[r4], in decode_rcr_cond_select()
5385 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const9, cpu_gpr_d[r4], in decode_rcr_cond_select()
5392 cpu_gpr_d[r1], temp2); in decode_rcr_cond_select()
5398 cpu_gpr_d[r1], temp2); in decode_rcr_cond_select()
5408 int r1, r3, r4; in decode_rcr_madd() local
5413 r1 = MASK_OP_RCR_S1(ctx->opcode); in decode_rcr_madd()
5420 gen_maddi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); in decode_rcr_madd()
5425 gen_maddi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], in decode_rcr_madd()
5429 gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); in decode_rcr_madd()
5434 gen_maddsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], in decode_rcr_madd()
5441 gen_maddui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], in decode_rcr_madd()
5446 gen_maddsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); in decode_rcr_madd()
5452 gen_maddsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], in decode_rcr_madd()
5463 int r1, r3, r4; in decode_rcr_msub() local
5468 r1 = MASK_OP_RCR_S1(ctx->opcode); in decode_rcr_msub()
5475 gen_msubi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); in decode_rcr_msub()
5480 gen_msubi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], in decode_rcr_msub()
5484 gen_msubsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); in decode_rcr_msub()
5489 gen_msubsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], in decode_rcr_msub()
5496 gen_msubui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], in decode_rcr_msub()
5501 gen_msubsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); in decode_rcr_msub()
5507 gen_msubsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], in decode_rcr_msub()
5521 int r1, r2; in decode_rlc_opc() local
5524 r1 = MASK_OP_RLC_S1(ctx->opcode); in decode_rlc_opc()
5529 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16); in decode_rlc_opc()
5532 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16 << 16); in decode_rlc_opc()
5535 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r1], const16 << 16); in decode_rlc_opc()
5565 gen_mtcr(ctx, cpu_gpr_d[r1], const16); in decode_rlc_opc()
5576 int r3, r2, r1; in decode_rr_accumulator() local
5582 r1 = MASK_OP_RR_S1(ctx->opcode); in decode_rr_accumulator()
5596 gen_absdif(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_accumulator()
5599 gen_helper_absdif_b(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], in decode_rr_accumulator()
5603 gen_helper_absdif_h(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], in decode_rr_accumulator()
5607 gen_helper_absdif_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], in decode_rr_accumulator()
5611 gen_helper_absdif_h_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], in decode_rr_accumulator()
5621 gen_add_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_accumulator()
5624 gen_helper_add_b(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_accumulator()
5627 gen_helper_add_h(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_accumulator()
5630 gen_addc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_accumulator()
5633 gen_adds(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_accumulator()
5636 gen_helper_add_h_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], in decode_rr_accumulator()
5640 gen_helper_add_h_suov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], in decode_rr_accumulator()
5644 gen_helper_add_suov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], in decode_rr_accumulator()
5648 gen_add_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_accumulator()
5651 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
5655 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
5659 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
5663 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
5667 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
5671 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
5675 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
5679 gen_helper_eq_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_accumulator()
5682 gen_helper_eq_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_accumulator()
5686 cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_accumulator()
5689 gen_helper_eqany_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_accumulator()
5692 gen_helper_eqany_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_accumulator()
5695 tcg_gen_setcond_tl(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
5699 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
5703 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
5707 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
5711 gen_helper_lt_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_accumulator()
5714 gen_helper_lt_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_accumulator()
5717 gen_helper_lt_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_accumulator()
5720 gen_helper_lt_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_accumulator()
5724 cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_accumulator()
5728 cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_accumulator()
5731 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
5732 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_accumulator()
5735 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
5736 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_accumulator()
5739 gen_helper_max_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_accumulator()
5742 gen_helper_max_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_accumulator()
5745 gen_helper_max_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_accumulator()
5748 gen_helper_max_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_accumulator()
5751 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
5752 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_accumulator()
5755 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
5756 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_accumulator()
5759 gen_helper_min_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_accumulator()
5762 gen_helper_min_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_accumulator()
5765 gen_helper_min_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_accumulator()
5768 gen_helper_min_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_accumulator()
5778 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); in decode_rr_accumulator()
5795 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
5799 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
5803 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
5807 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
5811 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
5815 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
5819 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
5823 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7f, -0x80); in decode_rr_accumulator()
5826 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xff); in decode_rr_accumulator()
5829 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7fff, -0x8000); in decode_rr_accumulator()
5832 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xffff); in decode_rr_accumulator()
5835 gen_sh_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
5839 gen_sh_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
5843 gen_sh_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
5847 gen_sh_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
5851 gen_sh_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
5855 gen_sh_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
5859 gen_sub_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_accumulator()
5862 gen_helper_sub_b(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_accumulator()
5865 gen_helper_sub_h(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_accumulator()
5868 gen_subc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_accumulator()
5871 gen_subs(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_accumulator()
5874 gen_subsu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_accumulator()
5877 gen_helper_sub_h_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], in decode_rr_accumulator()
5881 gen_helper_sub_h_suov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], in decode_rr_accumulator()
5885 gen_sub_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_accumulator()
5888 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
5892 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
5896 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
5900 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
5904 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
5908 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
5919 int r3, r2, r1; in decode_rr_logical_shift() local
5923 r1 = MASK_OP_RR_S1(ctx->opcode); in decode_rr_logical_shift()
5928 tcg_gen_and_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_logical_shift()
5931 tcg_gen_andc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_logical_shift()
5934 tcg_gen_not_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); in decode_rr_logical_shift()
5938 gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); in decode_rr_logical_shift()
5941 tcg_gen_clrsb_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); in decode_rr_logical_shift()
5944 gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); in decode_rr_logical_shift()
5947 tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], TARGET_LONG_BITS); in decode_rr_logical_shift()
5950 gen_helper_clz_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); in decode_rr_logical_shift()
5953 tcg_gen_nand_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_logical_shift()
5956 tcg_gen_nor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_logical_shift()
5959 tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_logical_shift()
5962 tcg_gen_orc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_logical_shift()
5965 gen_helper_sh(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_logical_shift()
5968 gen_helper_sh_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_logical_shift()
5971 gen_helper_sha(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_logical_shift()
5974 gen_helper_sha_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_logical_shift()
5977 gen_shas(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_logical_shift()
5980 tcg_gen_eqv_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_logical_shift()
5983 tcg_gen_xor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_logical_shift()
5993 int r1, r2, r3; in decode_rr_address() local
5999 r1 = MASK_OP_RR_S1(ctx->opcode); in decode_rr_address()
6004 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]); in decode_rr_address()
6008 tcg_gen_shli_tl(temp, cpu_gpr_d[r1], n); in decode_rr_address()
6013 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 3); in decode_rr_address()
6018 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], in decode_rr_address()
6022 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], 0); in decode_rr_address()
6025 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_a[r1], in decode_rr_address()
6029 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_a[r1], in decode_rr_address()
6042 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], in decode_rr_address()
6046 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], 0); in decode_rr_address()
6049 tcg_gen_sub_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]); in decode_rr_address()
6059 int r1; in decode_rr_idirect() local
6062 r1 = MASK_OP_RR_S1(ctx->opcode); in decode_rr_idirect()
6066 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); in decode_rr_idirect()
6069 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); in decode_rr_idirect()
6074 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); in decode_rr_idirect()
6078 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); in decode_rr_idirect()
6090 int r1, r2, r3; in decode_rr_divide() local
6097 r1 = MASK_OP_RR_S1(ctx->opcode); in decode_rr_divide()
6101 gen_helper_bmerge(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_divide()
6105 gen_bsplit(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]); in decode_rr_divide()
6109 gen_dvinit_b(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], in decode_rr_divide()
6117 tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 8); in decode_rr_divide()
6133 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 24); in decode_rr_divide()
6138 gen_dvinit_h(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], in decode_rr_divide()
6146 tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 16); in decode_rr_divide()
6162 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 16); in decode_rr_divide()
6172 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r1], 0x80000000); in decode_rr_divide()
6182 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); in decode_rr_divide()
6184 tcg_gen_sari_tl(cpu_gpr_d[r3+1], cpu_gpr_d[r1], 31); in decode_rr_divide()
6196 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); in decode_rr_divide()
6201 gen_helper_parity(cpu_gpr_d[r3], cpu_gpr_d[r1]); in decode_rr_divide()
6205 gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]); in decode_rr_divide()
6209 gen_helper_crc32b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_divide()
6216 gen_helper_crc32_be(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_divide()
6223 gen_helper_crc32_le(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_divide()
6231 tcg_gen_ctpop_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); in decode_rr_divide()
6239 GEN_HELPER_RR(divide, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], in decode_rr_divide()
6249 cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_divide()
6255 gen_helper_fmul(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_divide()
6258 gen_helper_fdiv(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_divide()
6262 gen_helper_ftohp(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); in decode_rr_divide()
6269 gen_helper_hptof(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); in decode_rr_divide()
6275 gen_helper_fcmp(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr_divide()
6278 gen_helper_ftoi(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); in decode_rr_divide()
6281 gen_helper_itof(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); in decode_rr_divide()
6284 gen_helper_ftou(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); in decode_rr_divide()
6288 gen_helper_ftouz(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); in decode_rr_divide()
6294 gen_helper_updfl(tcg_env, cpu_gpr_d[r1]); in decode_rr_divide()
6297 gen_helper_utof(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); in decode_rr_divide()
6300 gen_helper_ftoiz(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); in decode_rr_divide()
6303 gen_helper_qseed(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); in decode_rr_divide()
6315 int r1, r2, r3; in decode_rr1_mul() local
6319 r1 = MASK_OP_RR1_S1(ctx->opcode); in decode_rr1_mul()
6329 GEN_HELPER_LL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); in decode_rr1_mul()
6336 GEN_HELPER_LU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); in decode_rr1_mul()
6343 GEN_HELPER_UL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); in decode_rr1_mul()
6350 GEN_HELPER_UU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); in decode_rr1_mul()
6357 GEN_HELPER_LL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); in decode_rr1_mul()
6367 GEN_HELPER_LU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); in decode_rr1_mul()
6377 GEN_HELPER_UL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); in decode_rr1_mul()
6387 GEN_HELPER_UU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); in decode_rr1_mul()
6395 GEN_HELPER_LL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); in decode_rr1_mul()
6399 GEN_HELPER_LU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); in decode_rr1_mul()
6403 GEN_HELPER_UL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); in decode_rr1_mul()
6407 GEN_HELPER_UU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); in decode_rr1_mul()
6418 int r1, r2, r3; in decode_rr1_mulq() local
6423 r1 = MASK_OP_RR1_S1(ctx->opcode); in decode_rr1_mulq()
6434 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], cpu_gpr_d[r2], n, 32); in decode_rr1_mulq()
6438 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_rr1_mulq()
6443 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16); in decode_rr1_mulq()
6448 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0); in decode_rr1_mulq()
6452 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16); in decode_rr1_mulq()
6457 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0); in decode_rr1_mulq()
6460 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); in decode_rr1_mulq()
6465 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); in decode_rr1_mulq()
6470 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); in decode_rr1_mulq()
6475 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); in decode_rr1_mulq()
6488 int r1, r2, r3; in decode_rr2_mul() local
6491 r1 = MASK_OP_RR2_S1(ctx->opcode); in decode_rr2_mul()
6496 gen_mul_i32s(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rr2_mul()
6500 gen_mul_i64s(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], in decode_rr2_mul()
6504 gen_helper_mul_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], in decode_rr2_mul()
6509 gen_mul_i64u(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], in decode_rr2_mul()
6513 gen_helper_mul_suov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], in decode_rr2_mul()
6525 int r1, r2, r3; in decode_rrpw_extract_insert() local
6530 r1 = MASK_OP_RRPW_S1(ctx->opcode); in decode_rrpw_extract_insert()
6541 tcg_gen_sextract_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos, width); in decode_rrpw_extract_insert()
6548 tcg_gen_extract_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos, width); in decode_rrpw_extract_insert()
6565 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); in decode_rrpw_extract_insert()
6567 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_rrpw_extract_insert()
6580 int r1, r2, r3, r4; in decode_rrr_cond_select() local
6584 r1 = MASK_OP_RRR_S1(ctx->opcode); in decode_rrr_cond_select()
6591 gen_cond_add(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_rrr_cond_select()
6595 gen_cond_add(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], in decode_rrr_cond_select()
6599 gen_cond_sub(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], in decode_rrr_cond_select()
6603 gen_cond_sub(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], in decode_rrr_cond_select()
6609 cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rrr_cond_select()
6614 cpu_gpr_d[r1], cpu_gpr_d[r2]); in decode_rrr_cond_select()
6625 int r1, r2, r3, r4; in decode_rrr_divide() local
6628 r1 = MASK_OP_RRR_S1(ctx->opcode); in decode_rrr_divide()
6679 cpu_gpr_d[r3+1], cpu_gpr_d[r1]); in decode_rrr_divide()
6683 gen_helper_crcn(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_rrr_divide()
6690 gen_helper_fadd(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r3]); in decode_rrr_divide()
6693 gen_helper_fsub(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r3]); in decode_rrr_divide()
6696 gen_helper_fmadd(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], in decode_rrr_divide()
6700 gen_helper_fmsub(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], in decode_rrr_divide()
6712 uint32_t r1, r2, r3, r4; in decode_rrr2_madd() local
6715 r1 = MASK_OP_RRR2_S1(ctx->opcode); in decode_rrr2_madd()
6721 gen_madd32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], in decode_rrr2_madd()
6727 gen_madd64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], in decode_rrr2_madd()
6731 gen_helper_madd32_ssov(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], in decode_rrr2_madd()
6737 gen_madds_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], in decode_rrr2_madd()
6743 gen_maddu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], in decode_rrr2_madd()
6747 gen_helper_madd32_suov(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], in decode_rrr2_madd()
6753 gen_maddsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], in decode_rrr2_madd()
6764 uint32_t r1, r2, r3, r4; in decode_rrr2_msub() local
6767 r1 = MASK_OP_RRR2_S1(ctx->opcode); in decode_rrr2_msub()
6774 gen_msub32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], in decode_rrr2_msub()
6780 gen_msub64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], in decode_rrr2_msub()
6784 gen_helper_msub32_ssov(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], in decode_rrr2_msub()
6790 gen_msubs_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], in decode_rrr2_msub()
6796 gen_msubu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], in decode_rrr2_msub()
6800 gen_helper_msub32_suov(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], in decode_rrr2_msub()
6806 gen_msubsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], in decode_rrr2_msub()
6818 uint32_t r1, r2, r3, r4, n; in decode_rrr1_madd() local
6821 r1 = MASK_OP_RRR1_S1(ctx->opcode); in decode_rrr1_madd()
6832 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); in decode_rrr1_madd()
6838 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); in decode_rrr1_madd()
6844 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); in decode_rrr1_madd()
6850 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); in decode_rrr1_madd()
6856 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); in decode_rrr1_madd()
6862 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); in decode_rrr1_madd()
6868 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); in decode_rrr1_madd()
6874 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); in decode_rrr1_madd()
6880 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); in decode_rrr1_madd()
6886 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); in decode_rrr1_madd()
6892 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); in decode_rrr1_madd()
6898 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); in decode_rrr1_madd()
6904 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); in decode_rrr1_madd()
6910 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); in decode_rrr1_madd()
6916 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); in decode_rrr1_madd()
6922 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); in decode_rrr1_madd()
6925 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_madd()
6929 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_madd()
6933 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_madd()
6937 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_madd()
6941 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_madd()
6945 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_madd()
6949 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_madd()
6953 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_madd()
6964 uint32_t r1, r2, r3, r4, n; in decode_rrr1_maddq_h() local
6968 r1 = MASK_OP_RRR1_S1(ctx->opcode); in decode_rrr1_maddq_h()
6979 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_maddq_h()
6986 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_rrr1_maddq_h()
6991 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_maddq_h()
6999 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, in decode_rrr1_maddq_h()
7004 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_maddq_h()
7012 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, in decode_rrr1_maddq_h()
7016 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); in decode_rrr1_maddq_h()
7023 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); in decode_rrr1_maddq_h()
7029 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); in decode_rrr1_maddq_h()
7036 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); in decode_rrr1_maddq_h()
7042 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_maddq_h()
7049 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_rrr1_maddq_h()
7054 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_maddq_h()
7062 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, in decode_rrr1_maddq_h()
7067 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_maddq_h()
7075 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, in decode_rrr1_maddq_h()
7079 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); in decode_rrr1_maddq_h()
7086 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); in decode_rrr1_maddq_h()
7092 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); in decode_rrr1_maddq_h()
7099 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); in decode_rrr1_maddq_h()
7107 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); in decode_rrr1_maddq_h()
7112 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); in decode_rrr1_maddq_h()
7115 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); in decode_rrr1_maddq_h()
7120 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); in decode_rrr1_maddq_h()
7125 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); in decode_rrr1_maddq_h()
7130 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); in decode_rrr1_maddq_h()
7142 uint32_t r1, r2, r3, r4, n; in decode_rrr1_maddsu_h() local
7145 r1 = MASK_OP_RRR1_S1(ctx->opcode); in decode_rrr1_maddsu_h()
7156 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); in decode_rrr1_maddsu_h()
7162 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); in decode_rrr1_maddsu_h()
7168 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); in decode_rrr1_maddsu_h()
7174 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); in decode_rrr1_maddsu_h()
7180 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_rrr1_maddsu_h()
7187 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_rrr1_maddsu_h()
7194 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_rrr1_maddsu_h()
7201 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_rrr1_maddsu_h()
7208 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_rrr1_maddsu_h()
7215 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_rrr1_maddsu_h()
7222 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_rrr1_maddsu_h()
7229 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_rrr1_maddsu_h()
7236 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_rrr1_maddsu_h()
7243 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_rrr1_maddsu_h()
7250 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_rrr1_maddsu_h()
7257 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_rrr1_maddsu_h()
7261 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_maddsu_h()
7265 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_maddsu_h()
7269 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_maddsu_h()
7273 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_maddsu_h()
7277 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_maddsu_h()
7281 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_maddsu_h()
7285 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_maddsu_h()
7289 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_maddsu_h()
7300 uint32_t r1, r2, r3, r4, n; in decode_rrr1_msub() local
7303 r1 = MASK_OP_RRR1_S1(ctx->opcode); in decode_rrr1_msub()
7314 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); in decode_rrr1_msub()
7320 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); in decode_rrr1_msub()
7326 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); in decode_rrr1_msub()
7332 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); in decode_rrr1_msub()
7338 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); in decode_rrr1_msub()
7344 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); in decode_rrr1_msub()
7350 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); in decode_rrr1_msub()
7356 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); in decode_rrr1_msub()
7362 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); in decode_rrr1_msub()
7368 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); in decode_rrr1_msub()
7374 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); in decode_rrr1_msub()
7380 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); in decode_rrr1_msub()
7386 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); in decode_rrr1_msub()
7392 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); in decode_rrr1_msub()
7398 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); in decode_rrr1_msub()
7404 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); in decode_rrr1_msub()
7407 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_msub()
7411 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_msub()
7415 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_msub()
7419 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_msub()
7423 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_msub()
7427 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_msub()
7431 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_msub()
7435 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_msub()
7446 uint32_t r1, r2, r3, r4, n; in decode_rrr1_msubq_h() local
7450 r1 = MASK_OP_RRR1_S1(ctx->opcode); in decode_rrr1_msubq_h()
7461 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_msubq_h()
7468 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_rrr1_msubq_h()
7473 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_msubq_h()
7481 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, in decode_rrr1_msubq_h()
7486 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_msubq_h()
7494 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, in decode_rrr1_msubq_h()
7498 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); in decode_rrr1_msubq_h()
7505 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); in decode_rrr1_msubq_h()
7511 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); in decode_rrr1_msubq_h()
7518 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); in decode_rrr1_msubq_h()
7524 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_msubq_h()
7531 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_rrr1_msubq_h()
7536 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_msubq_h()
7544 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, in decode_rrr1_msubq_h()
7549 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_msubq_h()
7557 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, in decode_rrr1_msubq_h()
7561 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); in decode_rrr1_msubq_h()
7568 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); in decode_rrr1_msubq_h()
7574 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); in decode_rrr1_msubq_h()
7581 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); in decode_rrr1_msubq_h()
7589 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); in decode_rrr1_msubq_h()
7594 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); in decode_rrr1_msubq_h()
7597 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); in decode_rrr1_msubq_h()
7602 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); in decode_rrr1_msubq_h()
7607 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); in decode_rrr1_msubq_h()
7612 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); in decode_rrr1_msubq_h()
7624 uint32_t r1, r2, r3, r4, n; in decode_rrr1_msubad_h() local
7627 r1 = MASK_OP_RRR1_S1(ctx->opcode); in decode_rrr1_msubad_h()
7638 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); in decode_rrr1_msubad_h()
7644 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); in decode_rrr1_msubad_h()
7650 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); in decode_rrr1_msubad_h()
7656 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); in decode_rrr1_msubad_h()
7662 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_rrr1_msubad_h()
7669 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_rrr1_msubad_h()
7676 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_rrr1_msubad_h()
7683 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_rrr1_msubad_h()
7690 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_rrr1_msubad_h()
7697 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_rrr1_msubad_h()
7704 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_rrr1_msubad_h()
7711 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_rrr1_msubad_h()
7718 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_rrr1_msubad_h()
7725 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_rrr1_msubad_h()
7732 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_rrr1_msubad_h()
7739 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], in decode_rrr1_msubad_h()
7743 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_msubad_h()
7747 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_msubad_h()
7751 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_msubad_h()
7755 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_msubad_h()
7759 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_msubad_h()
7763 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_msubad_h()
7767 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_msubad_h()
7771 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rrr1_msubad_h()
7783 int r1, r2, r3, r4; in decode_rrrr_extract_insert() local
7786 r1 = MASK_OP_RRRR_S1(ctx->opcode); in decode_rrrr_extract_insert()
7798 if (r1 == r2) { in decode_rrrr_extract_insert()
7799 tcg_gen_rotl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos); in decode_rrrr_extract_insert()
7803 tcg_gen_shl_tl(tmp_width, cpu_gpr_d[r1], tmp_pos); in decode_rrrr_extract_insert()
7809 * which effectivly returns cpu_gpr_d[r1] in decode_rrrr_extract_insert()
7822 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos); in decode_rrrr_extract_insert()
7834 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], tmp_width, in decode_rrrr_extract_insert()
7846 int r1, r2, r3, r4; in decode_rrrw_extract_insert() local
7852 r1 = MASK_OP_RRRW_S1(ctx->opcode); in decode_rrrw_extract_insert()
7865 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp); in decode_rrrw_extract_insert()
7873 tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp); in decode_rrrw_extract_insert()
7891 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], temp, temp2); in decode_rrrw_extract_insert()
7902 uint32_t r1; in decode_sys_interrupts() local
7907 r1 = MASK_OP_SYS_S1D(ctx->opcode); in decode_sys_interrupts()
7923 tcg_gen_extract_tl(cpu_gpr_d[r1], cpu_ICR, in decode_sys_interrupts()
7980 tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], in decode_sys_interrupts()
8010 int32_t r1, r2, r3; in decode_32Bit_opc() local
8045 r1 = MASK_OP_ABS_S1D(ctx->opcode); in decode_32Bit_opc()
8049 tcg_gen_shri_tl(temp2, cpu_gpr_d[r1], 16); in decode_32Bit_opc()
8054 r1 = MASK_OP_ABS_S1D(ctx->opcode); in decode_32Bit_opc()
8057 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); in decode_32Bit_opc()
8058 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); in decode_32Bit_opc()
8062 r1 = MASK_OP_ABS_S1D(ctx->opcode); in decode_32Bit_opc()
8067 tcg_gen_movi_tl(cpu_gpr_a[r1], address << 14); in decode_32Bit_opc()
8073 tcg_gen_movi_tl(cpu_gpr_a[r1], EA_ABS_FORMAT(address)); in decode_32Bit_opc()
8163 r1 = MASK_OP_BRC_S1(ctx->opcode); in decode_32Bit_opc()
8164 gen_compute_branch(ctx, op1, r1, 0, const4, address); in decode_32Bit_opc()
8169 r1 = MASK_OP_BRN_S1(ctx->opcode); in decode_32Bit_opc()
8170 gen_compute_branch(ctx, op1, r1, 0, 0, address); in decode_32Bit_opc()
8182 r1 = MASK_OP_BRR_S1(ctx->opcode); in decode_32Bit_opc()
8183 gen_compute_branch(ctx, op1, r1, r2, 0, address); in decode_32Bit_opc()
8204 r1 = MASK_OP_RCRR_S1(ctx->opcode); in decode_32Bit_opc()
8217 gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, temp2, temp3); in decode_32Bit_opc()
8278 r1 = MASK_OP_RRPW_S1(ctx->opcode); in decode_32Bit_opc()
8283 tcg_gen_extract2_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], cpu_gpr_d[r1], in decode_32Bit_opc()