4  * Copyright (c) 2003-2005 Fabrice Bellard
30 int sparc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)  in sparc_cpu_gdb_read_register()  argument
34     if (n < 8) {  in sparc_cpu_gdb_read_register()
36         return gdb_get_rega(mem_buf, env->gregs[n]);  in sparc_cpu_gdb_read_register()
38     if (n < 32) {  in sparc_cpu_gdb_read_register()
40         return gdb_get_rega(mem_buf, env->regwptr[n - 8]);  in sparc_cpu_gdb_read_register()
43     if (n < 64) {  in sparc_cpu_gdb_read_register()
45         if (n & 1) {  in sparc_cpu_gdb_read_register()
46             return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.lower);  in sparc_cpu_gdb_read_register()
48             return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.upper);  in sparc_cpu_gdb_read_register()
52     switch (n) {  in sparc_cpu_gdb_read_register()
54         return gdb_get_rega(mem_buf, env->y);  in sparc_cpu_gdb_read_register()
58         return gdb_get_rega(mem_buf, env->wim);  in sparc_cpu_gdb_read_register()
60         return gdb_get_rega(mem_buf, env->tbr);  in sparc_cpu_gdb_read_register()
62         return gdb_get_rega(mem_buf, env->pc);  in sparc_cpu_gdb_read_register()
64         return gdb_get_rega(mem_buf, env->npc);  in sparc_cpu_gdb_read_register()
73     if (n < 64) {  in sparc_cpu_gdb_read_register()
74         /* f0-f31 */  in sparc_cpu_gdb_read_register()
75         if (n & 1) {  in sparc_cpu_gdb_read_register()
76             return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.lower);  in sparc_cpu_gdb_read_register()
78             return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.upper);  in sparc_cpu_gdb_read_register()
81     if (n < 80) {  in sparc_cpu_gdb_read_register()
82         /* f32-f62 (16 double width registers, even register numbers only)  in sparc_cpu_gdb_read_register()
83          * n == 64: f32 : env->fpr[16]  in sparc_cpu_gdb_read_register()
84          * n == 65: f34 : env->fpr[17]  in sparc_cpu_gdb_read_register()
86          * n == 79: f62 : env->fpr[31]  in sparc_cpu_gdb_read_register()
88         return gdb_get_reg64(mem_buf, env->fpr[(n - 64) + 16].ll);  in sparc_cpu_gdb_read_register()
90     switch (n) {  in sparc_cpu_gdb_read_register()
92         return gdb_get_regl(mem_buf, env->pc);  in sparc_cpu_gdb_read_register()
94         return gdb_get_regl(mem_buf, env->npc);  in sparc_cpu_gdb_read_register()
97                                      ((env->asi & 0xff) << 24) |  in sparc_cpu_gdb_read_register()
98                                      ((env->pstate & 0xfff) << 8) |  in sparc_cpu_gdb_read_register()
103         return gdb_get_regl(mem_buf, env->fprs);  in sparc_cpu_gdb_read_register()
105         return gdb_get_regl(mem_buf, env->y);  in sparc_cpu_gdb_read_register()
111 int sparc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)  in sparc_cpu_gdb_write_register()  argument
114     CPUSPARCState *env = &cpu->env;  in sparc_cpu_gdb_write_register()
125     if (n < 8) {  in sparc_cpu_gdb_write_register()
127         env->gregs[n] = tmp;  in sparc_cpu_gdb_write_register()
128     } else if (n < 32) {  in sparc_cpu_gdb_write_register()
130         env->regwptr[n - 8] = tmp;  in sparc_cpu_gdb_write_register()
133     else if (n < 64) {  in sparc_cpu_gdb_write_register()
135         /* f0-f31 */  in sparc_cpu_gdb_write_register()
136         if (n & 1) {  in sparc_cpu_gdb_write_register()
137             env->fpr[(n - 32) / 2].l.lower = tmp;  in sparc_cpu_gdb_write_register()
139             env->fpr[(n - 32) / 2].l.upper = tmp;  in sparc_cpu_gdb_write_register()
143         switch (n) {  in sparc_cpu_gdb_write_register()
145             env->y = tmp;  in sparc_cpu_gdb_write_register()
151             env->wim = tmp;  in sparc_cpu_gdb_write_register()
154             env->tbr = tmp;  in sparc_cpu_gdb_write_register()
157             env->pc = tmp;  in sparc_cpu_gdb_write_register()
160             env->npc = tmp;  in sparc_cpu_gdb_write_register()
171     else if (n < 64) {  in sparc_cpu_gdb_write_register()
172         /* f0-f31 */  in sparc_cpu_gdb_write_register()
174         if (n & 1) {  in sparc_cpu_gdb_write_register()
175             env->fpr[(n - 32) / 2].l.lower = tmp;  in sparc_cpu_gdb_write_register()
177             env->fpr[(n - 32) / 2].l.upper = tmp;  in sparc_cpu_gdb_write_register()
180     } else if (n < 80) {  in sparc_cpu_gdb_write_register()
181         /* f32-f62 (16 double width registers, even register numbers only)  in sparc_cpu_gdb_write_register()
182          * n == 64: f32 : env->fpr[16]  in sparc_cpu_gdb_write_register()
183          * n == 65: f34 : env->fpr[17]  in sparc_cpu_gdb_write_register()
185          * n == 79: f62 : env->fpr[31]  in sparc_cpu_gdb_write_register()
187         env->fpr[(n - 64) + 16].ll = tmp;  in sparc_cpu_gdb_write_register()
189         switch (n) {  in sparc_cpu_gdb_write_register()
191             env->pc = tmp;  in sparc_cpu_gdb_write_register()
194             env->npc = tmp;  in sparc_cpu_gdb_write_register()
198             env->asi = (tmp >> 24) & 0xff;  in sparc_cpu_gdb_write_register()
199             env->pstate = (tmp >> 8) & 0xfff;  in sparc_cpu_gdb_write_register()
206             env->fprs = tmp;  in sparc_cpu_gdb_write_register()
209             env->y = tmp;  in sparc_cpu_gdb_write_register()