target/sparc/cpu.h

5 #include "cpu-qom.h"
6 #include "exec/cpu-common.h"
7 #include "exec/cpu-defs.h"
8 #include "exec/cpu-interrupt.h"
9 #include "qemu/cpu-float.h"
245 #include "cpu-feature.h.inc"
252 #include "cpu-feature.h.inc"
341 /* Leon3 cache control */
343 /* Cache control: emulate the behavior of cache control registers but without
351 /* Cache Control register fields */
353 #define CACHE_CTRL_IF (1 <<  4)  /* Instruction Cache Freeze on Interrupt */
354 #define CACHE_CTRL_DF (1 <<  5)  /* Data Cache Freeze on Interrupt */
355 #define CACHE_CTRL_DP (1 << 14)  /* Data cache flush pending */
356 #define CACHE_CTRL_IP (1 << 15)  /* Instruction cache flush pending */
358 #define CACHE_CTRL_FI (1 << 21)  /* Flush Instruction cache (Write only) */
359 #define CACHE_CTRL_FD (1 << 22)  /* Flush Data cache (Write only) */
360 #define CACHE_CTRL_DS (1 << 23)  /* Data cache snoop enable */
407     target_ulong npc;      /* next program counter */
418      * Z is represented as == 0; any non-zero value is !Z.
419      * For sparc64, the high 32-bits of icc.Z are garbage.
446      * Single-element FPU fault queue, with address and insn,
447      * packaged into the double-word with which it is stored.
476     uint32_t psrpil;   /* interrupt blocking level */
477     uint32_t pil_in;   /* incoming interrupt level bitmap */
514 #define MAXTL_MASK (MAXTL_MAX - 1)
643 #define MMU_CONTEXT_MASK ((1 << MMU_CONTEXT_BITS) - 1)
648     return compare_masked(context, tlb->tag, MMU_CONTEXT_MASK);  in tlb_compare_context()
653 /* cpu-exec.c */
685     return env1->def.features & CPU_FEATURE_HYPV;  in cpu_has_hypervisor()
690     return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV);  in cpu_hypervisor_mode()
695     return env1->pstate & PS_PRIV;  in cpu_supervisor_mode()
700     return env1->psrs;  in cpu_supervisor_mode()
707     if (env1->psret != 0)  in cpu_interrupts_enabled()
710     if ((env1->pstate & PS_IE) && !cpu_hypervisor_mode(env1)) {  in cpu_interrupts_enabled()
721     /* level 15 is non-maskable on sparc v8 */  in cpu_pil_allowed()
722     return pil == 15 || pil > env1->psrpil;  in cpu_pil_allowed()
724     return pil > env1->psrpil;  in cpu_pil_allowed()
772         ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) |  in sparc64_tstate()
775     if (env->def.features & CPU_FEATURE_GL) {  in sparc64_tstate()
776         tstate |= (env->gl & 7ULL) << 40;  in sparc64_tstate()