target/sparc/cpu.h

403 struct CPUArchState {  struct
404     target_ulong gregs[8]; /* general registers */
405     target_ulong *regwptr; /* pointer to current register window */
406     target_ulong pc;       /* program counter */
407     target_ulong npc;      /* next program counter */
408     target_ulong y;        /* multiply/divide register */
414     target_long cc_N;
415     target_long cc_V;
421     target_ulong icc_Z;
423     target_ulong xcc_Z;
431     target_ulong icc_C;
433     target_ulong xcc_C;
436     target_ulong cond; /* conditional branch result (XXX: save it in a
440     uint32_t fsr;                    /* rm, tem, aexc */
441     uint32_t fsr_cexc_ftt;           /* cexc, ftt */
442     uint32_t fcc[TARGET_FCCREGS];    /* fcc* */
449     uint32_t fsr_qne;                /* qne */
450     union {
461     } fq;
464     CPU_DoubleU fpr[TARGET_DPREGS];  /* floating point registers */
465     uint32_t cwp;      /* index of current register window (extracted
468     uint32_t wim;      /* window invalid mask */
470     target_ulong tbr;  /* trap base register */
472     int      psrs;     /* supervisor mode (extracted from PSR) */
473     int      psrps;    /* previous supervisor mode */
474     int      psret;    /* enable traps */
476     uint32_t psrpil;   /* interrupt blocking level */
477     uint32_t pil_in;   /* incoming interrupt level bitmap */
479     int      psref;    /* enable fpu */
481     int interrupt_index;
483     target_ulong regbase[MAX_NWINDOWS * 16 + 8];
486     struct {} end_reset_fields;
489     target_ulong version;
490     uint32_t nwindows;
494     uint64_t lsu;
497     SparcV9MMU immu;
498     SparcV9MMU dmmu;
499     SparcTLBEntry itlb[64];
500     SparcTLBEntry dtlb[64];
501     uint32_t mmu_version;
503     uint32_t mmuregs[32];
504     uint64_t mxccdata[4];
505     uint64_t mxccregs[8];
506     uint32_t mmubpctrv, mmubpctrc, mmubpctrs;
507     uint64_t mmubpaction;
508     uint64_t mmubpregs[4];
509     uint64_t prom_addr;
511     float_status fp_status;
515     trap_state ts[MAXTL_MAX];
516     uint32_t asi;
517     uint32_t pstate;
518     uint32_t tl;
519     uint32_t maxtl;
520     uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
521     uint64_t agregs[8]; /* alternate general registers */
522     uint64_t bgregs[8]; /* backup for normal global registers */
523     uint64_t igregs[8]; /* interrupt general registers */
524     uint64_t mgregs[8]; /* mmu general registers */
525     uint64_t glregs[8 * MAXTL_MAX];
526     uint32_t fprs;
527     uint64_t tick_cmpr, stick_cmpr;
528     CPUTimer *tick, *stick;
531     uint64_t gsr;
532     uint32_t gl; // UA2005
534     uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr;
535     uint64_t scratch[8];
536     CPUTimer *hstick; // UA 2005
538     uint64_t ivec_status;
539     uint64_t ivec_data[3];
540     uint32_t softint;
546     sparc_def_t def;
549     DeviceState *irq_manager;
550     void (*qemu_irq_ack)(CPUSPARCState *env, int intno);
551     uint32_t cache_control;