Lines Matching +full:- +full:- +full:without +full:- +full:default +full:- +full:features
4 * Copyright (c) 2003-2005 Fabrice Bellard
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 #include "qemu/qemu-print.h"
25 #include "accel/tcg/cpu-mmu-index.h"
26 #include "exec/translation-block.h"
27 #include "hw/qdev-properties.h"
41 if (scc->parent_phases.hold) { in sparc_cpu_reset_hold()
42 scc->parent_phases.hold(obj, type); in sparc_cpu_reset_hold()
46 env->cwp = 0; in sparc_cpu_reset_hold()
48 env->wim = 1; in sparc_cpu_reset_hold()
50 env->regwptr = env->regbase + (env->cwp * 16); in sparc_cpu_reset_hold()
53 env->cleanwin = env->nwindows - 2; in sparc_cpu_reset_hold()
54 env->cansave = env->nwindows - 2; in sparc_cpu_reset_hold()
55 env->pstate = PS_RMO | PS_PEF | PS_IE; in sparc_cpu_reset_hold()
56 env->asi = 0x82; /* Primary no-fault */ in sparc_cpu_reset_hold()
60 env->psret = 0; in sparc_cpu_reset_hold()
61 env->psrs = 1; in sparc_cpu_reset_hold()
62 env->psrps = 1; in sparc_cpu_reset_hold()
65 env->pstate = PS_PRIV | PS_RED | PS_PEF; in sparc_cpu_reset_hold()
67 env->pstate |= PS_AG; in sparc_cpu_reset_hold()
69 env->hpstate = cpu_has_hypervisor(env) ? HS_PRIV : 0; in sparc_cpu_reset_hold()
70 env->tl = env->maxtl; in sparc_cpu_reset_hold()
71 env->gl = 2; in sparc_cpu_reset_hold()
72 cpu_tsptr(env)->tt = TT_POWER_ON_RESET; in sparc_cpu_reset_hold()
73 env->lsu = 0; in sparc_cpu_reset_hold()
75 env->mmuregs[0] &= ~(MMU_E | MMU_NF); in sparc_cpu_reset_hold()
76 env->mmuregs[0] |= env->def.mmu_bm; in sparc_cpu_reset_hold()
78 env->pc = 0; in sparc_cpu_reset_hold()
79 env->npc = env->pc + 4; in sparc_cpu_reset_hold()
81 env->cache_control = 0; in sparc_cpu_reset_hold()
91 if (cpu_interrupts_enabled(env) && env->interrupt_index > 0) { in sparc_cpu_exec_interrupt()
92 int pil = env->interrupt_index & 0xf; in sparc_cpu_exec_interrupt()
93 int type = env->interrupt_index & 0xf0; in sparc_cpu_exec_interrupt()
96 cs->exception_index = env->interrupt_index; in sparc_cpu_exec_interrupt()
108 info->print_insn = print_insn_sparc; in cpu_sparc_disas_set_info()
109 info->endian = BFD_ENDIAN_BIG; in cpu_sparc_disas_set_info()
111 info->mach = bfd_mach_sparc_v9b; in cpu_sparc_disas_set_info()
119 prop->driver = typename; in cpu_add_feat_as_prop()
120 prop->property = g_strdup(name); in cpu_add_feat_as_prop()
121 prop->value = g_strdup(val); in cpu_add_feat_as_prop()
125 /* Parse "+feature,-feature,feature=foo" CPU feature string */
126 static void sparc_cpu_parse_features(const char *typename, char *features, in sparc_cpu_parse_features() argument
138 if (!features) { in sparc_cpu_parse_features()
142 for (featurestr = strtok(features, ","); in sparc_cpu_parse_features()
154 } else if (featurestr[0] == '-') { in sparc_cpu_parse_features()
167 * Temporarily, only +feat/-feat will be supported in sparc_cpu_parse_features()
169 * minus-overrides-plus semantics and just follow in sparc_cpu_parse_features()
170 * the order options appear on the command-line. in sparc_cpu_parse_features()
172 * TODO: warn if user is relying on minus-override-plus semantics in sparc_cpu_parse_features()
173 * TODO: remove minus-override-plus semantics after in sparc_cpu_parse_features()
191 for (l = plus_features; l; l = l->next) { in sparc_cpu_parse_features()
192 const char *name = l->data; in sparc_cpu_parse_features()
197 for (l = minus_features; l; l = l->next) { in sparc_cpu_parse_features()
198 const char *name = l->data; in sparc_cpu_parse_features()
207 env->mxccregs[7] = ((cpu + 8) & 0xf) << 24; in cpu_sparc_set_id()
214 .name = "Fujitsu-Sparc64",
220 .features = CPU_DEFAULT_FEATURES,
223 .name = "Fujitsu-Sparc64-III",
229 .features = CPU_DEFAULT_FEATURES,
232 .name = "Fujitsu-Sparc64-IV",
238 .features = CPU_DEFAULT_FEATURES,
241 .name = "Fujitsu-Sparc64-V",
247 .features = CPU_DEFAULT_FEATURES,
250 .name = "TI-UltraSparc-I",
256 .features = CPU_DEFAULT_FEATURES,
259 .name = "TI-UltraSparc-II",
265 .features = CPU_DEFAULT_FEATURES,
268 .name = "TI-UltraSparc-IIi",
274 .features = CPU_DEFAULT_FEATURES,
277 .name = "TI-UltraSparc-IIe",
283 .features = CPU_DEFAULT_FEATURES,
286 .name = "Sun-UltraSparc-III",
292 .features = CPU_DEFAULT_FEATURES,
295 .name = "Sun-UltraSparc-III-Cu",
301 .features = CPU_DEFAULT_FEATURES,
304 .name = "Sun-UltraSparc-IIIi",
310 .features = CPU_DEFAULT_FEATURES,
313 .name = "Sun-UltraSparc-IV",
319 .features = CPU_DEFAULT_FEATURES,
322 .name = "Sun-UltraSparc-IV-plus",
328 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT,
331 .name = "Sun-UltraSparc-IIIi-plus",
337 .features = CPU_DEFAULT_FEATURES,
340 .name = "Sun-UltraSparc-T1",
347 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
351 .name = "Sun-UltraSparc-T2",
358 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
362 .name = "NEC-UltraSparc-I",
368 .features = CPU_DEFAULT_FEATURES,
372 .name = "Fujitsu-MB86904",
382 .features = CPU_DEFAULT_FEATURES,
385 .name = "Fujitsu-MB86907",
395 .features = CPU_DEFAULT_FEATURES,
398 .name = "TI-MicroSparc-I",
408 .features = CPU_FEATURE_MUL | CPU_FEATURE_DIV,
411 .name = "TI-MicroSparc-II",
421 .features = CPU_DEFAULT_FEATURES,
424 .name = "TI-MicroSparc-IIep",
434 .features = CPU_DEFAULT_FEATURES,
437 .name = "TI-SuperSparc-40", /* STP1020NPGA */
447 .features = CPU_DEFAULT_FEATURES,
450 .name = "TI-SuperSparc-50", /* STP1020PGA */
460 .features = CPU_DEFAULT_FEATURES,
463 .name = "TI-SuperSparc-51",
474 .features = CPU_DEFAULT_FEATURES,
477 .name = "TI-SuperSparc-60", /* STP1020APGA */
487 .features = CPU_DEFAULT_FEATURES,
490 .name = "TI-SuperSparc-61",
501 .features = CPU_DEFAULT_FEATURES,
504 .name = "TI-SuperSparc-II",
515 .features = CPU_DEFAULT_FEATURES,
528 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN,
541 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN |
568 static void print_features(uint32_t features, const char *prefix) in print_features() argument
573 if (feature_name[i] && (features & (1 << i))) { in print_features()
588 qemu_printf(" %-20s (IU " TARGET_FMT_lx in sparc_cpu_list()
595 print_features(CPU_DEFAULT_FEATURES & ~sparc_defs[i].features, "-"); in sparc_cpu_list()
596 print_features(~CPU_DEFAULT_FEATURES & sparc_defs[i].features, "+"); in sparc_cpu_list()
599 qemu_printf("Default CPU feature flags (use '-' to remove): "); in sparc_cpu_list()
605 qemu_printf("Numerical features (use '=' to set): iu_version " in sparc_cpu_list()
611 qemu_fprintf(f, "%c%c%c%c", cc & PSR_NEG ? 'N' : '-', in cpu_print_cc()
612 cc & PSR_ZERO ? 'Z' : '-', cc & PSR_OVF ? 'V' : '-', in cpu_print_cc()
613 cc & PSR_CARRY ? 'C' : '-'); in cpu_print_cc()
627 qemu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, in sparc_cpu_dump_state()
628 env->npc); in sparc_cpu_dump_state()
632 qemu_fprintf(f, "%%g%d-%d:", i, i + REGS_PER_LINE - 1); in sparc_cpu_dump_state()
634 qemu_fprintf(f, " " TARGET_FMT_lx, env->gregs[i]); in sparc_cpu_dump_state()
635 if (i % REGS_PER_LINE == REGS_PER_LINE - 1) { in sparc_cpu_dump_state()
642 qemu_fprintf(f, "%%%c%d-%d: ", in sparc_cpu_dump_state()
644 i, i + REGS_PER_LINE - 1); in sparc_cpu_dump_state()
646 qemu_fprintf(f, TARGET_FMT_lx " ", env->regwptr[i + x * 8]); in sparc_cpu_dump_state()
647 if (i % REGS_PER_LINE == REGS_PER_LINE - 1) { in sparc_cpu_dump_state()
658 qemu_fprintf(f, " %016" PRIx64, env->fpr[i].ll); in sparc_cpu_dump_state()
666 qemu_fprintf(f, "pstate: %08x ccr: %02x (icc: ", env->pstate, in sparc_cpu_dump_state()
670 cpu_print_cc(f, cpu_get_ccr(env) << (PSR_CARRY_SHIFT - 4)); in sparc_cpu_dump_state()
671 qemu_fprintf(f, ") asi: %02x tl: %d pil: %x gl: %d\n", env->asi, env->tl, in sparc_cpu_dump_state()
672 env->psrpil, env->gl); in sparc_cpu_dump_state()
674 TARGET_FMT_lx "\n", env->tbr, env->hpstate, env->htba); in sparc_cpu_dump_state()
677 env->cansave, env->canrestore, env->otherwin, env->wstate, in sparc_cpu_dump_state()
678 env->cleanwin, env->nwindows - 1 - env->cwp); in sparc_cpu_dump_state()
680 cpu_get_fsr(env), env->y, env->fprs); in sparc_cpu_dump_state()
685 qemu_fprintf(f, " SPE: %c%c%c) wim: %08x\n", env->psrs ? 'S' : '-', in sparc_cpu_dump_state()
686 env->psrps ? 'P' : '-', env->psret ? 'E' : '-', in sparc_cpu_dump_state()
687 env->wim); in sparc_cpu_dump_state()
689 cpu_get_fsr(env), env->y); in sparc_cpu_dump_state()
698 cpu->env.pc = value; in sparc_cpu_set_pc()
699 cpu->env.npc = value + 4; in sparc_cpu_set_pc()
706 return cpu->env.pc; in sparc_cpu_get_pc()
715 cpu->env.pc = tb->pc; in sparc_cpu_synchronize_from_tb()
716 cpu->env.npc = tb->cs_base; in sparc_cpu_synchronize_from_tb()
735 if (env->pstate & PS_AM) { in sparc_get_tb_cpu_state()
738 if ((env->pstate & PS_PEF) && (env->fprs & FPRS_FEF)) { in sparc_get_tb_cpu_state()
741 flags |= env->asi << TB_FLAG_ASI_SHIFT; in sparc_get_tb_cpu_state()
743 if (env->psref) { in sparc_get_tb_cpu_state()
747 if (env->fsr_qne) { in sparc_get_tb_cpu_state()
754 .pc = env->pc, in sparc_get_tb_cpu_state()
756 .cs_base = env->npc, in sparc_get_tb_cpu_state()
768 env->pc = pc; in sparc_restore_state_to_opc()
773 if (env->cond) { in sparc_restore_state_to_opc()
774 env->npc = npc & ~3; in sparc_restore_state_to_opc()
776 env->npc = pc + 4; in sparc_restore_state_to_opc()
779 env->npc = npc; in sparc_restore_state_to_opc()
786 return (cs->interrupt_request & CPU_INTERRUPT_HARD) && in sparc_cpu_has_work()
796 if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */ in sparc_cpu_mmu_index()
799 return env->psrs; in sparc_cpu_mmu_index()
804 ? (env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0 in sparc_cpu_mmu_index()
805 : (env->lsu & DMMU_E) == 0) { in sparc_cpu_mmu_index()
809 } else if (env->tl > 0) { in sparc_cpu_mmu_index()
825 * as type names shouldn't have spaces replace them with '-' in sparc_cpu_type_name()
828 *s = '-'; in sparc_cpu_type_name()
842 if (g_str_equal(typename, SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IV+"))) { in sparc_cpu_class_by_name()
844 typename = g_strdup(SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IV-plus")); in sparc_cpu_class_by_name()
845 } else if (g_str_equal(typename, SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IIIi+"))) { in sparc_cpu_class_by_name()
847 typename = g_strdup(SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IIIi-plus")); in sparc_cpu_class_by_name()
864 env->def.features |= CPU_FEATURE_FLOAT128; in sparc_cpu_realizefn()
867 env->version = env->def.iu_version; in sparc_cpu_realizefn()
868 env->nwindows = env->def.nwindows; in sparc_cpu_realizefn()
870 env->mmuregs[0] |= env->def.mmu_version; in sparc_cpu_realizefn()
872 env->mxccregs[7] |= env->def.mxcc_version; in sparc_cpu_realizefn()
874 env->mmu_version = env->def.mmu_version; in sparc_cpu_realizefn()
875 env->maxtl = env->def.maxtl; in sparc_cpu_realizefn()
876 env->version |= env->def.maxtl << 8; in sparc_cpu_realizefn()
877 env->version |= env->def.nwindows - 1; in sparc_cpu_realizefn()
885 set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status); in sparc_cpu_realizefn()
886 /* For fused-multiply add, prefer SNaN over QNaN, then C->B->A */ in sparc_cpu_realizefn()
887 set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status); in sparc_cpu_realizefn()
889 set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); in sparc_cpu_realizefn()
890 /* Default NaN value: sign bit clear, all frac bits set */ in sparc_cpu_realizefn()
891 set_float_default_nan_pattern(0b01111111, &env->fp_status); in sparc_cpu_realizefn()
901 scc->parent_realize(dev, errp); in sparc_cpu_realizefn()
908 CPUSPARCState *env = &cpu->env; in sparc_cpu_initfn()
910 if (scc->cpu_def) { in sparc_cpu_initfn()
911 env->def = *scc->cpu_def; in sparc_cpu_initfn()
919 int64_t value = cpu->env.def.nwindows; in sparc_get_nwindows()
943 cpu->env.def.nwindows = value; in sparc_set_nwindows()
955 DEFINE_PROP_BIT("float128", SPARCCPU, env.def.features,
958 DEFINE_PROP_BIT("cmt", SPARCCPU, env.def.features,
960 DEFINE_PROP_BIT("gl", SPARCCPU, env.def.features,
962 DEFINE_PROP_BIT("hypv", SPARCCPU, env.def.features,
964 DEFINE_PROP_BIT("vis1", SPARCCPU, env.def.features,
966 DEFINE_PROP_BIT("vis2", SPARCCPU, env.def.features,
968 DEFINE_PROP_BIT("fmaf", SPARCCPU, env.def.features,
970 DEFINE_PROP_BIT("vis3", SPARCCPU, env.def.features,
972 DEFINE_PROP_BIT("ima", SPARCCPU, env.def.features,
974 DEFINE_PROP_BIT("vis4", SPARCCPU, env.def.features,
977 DEFINE_PROP_BIT("mul", SPARCCPU, env.def.features,
979 DEFINE_PROP_BIT("div", SPARCCPU, env.def.features,
981 DEFINE_PROP_BIT("fsmuld", SPARCCPU, env.def.features,
984 DEFINE_PROP_UNSIGNED("iu-version", SPARCCPU, env.def.iu_version, 0,
986 DEFINE_PROP_UINT32("fpu-version", SPARCCPU, env.def.fpu_version, 0),
987 DEFINE_PROP_UINT32("mmu-version", SPARCCPU, env.def.mmu_version, 0),
993 #include "hw/core/sysemu-cpu-ops.h"
1003 #include "accel/tcg/cpu-ops.h"
1010 return cpu_env(cs)->pstate & PS_AM ? (uint32_t)result : result; in sparc_pointer_wrap()
1027 * implemented in some non-Sun SPARC V9 implementations, but is not
1070 &scc->parent_realize); in sparc_cpu_class_init()
1074 &scc->parent_phases); in sparc_cpu_class_init()
1076 cc->class_by_name = sparc_cpu_class_by_name; in sparc_cpu_class_init()
1077 cc->list_cpus = sparc_cpu_list, in sparc_cpu_class_init()
1078 cc->parse_features = sparc_cpu_parse_features; in sparc_cpu_class_init()
1079 cc->dump_state = sparc_cpu_dump_state; in sparc_cpu_class_init()
1081 cc->memory_rw_debug = sparc_cpu_memory_rw_debug; in sparc_cpu_class_init()
1083 cc->set_pc = sparc_cpu_set_pc; in sparc_cpu_class_init()
1084 cc->get_pc = sparc_cpu_get_pc; in sparc_cpu_class_init()
1085 cc->gdb_read_register = sparc_cpu_gdb_read_register; in sparc_cpu_class_init()
1086 cc->gdb_write_register = sparc_cpu_gdb_write_register; in sparc_cpu_class_init()
1088 cc->sysemu_ops = &sparc_sysemu_ops; in sparc_cpu_class_init()
1090 cc->disas_set_info = cpu_sparc_disas_set_info; in sparc_cpu_class_init()
1093 cc->gdb_num_core_regs = 86; in sparc_cpu_class_init()
1095 cc->gdb_num_core_regs = 72; in sparc_cpu_class_init()
1097 cc->tcg_ops = &sparc_tcg_ops; in sparc_cpu_class_init()
1114 scc->cpu_def = data; in sparc_cpu_cpudef_class_init()
1119 char *typename = sparc_cpu_type_name(def->name); in sparc_register_cpudef_type()