Lines Matching +full:lock +full:- +full:pr
22 #include "tcg/tcg-op.h"
23 #include "exec/helper-proto.h"
24 #include "exec/helper-gen.h"
25 #include "exec/translation-block.h"
29 #include "qemu/qemu-print.h"
32 #include "exec/helper-info.c.inc"
40 uint32_t envflags; /* should stay in sync with env->flags using TCG ops */
54 #define UNALIGN(C) (ctx->tbflags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN)
56 #define IS_USER(ctx) (!(ctx->tbflags & (1u << SR_MD)))
60 /* Target-specific values for ctx->base.is_jmp. */
132 offsetof(CPUSH4State, pr), "PR"); in sh4_translate_init()
165 qemu_fprintf(f, "pc=0x%08x sr=0x%08x pr=0x%08x fpscr=0x%08x\n", in superh_cpu_dump_state()
166 env->pc, cpu_read_sr(env), env->pr, env->fpscr); in superh_cpu_dump_state()
168 env->spc, env->ssr, env->gbr, env->vbr); in superh_cpu_dump_state()
170 env->sgr, env->dbr, env->delayed_pc, env->fpul); in superh_cpu_dump_state()
173 i, env->gregs[i], i + 1, env->gregs[i + 1], in superh_cpu_dump_state()
174 i + 2, env->gregs[i + 2], i + 3, env->gregs[i + 3]); in superh_cpu_dump_state()
176 if (env->flags & TB_FLAG_DELAY_SLOT) { in superh_cpu_dump_state()
178 env->delayed_pc); in superh_cpu_dump_state()
179 } else if (env->flags & TB_FLAG_DELAY_SLOT_COND) { in superh_cpu_dump_state()
181 env->delayed_pc); in superh_cpu_dump_state()
182 } else if (env->flags & TB_FLAG_DELAY_SLOT_RTE) { in superh_cpu_dump_state()
184 env->delayed_pc); in superh_cpu_dump_state()
211 tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); in gen_save_cpu_state()
213 if (ctx->delayed_pc != (uint32_t) -1) { in gen_save_cpu_state()
214 tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc); in gen_save_cpu_state()
216 if ((ctx->tbflags & TB_FLAG_ENVFLAGS_MASK) != ctx->envflags) { in gen_save_cpu_state()
217 tcg_gen_movi_i32(cpu_flags, ctx->envflags); in gen_save_cpu_state()
223 return (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE) != 0; in use_exit_tb()
231 return translator_use_goto_tb(&ctx->base, dest); in use_goto_tb()
239 tcg_gen_exit_tb(ctx->base.tb, n); in gen_goto_tb()
248 ctx->base.is_jmp = DISAS_NORETURN; in gen_goto_tb()
253 if (ctx->delayed_pc == -1) { in gen_jump()
263 ctx->base.is_jmp = DISAS_NORETURN; in gen_jump()
265 gen_goto_tb(ctx, 0, ctx->delayed_pc); in gen_jump()
276 if (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE) { in gen_conditional_jump()
281 tcg_gen_movi_i32(cpu_flags, ctx->envflags & ~TB_FLAG_GUSA_MASK); in gen_conditional_jump()
286 ctx->base.is_jmp = DISAS_NEXT; in gen_conditional_jump()
294 gen_goto_tb(ctx, 1, ctx->base.pc_next + 2); in gen_conditional_jump()
295 ctx->base.is_jmp = DISAS_NORETURN; in gen_conditional_jump()
307 if (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE) { in gen_delayed_conditional_jump()
314 tcg_gen_movi_i32(cpu_flags, ctx->envflags & ~TB_FLAG_GUSA_MASK); in gen_delayed_conditional_jump()
318 ctx->base.is_jmp = DISAS_NEXT; in gen_delayed_conditional_jump()
323 gen_goto_tb(ctx, 1, ctx->base.pc_next + 2); in gen_delayed_conditional_jump()
332 reg ^= ctx->fbank; in gen_load_fpr64()
340 reg ^= ctx->fbank; in gen_store_fpr64()
344 #define B3_0 (ctx->opcode & 0xf)
345 #define B6_4 ((ctx->opcode >> 4) & 0x7)
346 #define B7_4 ((ctx->opcode >> 4) & 0xf)
347 #define B7_0 (ctx->opcode & 0xff)
348 #define B7_0s ((int32_t) (int8_t) (ctx->opcode & 0xff))
349 #define B11_0s (ctx->opcode & 0x800 ? 0xfffff000 | (ctx->opcode & 0xfff) : \
350 (ctx->opcode & 0xfff))
351 #define B11_8 ((ctx->opcode >> 8) & 0xf)
352 #define B15_12 ((ctx->opcode >> 12) & 0xf)
354 #define REG(x) cpu_gregs[(x) ^ ctx->gbank]
355 #define ALTREG(x) cpu_gregs[(x) ^ ctx->gbank ^ 0x10]
356 #define FREG(x) cpu_fregs[(x) ^ ctx->fbank]
361 if (ctx->envflags & TB_FLAG_DELAY_SLOT_MASK) { \
371 if (ctx->tbflags & (1u << SR_FD)) { \
376 if (ctx->tbflags & FPSCR_PR) { \
381 if (!(ctx->tbflags & FPSCR_PR)) { \
386 if (!(ctx->features & SH_FEATURE_SH4A)) { \
396 - in memcpy, where data is copied in blocks, the first write in _decode_opc()
398 - in arch/sh/mm/cache-sh4.c, movcal.l + ocbi combination is used in _decode_opc()
412 if (ctx->has_movcal) in _decode_opc()
414 int opcode = ctx->opcode & 0xf0ff; in _decode_opc()
419 ctx->has_movcal = 0; in _decode_opc()
424 fprintf(stderr, "Translating opcode 0x%04x\n", ctx->opcode); in _decode_opc()
427 switch (ctx->opcode) { in _decode_opc()
436 ctx->envflags |= TB_FLAG_DELAY_SLOT; in _decode_opc()
437 ctx->delayed_pc = (uint32_t) - 1; in _decode_opc()
458 ctx->envflags |= TB_FLAG_DELAY_SLOT_RTE; in _decode_opc()
459 ctx->delayed_pc = (uint32_t) - 1; in _decode_opc()
460 ctx->base.is_jmp = DISAS_STOP; in _decode_opc()
471 ctx->base.is_jmp = DISAS_STOP; in _decode_opc()
476 ctx->base.is_jmp = DISAS_STOP; in _decode_opc()
481 ctx->base.is_jmp = DISAS_STOP; in _decode_opc()
487 tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next + 2); in _decode_opc()
492 switch (ctx->opcode & 0xf000) { in _decode_opc()
497 tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, in _decode_opc()
505 tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, in _decode_opc()
512 * Detect the start of a gUSA region (mov #-n, r15). in _decode_opc()
517 (tb_cflags(ctx->base.tb) & CF_PARALLEL)) { in _decode_opc()
518 ctx->envflags = in _decode_opc()
519 deposit32(ctx->envflags, TB_FLAG_GUSA_SHIFT, 8, B7_0s); in _decode_opc()
520 ctx->base.is_jmp = DISAS_STOP; in _decode_opc()
528 TCGv addr = tcg_constant_i32(ctx->base.pc_next + 4 + B7_0 * 2); in _decode_opc()
529 tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, in _decode_opc()
536 TCGv addr = tcg_constant_i32((ctx->base.pc_next + 4 + B7_0 * 4) & ~3); in _decode_opc()
537 tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, in _decode_opc()
546 ctx->delayed_pc = ctx->base.pc_next + 4 + B11_0s * 2; in _decode_opc()
547 ctx->envflags |= TB_FLAG_DELAY_SLOT; in _decode_opc()
551 tcg_gen_movi_i32(cpu_pr, ctx->base.pc_next + 4); in _decode_opc()
552 ctx->delayed_pc = ctx->base.pc_next + 4 + B11_0s * 2; in _decode_opc()
553 ctx->envflags |= TB_FLAG_DELAY_SLOT; in _decode_opc()
557 switch (ctx->opcode & 0xf00f) { in _decode_opc()
562 tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_UB); in _decode_opc()
565 tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, in _decode_opc()
569 tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, in _decode_opc()
573 tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_SB); in _decode_opc()
576 tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, in _decode_opc()
580 tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, in _decode_opc()
583 case 0x2004: /* mov.b Rm,@-Rn */ in _decode_opc()
587 /* might cause re-execution */ in _decode_opc()
588 tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_UB); in _decode_opc()
592 case 0x2005: /* mov.w Rm,@-Rn */ in _decode_opc()
596 tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, in _decode_opc()
601 case 0x2006: /* mov.l Rm,@-Rn */ in _decode_opc()
605 tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, in _decode_opc()
611 tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_SB); in _decode_opc()
616 tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, in _decode_opc()
622 tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, in _decode_opc()
631 tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_UB); in _decode_opc()
638 tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, in _decode_opc()
646 tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, in _decode_opc()
654 tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_SB); in _decode_opc()
661 tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, in _decode_opc()
669 tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, in _decode_opc()
766 using 64-bit temps, we compute arg0's high part from q ^ m, so in _decode_opc()
804 tcg_gen_qemu_ld_i32(arg0, REG(B7_4), ctx->memidx, in _decode_opc()
807 tcg_gen_qemu_ld_i32(arg1, REG(B11_8), ctx->memidx, in _decode_opc()
818 tcg_gen_qemu_ld_i32(arg0, REG(B7_4), ctx->memidx, in _decode_opc()
821 tcg_gen_qemu_ld_i32(arg1, REG(B11_8), ctx->memidx, in _decode_opc()
882 correctly handle the -32 case */ in _decode_opc()
904 correctly handle the -32 case */ in _decode_opc()
956 case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */ in _decode_opc()
958 if (ctx->tbflags & FPSCR_SZ) { in _decode_opc()
967 case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */ in _decode_opc()
969 if (ctx->tbflags & FPSCR_SZ) { in _decode_opc()
972 tcg_gen_qemu_st_i64(fp, REG(B11_8), ctx->memidx, in _decode_opc()
975 tcg_gen_qemu_st_i32(FREG(B7_4), REG(B11_8), ctx->memidx, in _decode_opc()
979 case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */ in _decode_opc()
981 if (ctx->tbflags & FPSCR_SZ) { in _decode_opc()
983 tcg_gen_qemu_ld_i64(fp, REG(B7_4), ctx->memidx, in _decode_opc()
987 tcg_gen_qemu_ld_i32(FREG(B11_8), REG(B7_4), ctx->memidx, in _decode_opc()
991 case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */ in _decode_opc()
993 if (ctx->tbflags & FPSCR_SZ) { in _decode_opc()
995 tcg_gen_qemu_ld_i64(fp, REG(B7_4), ctx->memidx, in _decode_opc()
1000 tcg_gen_qemu_ld_i32(FREG(B11_8), REG(B7_4), ctx->memidx, in _decode_opc()
1005 case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */ in _decode_opc()
1009 if (ctx->tbflags & FPSCR_SZ) { in _decode_opc()
1013 tcg_gen_qemu_st_i64(fp, addr, ctx->memidx, in _decode_opc()
1017 tcg_gen_qemu_st_i32(FREG(B7_4), addr, ctx->memidx, in _decode_opc()
1023 case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */ in _decode_opc()
1028 if (ctx->tbflags & FPSCR_SZ) { in _decode_opc()
1030 tcg_gen_qemu_ld_i64(fp, addr, ctx->memidx, in _decode_opc()
1034 tcg_gen_qemu_ld_i32(FREG(B11_8), addr, ctx->memidx, in _decode_opc()
1039 case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */ in _decode_opc()
1044 if (ctx->tbflags & FPSCR_SZ) { in _decode_opc()
1047 tcg_gen_qemu_st_i64(fp, addr, ctx->memidx, in _decode_opc()
1050 tcg_gen_qemu_st_i32(FREG(B7_4), addr, ctx->memidx, in _decode_opc()
1055 case 0xf000: /* fadd Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ in _decode_opc()
1056 case 0xf001: /* fsub Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ in _decode_opc()
1057 case 0xf002: /* fmul Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ in _decode_opc()
1058 case 0xf003: /* fdiv Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ in _decode_opc()
1059 case 0xf004: /* fcmp/eq Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ in _decode_opc()
1060 case 0xf005: /* fcmp/gt Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ in _decode_opc()
1063 if (ctx->tbflags & FPSCR_PR) { in _decode_opc()
1066 if (ctx->opcode & 0x0110) { in _decode_opc()
1073 switch (ctx->opcode & 0xf00f) { in _decode_opc()
1095 switch (ctx->opcode & 0xf00f) { in _decode_opc()
1132 switch (ctx->opcode & 0xff00) { in _decode_opc()
1142 tcg_gen_qemu_ld_i32(val, addr, ctx->memidx, MO_UB); in _decode_opc()
1144 tcg_gen_qemu_st_i32(val, addr, ctx->memidx, MO_UB); in _decode_opc()
1149 gen_conditional_jump(ctx, ctx->base.pc_next + 4 + B7_0s * 2, false); in _decode_opc()
1154 ctx->delayed_pc = ctx->base.pc_next + 4 + B7_0s * 2; in _decode_opc()
1155 ctx->envflags |= TB_FLAG_DELAY_SLOT_COND; in _decode_opc()
1159 gen_conditional_jump(ctx, ctx->base.pc_next + 4 + B7_0s * 2, true); in _decode_opc()
1164 ctx->delayed_pc = ctx->base.pc_next + 4 + B7_0s * 2; in _decode_opc()
1165 ctx->envflags |= TB_FLAG_DELAY_SLOT_COND; in _decode_opc()
1174 tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_SB); in _decode_opc()
1181 tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_TESW | MO_ALIGN); in _decode_opc()
1188 tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_TESL | MO_ALIGN); in _decode_opc()
1195 tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_UB); in _decode_opc()
1202 tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_TEUW | MO_ALIGN); in _decode_opc()
1209 tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_TEUL | MO_ALIGN); in _decode_opc()
1216 tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_UB); in _decode_opc()
1223 tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, in _decode_opc()
1231 tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_SB); in _decode_opc()
1238 tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, in _decode_opc()
1244 tcg_gen_movi_i32(REG(0), ((ctx->base.pc_next & 0xfffffffc) + in _decode_opc()
1256 tcg_gen_qemu_ld_i32(val, addr, ctx->memidx, MO_UB); in _decode_opc()
1258 tcg_gen_qemu_st_i32(val, addr, ctx->memidx, MO_UB); in _decode_opc()
1268 ctx->base.is_jmp = DISAS_NORETURN; in _decode_opc()
1282 tcg_gen_qemu_ld_i32(val, val, ctx->memidx, MO_UB); in _decode_opc()
1296 tcg_gen_qemu_ld_i32(val, addr, ctx->memidx, MO_UB); in _decode_opc()
1298 tcg_gen_qemu_st_i32(val, addr, ctx->memidx, MO_UB); in _decode_opc()
1303 switch (ctx->opcode & 0xf08f) { in _decode_opc()
1310 tcg_gen_qemu_ld_i32(ALTREG(B6_4), REG(B11_8), ctx->memidx, in _decode_opc()
1318 case 0x4083: /* stc.l Rm_BANK,@-Rn */ in _decode_opc()
1323 tcg_gen_qemu_st_i32(ALTREG(B6_4), addr, ctx->memidx, in _decode_opc()
1330 switch (ctx->opcode & 0xf0ff) { in _decode_opc()
1333 tcg_gen_addi_i32(cpu_delayed_pc, REG(B11_8), ctx->base.pc_next + 4); in _decode_opc()
1334 ctx->envflags |= TB_FLAG_DELAY_SLOT; in _decode_opc()
1335 ctx->delayed_pc = (uint32_t) - 1; in _decode_opc()
1339 tcg_gen_movi_i32(cpu_pr, ctx->base.pc_next + 4); in _decode_opc()
1341 ctx->envflags |= TB_FLAG_DELAY_SLOT; in _decode_opc()
1342 ctx->delayed_pc = (uint32_t) - 1; in _decode_opc()
1357 ctx->envflags |= TB_FLAG_DELAY_SLOT; in _decode_opc()
1358 ctx->delayed_pc = (uint32_t) - 1; in _decode_opc()
1362 tcg_gen_movi_i32(cpu_pr, ctx->base.pc_next + 4); in _decode_opc()
1364 ctx->envflags |= TB_FLAG_DELAY_SLOT; in _decode_opc()
1365 ctx->delayed_pc = (uint32_t) - 1; in _decode_opc()
1373 ctx->base.is_jmp = DISAS_STOP; in _decode_opc()
1380 tcg_gen_qemu_ld_i32(val, REG(B11_8), ctx->memidx, in _decode_opc()
1385 ctx->base.is_jmp = DISAS_STOP; in _decode_opc()
1392 case 0x4003: /* stc SR,@-Rn */ in _decode_opc()
1399 tcg_gen_qemu_st_i32(val, addr, ctx->memidx, MO_TEUL | MO_ALIGN); in _decode_opc()
1410 tcg_gen_qemu_ld_i32(cpu_##reg, REG(B11_8), ctx->memidx, \ in _decode_opc()
1424 tcg_gen_qemu_st_i32(cpu_##reg, addr, ctx->memidx, \ in _decode_opc()
1441 LDST(pr, 0x402a, 0x4026, 0x002a, 0x4022, {}) in _decode_opc()
1446 ctx->base.is_jmp = DISAS_STOP; in _decode_opc()
1452 tcg_gen_qemu_ld_i32(addr, REG(B11_8), ctx->memidx, in _decode_opc()
1456 ctx->base.is_jmp = DISAS_STOP; in _decode_opc()
1463 case 0x4062: /* sts FPSCR,@-Rn */ in _decode_opc()
1471 tcg_gen_qemu_st_i32(val, addr, ctx->memidx, MO_TEUL | MO_ALIGN); in _decode_opc()
1478 tcg_gen_qemu_ld_i32(val, REG(B11_8), ctx->memidx, in _decode_opc()
1481 tcg_gen_qemu_st_i32(REG(0), REG(B11_8), ctx->memidx, in _decode_opc()
1484 ctx->has_movcal = 1; in _decode_opc()
1488 /* Load non-boundary-aligned data */ in _decode_opc()
1489 tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, in _decode_opc()
1494 /* Load non-boundary-aligned data */ in _decode_opc()
1495 tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, in _decode_opc()
1504 * LDST -> T in _decode_opc()
1505 * If (T == 1) R0 -> (Rn) in _decode_opc()
1506 * 0 -> LDST in _decode_opc()
1509 * Since we currently support no smp boards, this implies user-mode. in _decode_opc()
1510 * But we can still support the official mechanism while user-mode in _decode_opc()
1511 * is single-threaded. */ in _decode_opc()
1517 if ((tb_cflags(ctx->base.tb) & CF_PARALLEL)) { in _decode_opc()
1524 REG(0), ctx->memidx, in _decode_opc()
1528 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_lock_addr, -1, fail); in _decode_opc()
1529 tcg_gen_qemu_st_i32(REG(0), REG(B11_8), ctx->memidx, in _decode_opc()
1539 tcg_gen_movi_i32(cpu_lock_addr, -1); in _decode_opc()
1544 * 1 -> LDST in _decode_opc()
1545 * (Rm) -> R0 in _decode_opc()
1547 * occurred 0 -> LDST in _decode_opc()
1552 if ((tb_cflags(ctx->base.tb) & CF_PARALLEL)) { in _decode_opc()
1555 tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, in _decode_opc()
1560 tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, in _decode_opc()
1647 tcg_constant_i32(0x80), ctx->memidx, MO_UB); in _decode_opc()
1650 case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */ in _decode_opc()
1654 case 0xf01d: /* flds FRm,FPUL - FPSCR: Nothing */ in _decode_opc()
1658 case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */ in _decode_opc()
1660 if (ctx->tbflags & FPSCR_PR) { in _decode_opc()
1662 if (ctx->opcode & 0x0100) { in _decode_opc()
1673 case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ in _decode_opc()
1675 if (ctx->tbflags & FPSCR_PR) { in _decode_opc()
1677 if (ctx->opcode & 0x0100) { in _decode_opc()
1688 case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */ in _decode_opc()
1692 case 0xf05d: /* fabs FRn/DRn - FPCSR: Nothing */ in _decode_opc()
1698 if (ctx->tbflags & FPSCR_PR) { in _decode_opc()
1699 if (ctx->opcode & 0x0100) { in _decode_opc()
1715 case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */ in _decode_opc()
1720 case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */ in _decode_opc()
1745 TCGv m = tcg_constant_i32((ctx->opcode >> 8) & 3); in _decode_opc()
1746 TCGv n = tcg_constant_i32((ctx->opcode >> 10) & 3); in _decode_opc()
1755 if ((ctx->opcode & 0x0300) != 0x0100) { in _decode_opc()
1758 TCGv n = tcg_constant_i32((ctx->opcode >> 10) & 3); in _decode_opc()
1766 ctx->opcode, ctx->base.pc_next); in _decode_opc()
1770 if (ctx->envflags & TB_FLAG_DELAY_SLOT_MASK) { in _decode_opc()
1778 ctx->base.is_jmp = DISAS_NORETURN; in _decode_opc()
1783 if (ctx->envflags & TB_FLAG_DELAY_SLOT_MASK) { in _decode_opc()
1788 ctx->base.is_jmp = DISAS_NORETURN; in _decode_opc()
1793 uint32_t old_flags = ctx->envflags; in decode_opc()
1799 ctx->envflags &= ~TB_FLAG_DELAY_SLOT_MASK; in decode_opc()
1803 if (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE in decode_opc()
1810 ctx->envflags &= ~TB_FLAG_GUSA_MASK; in decode_opc()
1812 tcg_gen_movi_i32(cpu_flags, ctx->envflags); in decode_opc()
1824 * cpu_exec_step_atomic holding the exclusive lock.
1828 ctx->envflags |= TB_FLAG_GUSA_EXCLUSIVE; in gen_restart_exclusive()
1831 ctx->base.is_jmp = DISAS_NORETURN; in gen_restart_exclusive()
1839 the normal start of such a sequence (mov #-x,r15). While we can handle
1850 uint32_t pc = ctx->base.pc_next; in decode_gusa()
1851 uint32_t pc_end = ctx->base.tb->cs_base; in decode_gusa()
1852 int max_insns = (pc_end - pc) / 2; in decode_gusa()
1863 insns[i] = translator_lduw(env, &ctx->base, pc + i * 2); in decode_gusa()
1866 ld_adr = ld_dst = ld_mop = -1; in decode_gusa()
1867 mv_src = -1; in decode_gusa()
1868 op_dst = op_src = op_opc = -1; in decode_gusa()
1869 mt_dst = -1; in decode_gusa()
1870 st_src = st_mop = -1; in decode_gusa()
1875 do { if (i >= max_insns) goto fail; ctx->opcode = insns[i++]; } while (0) in decode_gusa()
1881 switch (ctx->opcode & 0xf00f) { in decode_gusa()
1899 /* Unless we see a mov, any two-operand operation must use ld_dst. */ in decode_gusa()
1906 switch (ctx->opcode & 0xf00f) { in decode_gusa()
1926 /* Put back and re-examine as operation. */ in decode_gusa()
1927 --i; in decode_gusa()
1934 switch (ctx->opcode & 0xf00f) { in decode_gusa()
1973 op_arg = tcg_constant_i32(-1); in decode_gusa()
1985 /* Looking for the middle of a compare-and-swap sequence, in decode_gusa()
1996 switch (ctx->opcode & 0xff00) { in decode_gusa()
2002 if ((ctx->opcode & 0xff00) == 0x8b00) { /* bf label */ in decode_gusa()
2009 if ((ctx->opcode & 0xf0ff) == 0x0029) { /* movt Rn */ in decode_gusa()
2022 /* Looking for a compare-and-swap against zero. */ in decode_gusa()
2030 if ((ctx->opcode & 0xff00) != 0x8900 /* bt label */ in decode_gusa()
2037 /* Put back and re-examine as store. */ in decode_gusa()
2038 --i; in decode_gusa()
2045 if (i != max_insns - 1) { in decode_gusa()
2049 switch (ctx->opcode & 0xf00f) { in decode_gusa()
2074 case -1: in decode_gusa()
2080 ctx->memidx, ld_mop); in decode_gusa()
2089 op_arg, ctx->memidx, ld_mop); in decode_gusa()
2092 op_arg, ctx->memidx, ld_mop); in decode_gusa()
2107 op_arg, ctx->memidx, ld_mop); in decode_gusa()
2110 op_arg, ctx->memidx, ld_mop); in decode_gusa()
2121 op_arg, ctx->memidx, ld_mop); in decode_gusa()
2124 op_arg, ctx->memidx, ld_mop); in decode_gusa()
2135 op_arg, ctx->memidx, ld_mop); in decode_gusa()
2138 op_arg, ctx->memidx, ld_mop); in decode_gusa()
2148 REG(st_src), ctx->memidx, ld_mop); in decode_gusa()
2160 ctx->envflags &= ~TB_FLAG_GUSA_MASK; in decode_gusa()
2164 qemu_log_mask(LOG_UNIMP, "Unrecognized gUSA sequence %08x-%08x\n", in decode_gusa()
2171 entire region consumed via ctx->base.pc_next so that it's immediately in decode_gusa()
2175 ctx->base.pc_next = pc_end; in decode_gusa()
2176 ctx->base.num_insns += max_insns - 1; in decode_gusa()
2181 * tb->icount * insn_start. in decode_gusa()
2184 tcg_gen_insn_start(pc + i * 2, ctx->envflags); in decode_gusa()
2185 ctx->base.insn_start = tcg_last_op(); in decode_gusa()
2196 ctx->tbflags = tbflags = ctx->base.tb->flags; in sh4_tr_init_disas_context()
2197 ctx->envflags = tbflags & TB_FLAG_ENVFLAGS_MASK; in sh4_tr_init_disas_context()
2198 ctx->memidx = (tbflags & (1u << SR_MD)) == 0 ? 1 : 0; in sh4_tr_init_disas_context()
2201 ctx->delayed_pc = -1; /* use delayed pc from env pointer */ in sh4_tr_init_disas_context()
2202 ctx->features = cpu_env(cs)->features; in sh4_tr_init_disas_context()
2203 ctx->has_movcal = (tbflags & TB_FLAG_PENDING_MOVCA); in sh4_tr_init_disas_context()
2204 ctx->gbank = ((tbflags & (1 << SR_MD)) && in sh4_tr_init_disas_context()
2206 ctx->fbank = tbflags & FPSCR_FR ? 0x10 : 0; in sh4_tr_init_disas_context()
2211 uint32_t pc = ctx->base.pc_next; in sh4_tr_init_disas_context()
2212 uint32_t pc_end = ctx->base.tb->cs_base; in sh4_tr_init_disas_context()
2213 int backup = sextract32(ctx->tbflags, TB_FLAG_GUSA_SHIFT, 8); in sh4_tr_init_disas_context()
2214 int max_insns = (pc_end - pc) / 2; in sh4_tr_init_disas_context()
2219 ctx->envflags &= ~TB_FLAG_GUSA_MASK; in sh4_tr_init_disas_context()
2221 /* Regardless of single-stepping or the end of the page, in sh4_tr_init_disas_context()
2223 holding the exclusive lock. */ in sh4_tr_init_disas_context()
2224 ctx->base.max_insns = max_insns; in sh4_tr_init_disas_context()
2230 /* Since the ISA is fixed-width, we can bound by the number in sh4_tr_init_disas_context()
2232 bound = -(ctx->base.pc_next | TARGET_PAGE_MASK) / 2; in sh4_tr_init_disas_context()
2233 ctx->base.max_insns = MIN(ctx->base.max_insns, bound); in sh4_tr_init_disas_context()
2244 tcg_gen_insn_start(ctx->base.pc_next, ctx->envflags); in sh4_tr_insn_start()
2253 if (unlikely(ctx->envflags & TB_FLAG_GUSA_MASK) in sh4_tr_translate_insn()
2254 && !(ctx->envflags & TB_FLAG_GUSA_EXCLUSIVE)) { in sh4_tr_translate_insn()
2265 if (ctx->base.plugin_enabled) { in sh4_tr_translate_insn()
2267 ctx->base.pc_next += 2; in sh4_tr_translate_insn()
2275 ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next); in sh4_tr_translate_insn()
2277 ctx->base.pc_next += 2; in sh4_tr_translate_insn()
2284 if (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE) { in sh4_tr_tb_stop()
2286 ctx->envflags &= ~TB_FLAG_GUSA_MASK; in sh4_tr_tb_stop()
2289 switch (ctx->base.is_jmp) { in sh4_tr_tb_stop()
2297 gen_goto_tb(ctx, 0, ctx->base.pc_next); in sh4_tr_tb_stop()