Lines Matching full:always

217         qemu_log_mask(LOG_UNIMP, "%s bit is always zero\n", msg);  in warn_always_zero_bit()
232         /* Validate unimplemented (always zero) bits */  in textra_validate()
244         /* Validate unimplemented (always zero) bits */  in textra_validate()
448     /* validate unimplemented (always zero) bits */  in type2_mcontrol_validate()
576     /* validate unimplemented (always zero) bits */  in type6_mcontrol6_validate()
806     /* validate unimplemented (always zero) bits */  in itrigger_validate()
1067          * maskmax = 0 (unimplemented, always 0)  in riscv_trigger_reset_hold()
1069          * hit = 0 (unimplemented, always 0)  in riscv_trigger_reset_hold()
1070          * select = 0 (always 0, perform match on address)  in riscv_trigger_reset_hold()
1071          * timing = 0 (always 0, trigger before instruction)  in riscv_trigger_reset_hold()
1073          * action = 0 (always 0, raise a breakpoint exception)  in riscv_trigger_reset_hold()
1074          * chain = 0 (unimplemented, always 0)  in riscv_trigger_reset_hold()
1075          * match = 0 (always 0, when any compare value equals tdata2)  in riscv_trigger_reset_hold()