Lines Matching refs:wr_mask
1433 target_ulong wr_mask) in rmw_cd_mhpmcounter() argument
1435 if (wr_mask != 0 && wr_mask != -1) { in rmw_cd_mhpmcounter()
1439 if (!wr_mask && val) { in rmw_cd_mhpmcounter()
1441 } else if (wr_mask) { in rmw_cd_mhpmcounter()
1452 target_ulong wr_mask) in rmw_cd_mhpmcounterh() argument
1454 if (wr_mask != 0 && wr_mask != -1) { in rmw_cd_mhpmcounterh()
1458 if (!wr_mask && val) { in rmw_cd_mhpmcounterh()
1460 } else if (wr_mask) { in rmw_cd_mhpmcounterh()
1471 target_ulong wr_mask) in rmw_cd_mhpmevent() argument
1475 if (wr_mask != 0 && wr_mask != -1) { in rmw_cd_mhpmevent()
1479 if (!wr_mask && val) { in rmw_cd_mhpmevent()
1484 } else if (wr_mask) { in rmw_cd_mhpmevent()
1485 wr_mask &= ~MHPMEVENT_BIT_MINH; in rmw_cd_mhpmevent()
1486 mhpmevt_val = (new_val & wr_mask) | in rmw_cd_mhpmevent()
1487 (env->mhpmevent_val[evt_index] & ~wr_mask); in rmw_cd_mhpmevent()
1503 target_ulong wr_mask) in rmw_cd_mhpmeventh() argument
1508 if (wr_mask != 0 && wr_mask != -1) { in rmw_cd_mhpmeventh()
1512 if (!wr_mask && val) { in rmw_cd_mhpmeventh()
1517 } else if (wr_mask) { in rmw_cd_mhpmeventh()
1518 wr_mask &= ~MHPMEVENTH_BIT_MINH; in rmw_cd_mhpmeventh()
1520 (new_val & wr_mask) | (env->mhpmeventh_val[evt_index] & ~wr_mask); in rmw_cd_mhpmeventh()
1532 target_ulong new_val, target_ulong wr_mask) in rmw_cd_ctr_cfg() argument
1536 if (wr_mask) { in rmw_cd_ctr_cfg()
1537 wr_mask &= ~MCYCLECFG_BIT_MINH; in rmw_cd_ctr_cfg()
1538 env->mcyclecfg = (new_val & wr_mask) | (env->mcyclecfg & ~wr_mask); in rmw_cd_ctr_cfg()
1544 if (wr_mask) { in rmw_cd_ctr_cfg()
1545 wr_mask &= ~MINSTRETCFG_BIT_MINH; in rmw_cd_ctr_cfg()
1546 env->minstretcfg = (new_val & wr_mask) | in rmw_cd_ctr_cfg()
1547 (env->minstretcfg & ~wr_mask); in rmw_cd_ctr_cfg()
1559 target_ulong new_val, target_ulong wr_mask) in rmw_cd_ctr_cfgh() argument
1568 if (wr_mask) { in rmw_cd_ctr_cfgh()
1569 wr_mask &= ~MCYCLECFGH_BIT_MINH; in rmw_cd_ctr_cfgh()
1570 env->mcyclecfgh = (new_val & wr_mask) | in rmw_cd_ctr_cfgh()
1571 (env->mcyclecfgh & ~wr_mask); in rmw_cd_ctr_cfgh()
1577 if (wr_mask) { in rmw_cd_ctr_cfgh()
1578 wr_mask &= ~MINSTRETCFGH_BIT_MINH; in rmw_cd_ctr_cfgh()
1579 env->minstretcfgh = (new_val & wr_mask) | in rmw_cd_ctr_cfgh()
1580 (env->minstretcfgh & ~wr_mask); in rmw_cd_ctr_cfgh()
2192 uint64_t new_val, uint64_t wr_mask) in rmw_mideleg64() argument
2194 uint64_t mask = wr_mask & delegable_ints; in rmw_mideleg64()
2211 target_ulong new_val, target_ulong wr_mask) in rmw_mideleg() argument
2216 ret = rmw_mideleg64(env, csrno, &rval, new_val, wr_mask); in rmw_mideleg()
2227 target_ulong wr_mask) in rmw_midelegh() argument
2233 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); in rmw_midelegh()
2243 uint64_t new_val, uint64_t wr_mask) in rmw_mie64() argument
2245 uint64_t mask = wr_mask & all_ints; in rmw_mie64()
2262 target_ulong new_val, target_ulong wr_mask) in rmw_mie() argument
2267 ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask); in rmw_mie()
2277 target_ulong new_val, target_ulong wr_mask) in rmw_mieh() argument
2283 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); in rmw_mieh()
2293 uint64_t new_val, uint64_t wr_mask) in rmw_mvien64() argument
2295 uint64_t mask = wr_mask & mvien_writable_mask; in rmw_mvien64()
2308 target_ulong new_val, target_ulong wr_mask) in rmw_mvien() argument
2313 ret = rmw_mvien64(env, csrno, &rval, new_val, wr_mask); in rmw_mvien()
2323 target_ulong new_val, target_ulong wr_mask) in rmw_mvienh() argument
2329 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); in rmw_mvienh()
2401 target_ulong wr_mask) in rmw_xiselect() argument
2434 wr_mask &= ISELECT_MASK_SXCSRIND; in rmw_xiselect()
2436 wr_mask &= ISELECT_MASK_AIA; in rmw_xiselect()
2439 if (wr_mask) { in rmw_xiselect()
2440 *iselect = (*iselect & ~wr_mask) | (new_val & wr_mask); in rmw_xiselect()
2467 target_ulong wr_mask, int ext_irq_no) in rmw_iprio() argument
2491 if (wr_mask) { in rmw_iprio()
2492 new_val = (old_val & ~wr_mask) | (new_val & wr_mask); in rmw_iprio()
2510 target_ulong new_val, target_ulong wr_mask) in rmw_ctrsource() argument
2543 env->ctr_src[idx] = (env->ctr_src[idx] & ~wr_mask) | (new_val & wr_mask); in rmw_ctrsource()
2549 target_ulong new_val, target_ulong wr_mask) in rmw_ctrtarget() argument
2582 env->ctr_dst[idx] = (env->ctr_dst[idx] & ~wr_mask) | (new_val & wr_mask); in rmw_ctrtarget()
2588 target_ulong new_val, target_ulong wr_mask) in rmw_ctrdata() argument
2603 const uint64_t mask = wr_mask & CTRDATA_MASK; in rmw_ctrdata()
2629 target_ulong new_val, target_ulong wr_mask) in rmw_xireg_aia() argument
2674 isel, iprio, val, new_val, wr_mask, in rmw_xireg_aia()
2688 val, new_val, wr_mask); in rmw_xireg_aia()
2709 target_ulong new_val, target_ulong wr_mask) in rmw_xireg_cd() argument
2752 ret = rmw_cd_mhpmcounter(env, ctr_index, val, new_val, wr_mask); in rmw_xireg_cd()
2755 ret = rmw_cd_mhpmcounterh(env, ctr_index, val, new_val, wr_mask); in rmw_xireg_cd()
2759 ret = rmw_cd_ctr_cfg(env, ctr_index, val, new_val, wr_mask); in rmw_xireg_cd()
2761 ret = rmw_cd_mhpmevent(env, ctr_index, val, new_val, wr_mask); in rmw_xireg_cd()
2766 ret = rmw_cd_ctr_cfgh(env, ctr_index, val, new_val, wr_mask); in rmw_xireg_cd()
2768 ret = rmw_cd_mhpmeventh(env, ctr_index, val, new_val, wr_mask); in rmw_xireg_cd()
2781 target_ulong new_val, target_ulong wr_mask) in rmw_xireg_ctr() argument
2788 return rmw_ctrsource(env, isel, val, new_val, wr_mask); in rmw_xireg_ctr()
2790 return rmw_ctrtarget(env, isel, val, new_val, wr_mask); in rmw_xireg_ctr()
2792 return rmw_ctrdata(env, isel, val, new_val, wr_mask); in rmw_xireg_ctr()
2809 target_ulong new_val, target_ulong wr_mask) in rmw_xireg_csrind() argument
2815 ret = rmw_xireg_cd(env, csrno, isel, val, new_val, wr_mask); in rmw_xireg_csrind()
2817 ret = rmw_xireg_ctr(env, csrno, isel, val, new_val, wr_mask); in rmw_xireg_csrind()
2835 target_ulong new_val, target_ulong wr_mask) in rmw_xiregi() argument
2861 return rmw_xireg_csrind(env, csrno, isel, val, new_val, wr_mask); in rmw_xiregi()
2866 target_ulong wr_mask) in rmw_xireg() argument
2903 return rmw_xireg_aia(env, csrno, isel, val, new_val, wr_mask); in rmw_xireg()
2906 return rmw_xireg_csrind(env, csrno, isel, val, new_val, wr_mask); in rmw_xireg()
2915 target_ulong wr_mask) in rmw_xtopei() argument
2961 val, new_val, wr_mask); in rmw_xtopei()
3396 uint64_t wr_mask, target_ulong new_val) in write_mstateen() argument
3401 *reg = (*reg & ~wr_mask) | (new_val & wr_mask); in write_mstateen()
3409 uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; in write_mstateen0() local
3411 wr_mask |= SMSTATEEN0_FCSR; in write_mstateen0()
3415 wr_mask |= SMSTATEEN0_P1P13; in write_mstateen0()
3419 wr_mask |= SMSTATEEN0_SVSLCT; in write_mstateen0()
3428 wr_mask |= (SMSTATEEN0_AIA | SMSTATEEN0_IMSIC); in write_mstateen0()
3432 wr_mask |= SMSTATEEN0_CTR; in write_mstateen0()
3435 return write_mstateen(env, csrno, wr_mask, new_val); in write_mstateen0()
3453 uint64_t wr_mask, target_ulong new_val) in write_mstateenh() argument
3460 *reg = (*reg & ~wr_mask) | (val & wr_mask); in write_mstateenh()
3468 uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; in write_mstateen0h() local
3471 wr_mask |= SMSTATEEN0_P1P13; in write_mstateen0h()
3475 wr_mask |= SMSTATEEN0_CTR; in write_mstateen0h()
3478 return write_mstateenh(env, csrno, wr_mask, new_val); in write_mstateen0h()
3501 uint64_t *reg, wr_mask; in write_hstateen() local
3504 wr_mask = env->mstateen[index] & mask; in write_hstateen()
3505 *reg = (*reg & ~wr_mask) | (new_val & wr_mask); in write_hstateen()
3513 uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; in write_hstateen0() local
3516 wr_mask |= SMSTATEEN0_FCSR; in write_hstateen0()
3520 wr_mask |= SMSTATEEN0_SVSLCT; in write_hstateen0()
3529 wr_mask |= (SMSTATEEN0_AIA | SMSTATEEN0_IMSIC); in write_hstateen0()
3533 wr_mask |= SMSTATEEN0_CTR; in write_hstateen0()
3536 return write_hstateen(env, csrno, wr_mask, new_val); in write_hstateen0()
3559 uint64_t *reg, wr_mask, val; in write_hstateenh() local
3564 wr_mask = env->mstateen[index] & mask; in write_hstateenh()
3565 *reg = (*reg & ~wr_mask) | (val & wr_mask); in write_hstateenh()
3573 uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; in write_hstateen0h() local
3576 wr_mask |= SMSTATEEN0_CTR; in write_hstateen0h()
3579 return write_hstateenh(env, csrno, wr_mask, new_val); in write_hstateen0h()
3607 uint64_t wr_mask; in write_sstateen() local
3610 wr_mask = env->mstateen[index] & mask; in write_sstateen()
3612 wr_mask &= env->hstateen[index]; in write_sstateen()
3616 *reg = (*reg & ~wr_mask) | (new_val & wr_mask); in write_sstateen()
3624 uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; in write_sstateen0() local
3627 wr_mask |= SMSTATEEN0_FCSR; in write_sstateen0()
3630 return write_sstateen(env, csrno, wr_mask, new_val); in write_sstateen0()
3641 uint64_t new_val, uint64_t wr_mask) in rmw_mip64() argument
3643 uint64_t old_mip, mask = wr_mask & delegable_ints; in rmw_mip64()
3678 target_ulong new_val, target_ulong wr_mask) in rmw_mip() argument
3683 ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask); in rmw_mip()
3693 target_ulong new_val, target_ulong wr_mask) in rmw_miph() argument
3699 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); in rmw_miph()
3720 uint64_t new_val, uint64_t wr_mask) in rmw_mvip64() argument
3775 wr_mask_mip = wr_mask & alias_mask & mvip_writable_mask; in rmw_mvip64()
3776 wr_mask_mvip = wr_mask & nalias_mask & mvip_writable_mask; in rmw_mvip64()
3815 target_ulong new_val, target_ulong wr_mask) in rmw_mvip() argument
3820 ret = rmw_mvip64(env, csrno, &rval, new_val, wr_mask); in rmw_mvip()
3830 target_ulong new_val, target_ulong wr_mask) in rmw_mviph() argument
3836 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); in rmw_mviph()
3907 uint64_t new_val, uint64_t wr_mask) in rmw_vsie64() argument
3922 vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1); in rmw_vsie64()
3923 wr_mask &= ~(VS_MODE_INTERRUPTS >> 1); in rmw_vsie64()
3924 wr_mask |= vsbits << 1; in rmw_vsie64()
3926 wr_mask_mie = wr_mask & alias_mask; in rmw_vsie64()
3927 wr_mask_vsie = wr_mask & nalias_mask; in rmw_vsie64()
3946 target_ulong new_val, target_ulong wr_mask) in rmw_vsie() argument
3951 ret = rmw_vsie64(env, csrno, &rval, new_val, wr_mask); in rmw_vsie()
3961 target_ulong new_val, target_ulong wr_mask) in rmw_vsieh() argument
3967 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); in rmw_vsieh()
3977 uint64_t new_val, uint64_t wr_mask) in rmw_sie64() argument
3982 uint64_t sie_mask = wr_mask & nalias_mask; in rmw_sie64()
3998 ret = rmw_vsie64(env, CSR_VSIE, ret_val, new_val, wr_mask); in rmw_sie64()
4003 ret = rmw_mie64(env, csrno, ret_val, new_val, wr_mask & alias_mask); in rmw_sie64()
4017 target_ulong new_val, target_ulong wr_mask) in rmw_sie() argument
4022 ret = rmw_sie64(env, csrno, &rval, new_val, wr_mask); in rmw_sie()
4032 target_ulong new_val, target_ulong wr_mask) in rmw_sieh() argument
4038 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); in rmw_sieh()
4157 uint64_t new_val, uint64_t wr_mask);
4161 uint64_t new_val, uint64_t wr_mask) in rmw_vsip64() argument
4174 vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1); in rmw_vsip64()
4175 wr_mask &= ~(VS_MODE_INTERRUPTS >> 1); in rmw_vsip64()
4176 wr_mask |= vsbits << 1; in rmw_vsip64()
4179 wr_mask & mask & vsip_writable_mask); in rmw_vsip64()
4192 target_ulong new_val, target_ulong wr_mask) in rmw_vsip() argument
4197 ret = rmw_vsip64(env, csrno, &rval, new_val, wr_mask); in rmw_vsip()
4207 target_ulong new_val, target_ulong wr_mask) in rmw_vsiph() argument
4213 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); in rmw_vsiph()
4223 uint64_t new_val, uint64_t wr_mask) in rmw_sip64() argument
4232 ret = rmw_vsip64(env, CSR_VSIP, ret_val, new_val, wr_mask); in rmw_sip64()
4234 ret = rmw_mvip64(env, csrno, ret_val, new_val, wr_mask & mask); in rmw_sip64()
4247 target_ulong new_val, target_ulong wr_mask) in rmw_sip() argument
4252 ret = rmw_sip64(env, csrno, &rval, new_val, wr_mask); in rmw_sip()
4262 target_ulong new_val, target_ulong wr_mask) in rmw_siph() argument
4268 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); in rmw_siph()
4301 target_ulong new_val, target_ulong wr_mask) in rmw_sctrdepth() argument
4303 uint64_t mask = wr_mask & SCTRDEPTH_MASK; in rmw_sctrdepth()
4331 target_ulong new_val, target_ulong wr_mask) in rmw_sctrstatus() argument
4334 uint32_t mask = wr_mask & SCTRSTATUS_MASK; in rmw_sctrstatus()
4350 target_ulong new_val, target_ulong wr_mask) in rmw_xctrctl() argument
4352 uint64_t csr_mask, mask = wr_mask; in rmw_xctrctl()
4578 uint64_t new_val, uint64_t wr_mask) in rmw_hvien64() argument
4580 uint64_t mask = wr_mask & hvien_writable_mask; in rmw_hvien64()
4593 target_ulong new_val, target_ulong wr_mask) in rmw_hvien() argument
4598 ret = rmw_hvien64(env, csrno, &rval, new_val, wr_mask); in rmw_hvien()
4608 target_ulong new_val, target_ulong wr_mask) in rmw_hvienh() argument
4614 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); in rmw_hvienh()
4624 uint64_t new_val, uint64_t wr_mask) in rmw_hideleg64() argument
4626 uint64_t mask = wr_mask & vs_delegable_ints; in rmw_hideleg64()
4638 target_ulong new_val, target_ulong wr_mask) in rmw_hideleg() argument
4643 ret = rmw_hideleg64(env, csrno, &rval, new_val, wr_mask); in rmw_hideleg()
4653 target_ulong new_val, target_ulong wr_mask) in rmw_hidelegh() argument
4659 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); in rmw_hidelegh()
4678 uint64_t new_val, uint64_t wr_mask) in rmw_hvip64() argument
4726 wr_mask_hvip = wr_mask & nalias_mask & hvip_writable_mask; in rmw_hvip64()
4727 wr_mask_mip = wr_mask & alias_mask & hvip_writable_mask; in rmw_hvip64()
4762 target_ulong new_val, target_ulong wr_mask) in rmw_hvip() argument
4767 ret = rmw_hvip64(env, csrno, &rval, new_val, wr_mask); in rmw_hvip()
4777 target_ulong new_val, target_ulong wr_mask) in rmw_hviph() argument
4783 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); in rmw_hviph()
4806 target_ulong new_val, target_ulong wr_mask) in rmw_hie() argument
4811 ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & HS_MODE_INTERRUPTS); in rmw_hie()